\r
**/\r
typedef EFI_STATUS\r
-(EFIAPI *EFI_SPI_HC_PROTOCOL_CHIP_SELECT) (\r
+(EFIAPI *EFI_SPI_HC_PROTOCOL_CHIP_SELECT)(\r
IN CONST EFI_SPI_HC_PROTOCOL *This,\r
IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,\r
IN BOOLEAN PinValue\r
\r
**/\r
typedef EFI_STATUS\r
-(EFIAPI *EFI_SPI_HC_PROTOCOL_CLOCK) (\r
+(EFIAPI *EFI_SPI_HC_PROTOCOL_CLOCK)(\r
IN CONST EFI_SPI_HC_PROTOCOL *This,\r
IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,\r
IN UINT32 *ClockHz\r
\r
**/\r
typedef EFI_STATUS\r
-(EFIAPI *EFI_SPI_HC_PROTOCOL_TRANSACTION) (\r
+(EFIAPI *EFI_SPI_HC_PROTOCOL_TRANSACTION)(\r
IN CONST EFI_SPI_HC_PROTOCOL *This,\r
IN EFI_SPI_BUS_TRANSACTION *BusTransaction\r
);\r
/// sending) operation.The SPI host controller must support a 1 - bit bus\r
/// width.\r
///\r
- UINT32 Attributes;\r
+ UINT32 Attributes;\r
\r
///\r
/// Mask of frame sizes which the SPI host controller supports. Frame size of\r
/// N-bits is supported when bit N-1 is set. The host controller must support\r
/// a frame size of 8-bits.\r
///\r
- UINT32 FrameSizeSupportMask;\r
+ UINT32 FrameSizeSupportMask;\r
\r
///\r
/// Maximum transfer size in bytes: 1 - Oxffffffff\r
///\r
- UINT32 MaximumTransferBytes;\r
+ UINT32 MaximumTransferBytes;\r
\r
///\r
/// Assert or deassert the SPI chip select.\r
///\r
- EFI_SPI_HC_PROTOCOL_CHIP_SELECT ChipSelect;\r
+ EFI_SPI_HC_PROTOCOL_CHIP_SELECT ChipSelect;\r
\r
///\r
/// Set up the clock generator to produce the correct clock frequency, phase\r
/// and polarity for a SPI chip.\r
///\r
- EFI_SPI_HC_PROTOCOL_CLOCK Clock;\r
+ EFI_SPI_HC_PROTOCOL_CLOCK Clock;\r
\r
///\r
/// Perform the SPI transaction on the SPI peripheral using the SPI host\r
/// controller.\r
///\r
- EFI_SPI_HC_PROTOCOL_TRANSACTION Transaction;\r
+ EFI_SPI_HC_PROTOCOL_TRANSACTION Transaction;\r
};\r
\r
-extern EFI_GUID gEfiSpiHcProtocolGuid;\r
+extern EFI_GUID gEfiSpiHcProtocolGuid;\r
\r
#endif // __SPI_HC_PROTOCOL_H__\r