**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SPI_IO_PROTOCOL_TRANSACTION) (\r
+(EFIAPI *EFI_SPI_IO_PROTOCOL_TRANSACTION)(\r
IN CONST EFI_SPI_IO_PROTOCOL *This,\r
IN EFI_SPI_TRANSACTION_TYPE TransactionType,\r
IN BOOLEAN DebugTransaction,\r
\r
**/\r
typedef EFI_STATUS\r
-(EFIAPI *EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL) (\r
+(EFIAPI *EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL)(\r
IN CONST EFI_SPI_IO_PROTOCOL *This,\r
IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral\r
);\r
///\r
/// Pointer to the SPI peripheral being manipulated.\r
///\r
- CONST EFI_SPI_PERIPHERAL *SpiPeripheral;\r
+ CONST EFI_SPI_PERIPHERAL *SpiPeripheral;\r
\r
///\r
/// Type of transaction specified by one of the EFI_SPI_TRANSACTION_TYPE\r
/// values.\r
///\r
- EFI_SPI_TRANSACTION_TYPE TransactionType;\r
+ EFI_SPI_TRANSACTION_TYPE TransactionType;\r
\r
///\r
/// TRUE if the transaction is being debugged. Debugging may be turned on for\r
/// messages. All other transactions with this value set to FALSE will not\r
/// display any debugging messages.\r
///\r
- BOOLEAN DebugTransaction;\r
+ BOOLEAN DebugTransaction;\r
\r
///\r
/// SPI bus width in bits: 1, 2, 4\r
///\r
- UINT32 BusWidth;\r
+ UINT32 BusWidth;\r
\r
///\r
/// Frame size in bits, range: 1 - 32\r
///\r
- UINT32 FrameSize;\r
+ UINT32 FrameSize;\r
\r
///\r
/// Length of the write buffer in bytes\r
///\r
- UINT32 WriteBytes;\r
+ UINT32 WriteBytes;\r
\r
///\r
/// Buffer containing data to send to the SPI peripheral\r
/// Frame sizes 1 - 8 bits: UINT8 (one byte) per frame\r
/// Frame sizes 7 - 16 bits : UINT16 (two bytes) per frame\r
///\r
- UINT8 *WriteBuffer;\r
+ UINT8 *WriteBuffer;\r
\r
///\r
/// Length of the read buffer in bytes\r
///\r
- UINT32 ReadBytes;\r
+ UINT32 ReadBytes;\r
\r
///\r
/// Buffer to receive the data from the SPI peripheral\r
/// * Frame sizes 7 - 16 bits : UINT16 (two bytes) per frame\r
/// * Frame sizes 17 - 32 bits : UINT32 (four bytes) per frame\r
///\r
- UINT8 *ReadBuffer;\r
+ UINT8 *ReadBuffer;\r
} EFI_SPI_BUS_TRANSACTION;\r
\r
///\r
/// Address of an EFI_SPI_PERIPHERAL data structure associated with this\r
/// protocol instance.\r
///\r
- CONST EFI_SPI_PERIPHERAL *SpiPeripheral;\r
+ CONST EFI_SPI_PERIPHERAL *SpiPeripheral;\r
\r
///\r
/// Address of the original EFI_SPI_PERIPHERAL data structure associated with\r
/// this protocol instance.\r
///\r
- CONST EFI_SPI_PERIPHERAL *OriginalSpiPeripheral;\r
+ CONST EFI_SPI_PERIPHERAL *OriginalSpiPeripheral;\r
\r
///\r
/// Mask of frame sizes which the SPI 10 layer supports. Frame size of N-bits\r
/// 8-bit frame sizes by the SPI bus layer if the frame size is not supported\r
/// by the SPI host controller.\r
///\r
- UINT32 FrameSizeSupportMask;\r
+ UINT32 FrameSizeSupportMask;\r
\r
///\r
/// Maximum transfer size in bytes: 1 - Oxffffffff\r
///\r
- UINT32 MaximumTransferBytes;\r
+ UINT32 MaximumTransferBytes;\r
\r
///\r
/// Transaction attributes: One or more from:\r
/// * SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS\r
/// - Transfer size includes the 3 address bytes\r
///\r
- UINT32 Attributes;\r
+ UINT32 Attributes;\r
\r
///\r
/// Pointer to legacy SPI controller protocol\r
///\r
- CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *LegacySpiProtocol;\r
+ CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *LegacySpiProtocol;\r
\r
///\r
/// Initiate a SPI transaction between the host and a SPI peripheral.\r
///\r
- EFI_SPI_IO_PROTOCOL_TRANSACTION Transaction;\r
+ EFI_SPI_IO_PROTOCOL_TRANSACTION Transaction;\r
\r
///\r
/// Update the SPI peripheral associated with this SPI 10 instance.\r
///\r
- EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL UpdateSpiPeripheral;\r
+ EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL UpdateSpiPeripheral;\r
};\r
\r
#endif // __SPI_IO_PROTOCOL_H__\r