AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);\r
@endcode\r
**/\r
-#define CPUID_SIGNATURE 0x00\r
+#define CPUID_SIGNATURE 0x00\r
\r
///\r
/// @{ CPUID signature values returned by Intel processors\r
/// @}\r
///\r
\r
-\r
/**\r
CPUID Version Information\r
\r
AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
@endcode\r
**/\r
-#define CPUID_VERSION_INFO 0x01\r
+#define CPUID_VERSION_INFO 0x01\r
\r
/**\r
CPUID Version Information returned in EAX for CPUID leaf\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID\r
- UINT32 Model:4; ///< [Bits 7:4] Model\r
- UINT32 FamilyId:4; ///< [Bits 11:8] Family\r
- UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type\r
- UINT32 Reserved1:2; ///< [Bits 15:14] Reserved\r
- UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID\r
- UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID\r
- UINT32 Reserved2:4; ///< Reserved\r
+ UINT32 SteppingId : 4; ///< [Bits 3:0] Stepping ID\r
+ UINT32 Model : 4; ///< [Bits 7:4] Model\r
+ UINT32 FamilyId : 4; ///< [Bits 11:8] Family\r
+ UINT32 ProcessorType : 2; ///< [Bits 13:12] Processor Type\r
+ UINT32 Reserved1 : 2; ///< [Bits 15:14] Reserved\r
+ UINT32 ExtendedModelId : 4; ///< [Bits 19:16] Extended Model ID\r
+ UINT32 ExtendedFamilyId : 8; ///< [Bits 27:20] Extended Family ID\r
+ UINT32 Reserved2 : 4; ///< Reserved\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
/// [Bits 7:0] Provides an entry into a brand string table that contains\r
/// brand strings for IA-32 processors.\r
///\r
- UINT32 BrandIndex:8;\r
+ UINT32 BrandIndex : 8;\r
///\r
/// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH\r
/// and CLFLUSHOPT instructions in 8-byte increments. This field was\r
/// introduced in the Pentium 4 processor.\r
///\r
- UINT32 CacheLineSize:8;\r
+ UINT32 CacheLineSize : 8;\r
///\r
/// [Bits 23:16] Maximum number of addressable IDs for logical processors\r
/// in this physical package.\r
/// logical processors in a physical package. This field is only valid if\r
/// CPUID.1.EDX.HTT[bit 28]= 1.\r
///\r
- UINT32 MaximumAddressableIdsForLogicalProcessors:8;\r
+ UINT32 MaximumAddressableIdsForLogicalProcessors : 8;\r
///\r
/// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the\r
/// processor during power up. This field was introduced in the Pentium 4\r
/// processor.\r
///\r
- UINT32 InitialLocalApicId:8;\r
+ UINT32 InitialLocalApicId : 8;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
/// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the\r
/// processor supports this technology\r
///\r
- UINT32 SSE3:1;\r
+ UINT32 SSE3 : 1;\r
///\r
/// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ\r
/// instruction. Carryless Multiplication\r
///\r
- UINT32 PCLMULQDQ:1;\r
+ UINT32 PCLMULQDQ : 1;\r
///\r
/// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports\r
/// DS area using 64-bit layout.\r
///\r
- UINT32 DTES64:1;\r
+ UINT32 DTES64 : 1;\r
///\r
/// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports\r
/// this feature.\r
///\r
- UINT32 MONITOR:1;\r
+ UINT32 MONITOR : 1;\r
///\r
/// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor\r
/// supports the extensions to the Debug Store feature to allow for branch\r
/// message storage qualified by CPL\r
///\r
- UINT32 DS_CPL:1;\r
+ UINT32 DS_CPL : 1;\r
///\r
/// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the\r
/// processor supports this technology.\r
///\r
- UINT32 VMX:1;\r
+ UINT32 VMX : 1;\r
///\r
/// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor\r
/// supports this technology\r
///\r
- UINT32 SMX:1;\r
+ UINT32 SMX : 1;\r
///\r
/// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates\r
/// that the processor supports this technology\r
///\r
- UINT32 EIST:1;\r
+ UINT32 EIST : 1;\r
///\r
/// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor\r
/// supports this technology\r
///\r
- UINT32 TM2:1;\r
+ UINT32 TM2 : 1;\r
///\r
/// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming\r
/// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction\r
/// extensions are not present in the processor.\r
///\r
- UINT32 SSSE3:1;\r
+ UINT32 SSSE3 : 1;\r
///\r
/// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode\r
/// can be set to either adaptive mode or shared mode. A value of 0 indicates\r
/// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR\r
/// Bit 24 (L1 Data Cache Context Mode) for details\r
///\r
- UINT32 CNXT_ID:1;\r
+ UINT32 CNXT_ID : 1;\r
///\r
/// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE\r
/// MSR for silicon debug\r
///\r
- UINT32 SDBG:1;\r
+ UINT32 SDBG : 1;\r
///\r
/// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple\r
/// Add) extensions using YMM state.\r
///\r
- UINT32 FMA:1;\r
+ UINT32 FMA : 1;\r
///\r
/// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature\r
/// is available.\r
///\r
- UINT32 CMPXCHG16B:1;\r
+ UINT32 CMPXCHG16B : 1;\r
///\r
/// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor\r
/// supports changing IA32_MISC_ENABLE[Bit 23].\r
///\r
- UINT32 xTPR_Update_Control:1;\r
+ UINT32 xTPR_Update_Control : 1;\r
///\r
/// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the\r
/// processor supports the performance and debug feature indication MSR\r
/// IA32_PERF_CAPABILITIES.\r
///\r
- UINT32 PDCM:1;\r
- UINT32 Reserved:1;\r
+ UINT32 PDCM : 1;\r
+ UINT32 Reserved : 1;\r
///\r
/// [Bit 17] Process-context identifiers. A value of 1 indicates that the\r
/// processor supports PCIDs and that software may set CR4.PCIDE to 1.\r
///\r
- UINT32 PCID:1;\r
+ UINT32 PCID : 1;\r
///\r
/// [Bit 18] A value of 1 indicates the processor supports the ability to\r
/// prefetch data from a memory mapped device. Direct Cache Access.\r
///\r
- UINT32 DCA:1;\r
+ UINT32 DCA : 1;\r
///\r
/// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.\r
///\r
- UINT32 SSE4_1:1;\r
+ UINT32 SSE4_1 : 1;\r
///\r
/// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.\r
///\r
- UINT32 SSE4_2:1;\r
+ UINT32 SSE4_2 : 1;\r
///\r
/// [Bit 21] A value of 1 indicates that the processor supports x2APIC\r
/// feature.\r
///\r
- UINT32 x2APIC:1;\r
+ UINT32 x2APIC : 1;\r
///\r
/// [Bit 22] A value of 1 indicates that the processor supports MOVBE\r
/// instruction.\r
///\r
- UINT32 MOVBE:1;\r
+ UINT32 MOVBE : 1;\r
///\r
/// [Bit 23] A value of 1 indicates that the processor supports the POPCNT\r
/// instruction.\r
///\r
- UINT32 POPCNT:1;\r
+ UINT32 POPCNT : 1;\r
///\r
/// [Bit 24] A value of 1 indicates that the processor's local APIC timer\r
/// supports one-shot operation using a TSC deadline value.\r
///\r
- UINT32 TSC_Deadline:1;\r
+ UINT32 TSC_Deadline : 1;\r
///\r
/// [Bit 25] A value of 1 indicates that the processor supports the AESNI\r
/// instruction extensions.\r
///\r
- UINT32 AESNI:1;\r
+ UINT32 AESNI : 1;\r
///\r
/// [Bit 26] A value of 1 indicates that the processor supports the\r
/// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV\r
/// instructions, and XCR0.\r
///\r
- UINT32 XSAVE:1;\r
+ UINT32 XSAVE : 1;\r
///\r
/// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]\r
/// to enable XSETBV/XGETBV instructions to access XCR0 and to support\r
/// processor extended state management using XSAVE/XRSTOR.\r
///\r
- UINT32 OSXSAVE:1;\r
+ UINT32 OSXSAVE : 1;\r
///\r
/// [Bit 28] A value of 1 indicates the processor supports the AVX instruction\r
/// extensions.\r
///\r
- UINT32 AVX:1;\r
+ UINT32 AVX : 1;\r
///\r
/// [Bit 29] A value of 1 indicates that processor supports 16-bit\r
/// floating-point conversion instructions.\r
///\r
- UINT32 F16C:1;\r
+ UINT32 F16C : 1;\r
///\r
/// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.\r
///\r
- UINT32 RDRAND:1;\r
+ UINT32 RDRAND : 1;\r
///\r
/// [Bit 31] Always returns 0.\r
///\r
- UINT32 NotUsed:1;\r
+ UINT32 NotUsed : 1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
/// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.\r
///\r
- UINT32 FPU:1;\r
+ UINT32 FPU : 1;\r
///\r
/// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,\r
/// including CR4.VME for controlling the feature, CR4.PVI for protected\r
/// the TSS with the software indirection bitmap, and EFLAGS.VIF and\r
/// EFLAGS.VIP flags.\r
///\r
- UINT32 VME:1;\r
+ UINT32 VME : 1;\r
///\r
/// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including\r
/// CR4.DE for controlling the feature, and optional trapping of accesses to\r
/// DR4 and DR5.\r
///\r
- UINT32 DE:1;\r
+ UINT32 DE : 1;\r
///\r
/// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,\r
/// including CR4.PSE for controlling the feature, the defined dirty bit in\r
/// PDE (Page Directory Entries), optional reserved bit trapping in CR3,\r
/// PDEs, and PTEs.\r
///\r
- UINT32 PSE:1;\r
+ UINT32 PSE : 1;\r
///\r
/// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,\r
/// including CR4.TSD for controlling privilege.\r
///\r
- UINT32 TSC:1;\r
+ UINT32 TSC : 1;\r
///\r
/// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The\r
/// RDMSR and WRMSR instructions are supported. Some of the MSRs are\r
/// implementation dependent.\r
///\r
- UINT32 MSR:1;\r
+ UINT32 MSR : 1;\r
///\r
/// [Bit 6] Physical Address Extension. Physical addresses greater than 32\r
/// bits are supported: extended page table entry formats, an extra level in\r
/// the page translation tables is defined, 2-MByte pages are supported\r
/// instead of 4 Mbyte pages if PAE bit is 1.\r
///\r
- UINT32 PAE:1;\r
+ UINT32 PAE : 1;\r
///\r
/// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine\r
/// Checks, including CR4.MCE for controlling the feature. This feature does\r
/// processing of the exception, or test for the presence of the Machine\r
/// Check feature.\r
///\r
- UINT32 MCE:1;\r
+ UINT32 MCE : 1;\r
///\r
/// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)\r
/// instruction is supported (implicitly locked and atomic).\r
///\r
- UINT32 CX8:1;\r
+ UINT32 CX8 : 1;\r
///\r
/// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable\r
/// Interrupt Controller (APIC), responding to memory mapped commands in the\r
/// physical address range FFFE0000H to FFFE0FFFH (by default - some\r
/// processors permit the APIC to be relocated).\r
///\r
- UINT32 APIC:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 APIC : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT\r
/// and associated MSRs are supported.\r
///\r
- UINT32 SEP:1;\r
+ UINT32 SEP : 1;\r
///\r
/// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap\r
/// MSR contains feature bits that describe what memory types are supported,\r
/// how many variable MTRRs are supported, and whether fixed MTRRs are\r
/// supported.\r
///\r
- UINT32 MTRR:1;\r
+ UINT32 MTRR : 1;\r
///\r
/// [Bit 13] Page Global Bit. The global bit is supported in paging-structure\r
/// entries that map a page, indicating TLB entries that are common to\r
/// different processes and need not be flushed. The CR4.PGE bit controls\r
/// this feature.\r
///\r
- UINT32 PGE:1;\r
+ UINT32 PGE : 1;\r
///\r
/// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine\r
/// Check Architecture of reporting machine errors is supported. The MCG_CAP\r
/// MSR contains feature bits describing how many banks of error reporting\r
/// MSRs are supported.\r
///\r
- UINT32 MCA:1;\r
+ UINT32 MCA : 1;\r
///\r
/// [Bit 15] Conditional Move Instructions. The conditional move instruction\r
/// CMOV is supported. In addition, if x87 FPU is present as indicated by the\r
/// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.\r
///\r
- UINT32 CMOV:1;\r
+ UINT32 CMOV : 1;\r
///\r
/// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This\r
/// feature augments the Memory Type Range Registers (MTRRs), allowing an\r
/// operating system to specify attributes of memory accessed through a\r
/// linear address on a 4KB granularity.\r
///\r
- UINT32 PAT:1;\r
+ UINT32 PAT : 1;\r
///\r
/// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical\r
/// memory beyond 4 GBytes are supported with 32-bit paging. This feature\r
/// encoded in bits 20:13 of the page-directory entry. Such physical\r
/// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.\r
///\r
- UINT32 PSE_36:1;\r
+ UINT32 PSE_36 : 1;\r
///\r
/// [Bit 18] Processor Serial Number. The processor supports the 96-bit\r
/// processor identification number feature and the feature is enabled.\r
///\r
- UINT32 PSN:1;\r
+ UINT32 PSN : 1;\r
///\r
/// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.\r
///\r
- UINT32 CLFSH:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 CLFSH : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 21] Debug Store. The processor supports the ability to write debug\r
/// information into a memory resident buffer. This feature is used by the\r
/// branch trace store (BTS) and precise event-based sampling (PEBS)\r
/// facilities.\r
///\r
- UINT32 DS:1;\r
+ UINT32 DS : 1;\r
///\r
/// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The\r
/// processor implements internal MSRs that allow processor temperature to\r
/// be monitored and processor performance to be modulated in predefined\r
/// duty cycles under software control.\r
///\r
- UINT32 ACPI:1;\r
+ UINT32 ACPI : 1;\r
///\r
/// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX\r
/// technology.\r
///\r
- UINT32 MMX:1;\r
+ UINT32 MMX : 1;\r
///\r
/// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR\r
/// instructions are supported for fast save and restore of the floating\r
/// available for an operating system to indicate that it supports the\r
/// FXSAVE and FXRSTOR instructions.\r
///\r
- UINT32 FXSR:1;\r
+ UINT32 FXSR : 1;\r
///\r
/// [Bit 25] SSE. The processor supports the SSE extensions.\r
///\r
- UINT32 SSE:1;\r
+ UINT32 SSE : 1;\r
///\r
/// [Bit 26] SSE2. The processor supports the SSE2 extensions.\r
///\r
- UINT32 SSE2:1;\r
+ UINT32 SSE2 : 1;\r
///\r
/// [Bit 27] Self Snoop. The processor supports the management of\r
/// conflicting memory types by performing a snoop of its own cache\r
/// structure for transactions issued to the bus.\r
///\r
- UINT32 SS:1;\r
+ UINT32 SS : 1;\r
///\r
/// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT\r
/// indicates there is only a single logical processor in the package and\r
/// addressable IDs for logical processors in this package) is valid for the\r
/// package.\r
///\r
- UINT32 HTT:1;\r
+ UINT32 HTT : 1;\r
///\r
/// [Bit 29] Thermal Monitor. The processor implements the thermal monitor\r
/// automatic thermal control circuitry (TCC).\r
///\r
- UINT32 TM:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 TM : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 31] Pending Break Enable. The processor supports the use of the\r
/// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is\r
/// the processor should return to normal operation to handle the interrupt.\r
/// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.\r
///\r
- UINT32 PBE:1;\r
+ UINT32 PBE : 1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
UINT32 Uint32;\r
} CPUID_VERSION_INFO_EDX;\r
\r
-\r
/**\r
CPUID Cache and TLB Information\r
\r
use CPUID leaf 4 to query cache parameters</td></tr>\r
</table>\r
**/\r
-#define CPUID_CACHE_INFO 0x02\r
+#define CPUID_CACHE_INFO 0x02\r
\r
/**\r
CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved:31;\r
+ UINT32 Reserved : 31;\r
///\r
/// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.\r
/// if 1, then none of the cache descriptor bytes in the register are valid.\r
///\r
- UINT32 NotValid:1;\r
+ UINT32 NotValid : 1;\r
} Bits;\r
///\r
/// Array of Cache and TLB descriptor bytes\r
///\r
- UINT8 CacheDescriptor[4];\r
+ UINT8 CacheDescriptor[4];\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_CACHE_INFO_CACHE_TLB;\r
\r
-\r
/**\r
CPUID Processor Serial Number\r
\r
AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);\r
@endcode\r
**/\r
-#define CPUID_SERIAL_NUMBER 0x03\r
-\r
+#define CPUID_SERIAL_NUMBER 0x03\r
\r
/**\r
CPUID Cache Parameters\r
} while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);\r
@endcode\r
**/\r
-#define CPUID_CACHE_PARAMS 0x04\r
+#define CPUID_CACHE_PARAMS 0x04\r
\r
/**\r
CPUID Cache Parameters Information returned in EAX for CPUID leaf\r
/// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,\r
/// then there is no information for the requested cache level.\r
///\r
- UINT32 CacheType:5;\r
+ UINT32 CacheType : 5;\r
///\r
/// [Bits 7:5] Cache level (Starts at 1).\r
///\r
- UINT32 CacheLevel:3;\r
+ UINT32 CacheLevel : 3;\r
///\r
/// [Bit 8] Self Initializing cache level (does not need SW initialization).\r
///\r
- UINT32 SelfInitializingCache:1;\r
+ UINT32 SelfInitializingCache : 1;\r
///\r
/// [Bit 9] Fully Associative cache.\r
///\r
- UINT32 FullyAssociativeCache:1;\r
+ UINT32 FullyAssociativeCache : 1;\r
///\r
/// [Bits 13:10] Reserved.\r
///\r
- UINT32 Reserved:4;\r
+ UINT32 Reserved : 4;\r
///\r
/// [Bits 25:14] Maximum number of addressable IDs for logical processors\r
/// sharing this cache.\r
/// is the number of unique initial APIC IDs reserved for addressing\r
/// different logical processors sharing this cache.\r
///\r
- UINT32 MaximumAddressableIdsForLogicalProcessors:12;\r
+ UINT32 MaximumAddressableIdsForLogicalProcessors : 12;\r
///\r
/// [Bits 31:26] Maximum number of addressable IDs for processor cores in\r
/// the physical package.\r
/// The returned value is constant for valid initial values in ECX. Valid\r
/// ECX values start from 0.\r
///\r
- UINT32 MaximumAddressableIdsForProcessorCores:6;\r
+ UINT32 MaximumAddressableIdsForProcessorCores : 6;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_CACHE_PARAMS_EAX;\r
\r
///\r
/// [Bits 11:0] System Coherency Line Size. Add one to the return value to\r
/// get the result.\r
///\r
- UINT32 LineSize:12;\r
+ UINT32 LineSize : 12;\r
///\r
/// [Bits 21:12] Physical Line Partitions. Add one to the return value to\r
/// get the result.\r
///\r
- UINT32 LinePartitions:10;\r
+ UINT32 LinePartitions : 10;\r
///\r
/// [Bits 31:22] Ways of associativity. Add one to the return value to get\r
/// the result.\r
///\r
- UINT32 Ways:10;\r
+ UINT32 Ways : 10;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_CACHE_PARAMS_EBX;\r
\r
/**\r
/// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of\r
/// non-originating threads sharing this cache.\r
///\r
- UINT32 Invalidate:1;\r
+ UINT32 Invalidate : 1;\r
///\r
/// [Bit 1] Cache Inclusiveness.\r
/// 0 = Cache is not inclusive of lower cache levels.\r
/// 1 = Cache is inclusive of lower cache levels.\r
///\r
- UINT32 CacheInclusiveness:1;\r
+ UINT32 CacheInclusiveness : 1;\r
///\r
/// [Bit 2] Complex Cache Indexing.\r
/// 0 = Direct mapped cache.\r
/// 1 = A complex function is used to index the cache, potentially using all\r
/// address bits.\r
///\r
- UINT32 ComplexCacheIndexing:1;\r
- UINT32 Reserved:29;\r
+ UINT32 ComplexCacheIndexing : 1;\r
+ UINT32 Reserved : 29;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_CACHE_PARAMS_EDX;\r
\r
-\r
/**\r
CPUID MONITOR/MWAIT Information\r
\r
AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
@endcode\r
**/\r
-#define CPUID_MONITOR_MWAIT 0x05\r
+#define CPUID_MONITOR_MWAIT 0x05\r
\r
/**\r
CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf\r
/// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's\r
/// monitor granularity).\r
///\r
- UINT32 SmallestMonitorLineSize:16;\r
- UINT32 Reserved:16;\r
+ UINT32 SmallestMonitorLineSize : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_MONITOR_MWAIT_EAX;\r
\r
/**\r
/// [Bits 15:0] Largest monitor-line size in bytes (default is processor's\r
/// monitor granularity).\r
///\r
- UINT32 LargestMonitorLineSize:16;\r
- UINT32 Reserved:16;\r
+ UINT32 LargestMonitorLineSize : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_MONITOR_MWAIT_EBX;\r
\r
/**\r
/// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,\r
/// and EDX are valid.\r
///\r
- UINT32 ExtensionsSupported:1;\r
+ UINT32 ExtensionsSupported : 1;\r
///\r
/// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when\r
/// interrupts disabled.\r
///\r
- UINT32 InterruptAsBreak:1;\r
- UINT32 Reserved:30;\r
+ UINT32 InterruptAsBreak : 1;\r
+ UINT32 Reserved : 30;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_MONITOR_MWAIT_ECX;\r
\r
/**\r
///\r
/// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.\r
///\r
- UINT32 C0States:4;\r
+ UINT32 C0States : 4;\r
///\r
/// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.\r
///\r
- UINT32 C1States:4;\r
+ UINT32 C1States : 4;\r
///\r
/// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.\r
///\r
- UINT32 C2States:4;\r
+ UINT32 C2States : 4;\r
///\r
/// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.\r
///\r
- UINT32 C3States:4;\r
+ UINT32 C3States : 4;\r
///\r
/// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.\r
///\r
- UINT32 C4States:4;\r
+ UINT32 C4States : 4;\r
///\r
/// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.\r
///\r
- UINT32 C5States:4;\r
+ UINT32 C5States : 4;\r
///\r
/// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.\r
///\r
- UINT32 C6States:4;\r
+ UINT32 C6States : 4;\r
///\r
/// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.\r
///\r
- UINT32 C7States:4;\r
+ UINT32 C7States : 4;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_MONITOR_MWAIT_EDX;\r
\r
-\r
/**\r
CPUID Thermal and Power Management\r
\r
AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
@endcode\r
**/\r
-#define CPUID_THERMAL_POWER_MANAGEMENT 0x06\r
+#define CPUID_THERMAL_POWER_MANAGEMENT 0x06\r
\r
/**\r
CPUID Thermal and Power Management Information returned in EAX for CPUID leaf\r
///\r
/// [Bit 0] Digital temperature sensor is supported if set.\r
///\r
- UINT32 DigitalTemperatureSensor:1;\r
+ UINT32 DigitalTemperatureSensor : 1;\r
///\r
/// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).\r
///\r
- UINT32 TurboBoostTechnology:1;\r
+ UINT32 TurboBoostTechnology : 1;\r
///\r
/// [Bit 2] APIC-Timer-always-running feature is supported if set.\r
///\r
- UINT32 ARAT:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 ARAT : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 4] Power limit notification controls are supported if set.\r
///\r
- UINT32 PLN:1;\r
+ UINT32 PLN : 1;\r
///\r
/// [Bit 5] Clock modulation duty cycle extension is supported if set.\r
///\r
- UINT32 ECMD:1;\r
+ UINT32 ECMD : 1;\r
///\r
/// [Bit 6] Package thermal management is supported if set.\r
///\r
- UINT32 PTM:1;\r
+ UINT32 PTM : 1;\r
///\r
/// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,\r
/// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.\r
///\r
- UINT32 HWP:1;\r
+ UINT32 HWP : 1;\r
///\r
/// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.\r
///\r
- UINT32 HWP_Notification:1;\r
+ UINT32 HWP_Notification : 1;\r
///\r
/// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.\r
///\r
- UINT32 HWP_Activity_Window:1;\r
+ UINT32 HWP_Activity_Window : 1;\r
///\r
/// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.\r
///\r
- UINT32 HWP_Energy_Performance_Preference:1;\r
+ UINT32 HWP_Energy_Performance_Preference : 1;\r
///\r
/// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.\r
///\r
- UINT32 HWP_Package_Level_Request:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 HWP_Package_Level_Request : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,\r
/// IA32_THREAD_STALL MSRs are supported if set.\r
///\r
- UINT32 HDC:1;\r
+ UINT32 HDC : 1;\r
///\r
/// [Bit 14] Intel Turbo Boost Max Technology 3.0 available.\r
///\r
- UINT32 TurboBoostMaxTechnology30:1;\r
+ UINT32 TurboBoostMaxTechnology30 : 1;\r
///\r
/// [Bit 15] HWP Capabilities.\r
/// Highest Performance change is supported if set.\r
///\r
- UINT32 HWPCapabilities:1;\r
+ UINT32 HWPCapabilities : 1;\r
///\r
/// [Bit 16] HWP PECI override is supported if set.\r
///\r
- UINT32 HWPPECIOverride:1;\r
+ UINT32 HWPPECIOverride : 1;\r
///\r
/// [Bit 17] Flexible HWP is supported if set.\r
///\r
- UINT32 FlexibleHWP:1;\r
+ UINT32 FlexibleHWP : 1;\r
///\r
/// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.\r
///\r
- UINT32 FastAccessMode:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 FastAccessMode : 1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set.\r
///\r
- UINT32 IgnoringIdleLogicalProcessorHWPRequest:1;\r
- UINT32 Reserved5:11;\r
+ UINT32 IgnoringIdleLogicalProcessorHWPRequest : 1;\r
+ UINT32 Reserved5 : 11;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_THERMAL_POWER_MANAGEMENT_EAX;\r
\r
/**\r
///\r
/// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.\r
///\r
- UINT32 InterruptThresholds:4;\r
- UINT32 Reserved:28;\r
+ UINT32 InterruptThresholds : 4;\r
+ UINT32 Reserved : 28;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_THERMAL_POWER_MANAGEMENT_EBX;\r
\r
/**\r
/// processor performance (since last reset of the counters), as a percentage\r
/// of the expected processor performance when running at the TSC frequency.\r
///\r
- UINT32 HardwareCoordinationFeedback:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 HardwareCoordinationFeedback : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 3] If this bit is set, then the processor supports performance-energy\r
/// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS\r
/// (1B0H).\r
///\r
- UINT32 PerformanceEnergyBias:1;\r
- UINT32 Reserved2:28;\r
+ UINT32 PerformanceEnergyBias : 1;\r
+ UINT32 Reserved2 : 28;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_THERMAL_POWER_MANAGEMENT_ECX;\r
\r
-\r
/**\r
CPUID Structured Extended Feature Flags Enumeration\r
\r
}\r
@endcode\r
**/\r
-#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07\r
+#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07\r
\r
///\r
/// CPUID Structured Extended Feature Flags Enumeration sub-leaf\r
///\r
/// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.\r
///\r
- UINT32 FSGSBASE:1;\r
+ UINT32 FSGSBASE : 1;\r
///\r
/// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.\r
///\r
- UINT32 IA32_TSC_ADJUST:1;\r
+ UINT32 IA32_TSC_ADJUST : 1;\r
///\r
/// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT\r
/// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".\r
///\r
- UINT32 SGX:1;\r
+ UINT32 SGX : 1;\r
///\r
/// [Bit 3] If 1 indicates the processor supports the first group of advanced\r
/// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)\r
///\r
- UINT32 BMI1:1;\r
+ UINT32 BMI1 : 1;\r
///\r
/// [Bit 4] Hardware Lock Elision\r
///\r
- UINT32 HLE:1;\r
+ UINT32 HLE : 1;\r
///\r
/// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.\r
///\r
- UINT32 AVX2:1;\r
+ UINT32 AVX2 : 1;\r
///\r
/// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.\r
///\r
- UINT32 FDP_EXCPTN_ONLY:1;\r
+ UINT32 FDP_EXCPTN_ONLY : 1;\r
///\r
/// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.\r
///\r
- UINT32 SMEP:1;\r
+ UINT32 SMEP : 1;\r
///\r
/// [Bit 8] If 1 indicates the processor supports the second group of\r
/// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,\r
/// SARX, SHLX, SHRX)\r
///\r
- UINT32 BMI2:1;\r
+ UINT32 BMI2 : 1;\r
///\r
/// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.\r
///\r
- UINT32 EnhancedRepMovsbStosb:1;\r
+ UINT32 EnhancedRepMovsbStosb : 1;\r
///\r
/// [Bit 10] If 1, supports INVPCID instruction for system software that\r
/// manages process-context identifiers.\r
///\r
- UINT32 INVPCID:1;\r
+ UINT32 INVPCID : 1;\r
///\r
/// [Bit 11] Restricted Transactional Memory\r
///\r
- UINT32 RTM:1;\r
+ UINT32 RTM : 1;\r
///\r
/// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)\r
/// Monitoring capability if 1.\r
///\r
- UINT32 RDT_M:1;\r
+ UINT32 RDT_M : 1;\r
///\r
/// [Bit 13] Deprecates FPU CS and FPU DS values if 1.\r
///\r
- UINT32 DeprecateFpuCsDs:1;\r
+ UINT32 DeprecateFpuCsDs : 1;\r
///\r
/// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.\r
///\r
- UINT32 MPX:1;\r
+ UINT32 MPX : 1;\r
///\r
/// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)\r
/// Allocation capability if 1.\r
///\r
- UINT32 RDT_A:1;\r
+ UINT32 RDT_A : 1;\r
///\r
/// [Bit 16] AVX512F.\r
///\r
- UINT32 AVX512F:1;\r
+ UINT32 AVX512F : 1;\r
///\r
/// [Bit 17] AVX512DQ.\r
///\r
- UINT32 AVX512DQ:1;\r
+ UINT32 AVX512DQ : 1;\r
///\r
/// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.\r
///\r
- UINT32 RDSEED:1;\r
+ UINT32 RDSEED : 1;\r
///\r
/// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX\r
/// instructions.\r
///\r
- UINT32 ADX:1;\r
+ UINT32 ADX : 1;\r
///\r
/// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC\r
/// instructions) if 1.\r
///\r
- UINT32 SMAP:1;\r
+ UINT32 SMAP : 1;\r
///\r
/// [Bit 21] AVX512_IFMA.\r
///\r
- UINT32 AVX512_IFMA:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 AVX512_IFMA : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.\r
///\r
- UINT32 CLFLUSHOPT:1;\r
+ UINT32 CLFLUSHOPT : 1;\r
///\r
/// [Bit 24] If 1 indicates the processor supports the CLWB instruction.\r
///\r
- UINT32 CLWB:1;\r
+ UINT32 CLWB : 1;\r
///\r
/// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace\r
/// extensions.\r
///\r
- UINT32 IntelProcessorTrace:1;\r
+ UINT32 IntelProcessorTrace : 1;\r
///\r
/// [Bit 26] AVX512PF. (Intel Xeon Phi only.).\r
///\r
- UINT32 AVX512PF:1;\r
+ UINT32 AVX512PF : 1;\r
///\r
/// [Bit 27] AVX512ER. (Intel Xeon Phi only.).\r
///\r
- UINT32 AVX512ER:1;\r
+ UINT32 AVX512ER : 1;\r
///\r
/// [Bit 28] AVX512CD.\r
///\r
- UINT32 AVX512CD:1;\r
+ UINT32 AVX512CD : 1;\r
///\r
/// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)\r
/// SHA Extensions) if 1.\r
///\r
- UINT32 SHA:1;\r
+ UINT32 SHA : 1;\r
///\r
/// [Bit 30] AVX512BW.\r
///\r
- UINT32 AVX512BW:1;\r
+ UINT32 AVX512BW : 1;\r
///\r
/// [Bit 31] AVX512VL.\r
///\r
- UINT32 AVX512VL:1;\r
+ UINT32 AVX512VL : 1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX;\r
\r
/**\r
/// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.\r
/// (Intel Xeon Phi only.)\r
///\r
- UINT32 PREFETCHWT1:1;\r
+ UINT32 PREFETCHWT1 : 1;\r
///\r
/// [Bit 1] AVX512_VBMI.\r
///\r
- UINT32 AVX512_VBMI:1;\r
+ UINT32 AVX512_VBMI : 1;\r
///\r
/// [Bit 2] Supports user-mode instruction prevention if 1.\r
///\r
- UINT32 UMIP:1;\r
+ UINT32 UMIP : 1;\r
///\r
/// [Bit 3] Supports protection keys for user-mode pages if 1.\r
///\r
- UINT32 PKU:1;\r
+ UINT32 PKU : 1;\r
///\r
/// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the\r
/// RDPKRU/WRPKRU instructions).\r
///\r
- UINT32 OSPKE:1;\r
- UINT32 Reserved5:9;\r
+ UINT32 OSPKE : 1;\r
+ UINT32 Reserved5 : 9;\r
///\r
/// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).\r
///\r
- UINT32 AVX512_VPOPCNTDQ:1;\r
- UINT32 Reserved7:1;\r
+ UINT32 AVX512_VPOPCNTDQ : 1;\r
+ UINT32 Reserved7 : 1;\r
///\r
/// [Bits 16] Supports 5-level paging if 1.\r
///\r
- UINT32 FiveLevelPage:1;\r
+ UINT32 FiveLevelPage : 1;\r
///\r
/// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions\r
/// in 64-bit mode.\r
///\r
- UINT32 MAWAU:5;\r
+ UINT32 MAWAU : 5;\r
///\r
/// [Bit 22] RDPID and IA32_TSC_AUX are available if 1.\r
///\r
- UINT32 RDPID:1;\r
- UINT32 Reserved3:7;\r
+ UINT32 RDPID : 1;\r
+ UINT32 Reserved3 : 7;\r
///\r
/// [Bit 30] Supports SGX Launch Configuration if 1.\r
///\r
- UINT32 SGX_LC:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 SGX_LC : 1;\r
+ UINT32 Reserved4 : 1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;\r
\r
/**\r
///\r
/// [Bit 1:0] Reserved.\r
///\r
- UINT32 Reserved1:2;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.)\r
///\r
- UINT32 AVX512_4VNNIW:1;\r
+ UINT32 AVX512_4VNNIW : 1;\r
///\r
/// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.)\r
///\r
- UINT32 AVX512_4FMAPS:1;\r
+ UINT32 AVX512_4FMAPS : 1;\r
///\r
/// [Bit 14:4] Reserved.\r
///\r
- UINT32 Reserved4:11;\r
+ UINT32 Reserved4 : 11;\r
///\r
/// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid part.\r
///\r
- UINT32 Hybrid:1;\r
+ UINT32 Hybrid : 1;\r
///\r
/// [Bit 25:16] Reserved.\r
///\r
- UINT32 Reserved5:10;\r
+ UINT32 Reserved5 : 10;\r
///\r
/// [Bit 26] Enumerates support for indirect branch restricted speculation\r
/// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors\r
/// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and\r
/// IA32_PRED_CMD[0] (IBPB).\r
///\r
- UINT32 EnumeratesSupportForIBRSAndIBPB:1;\r
+ UINT32 EnumeratesSupportForIBRSAndIBPB : 1;\r
///\r
/// [Bit 27] Enumerates support for single thread indirect branch\r
/// predictors (STIBP). Processors that set this bit support the\r
/// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1]\r
/// (STIBP).\r
///\r
- UINT32 EnumeratesSupportForSTIBP:1;\r
+ UINT32 EnumeratesSupportForSTIBP : 1;\r
///\r
/// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit\r
/// support the IA32_FLUSH_CMD MSR. They allow software to set\r
/// IA32_FLUSH_CMD[0] (L1D_FLUSH).\r
///\r
- UINT32 EnumeratesSupportForL1D_FLUSH:1;\r
+ UINT32 EnumeratesSupportForL1D_FLUSH : 1;\r
///\r
/// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR.\r
///\r
- UINT32 EnumeratesSupportForCapability:1;\r
+ UINT32 EnumeratesSupportForCapability : 1;\r
///\r
/// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR.\r
///\r
- UINT32 EnumeratesSupportForCoreCapabilitiesMsr:1;\r
+ UINT32 EnumeratesSupportForCoreCapabilitiesMsr : 1;\r
///\r
/// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).\r
/// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow\r
/// software to set IA32_SPEC_CTRL[2] (SSBD).\r
///\r
- UINT32 EnumeratesSupportForSSBD:1;\r
+ UINT32 EnumeratesSupportForSSBD : 1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX;\r
\r
/**\r
AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);\r
@endcode\r
**/\r
-#define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09\r
-\r
+#define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09\r
\r
/**\r
CPUID Architectural Performance Monitoring\r
///\r
/// [Bit 7:0] Version ID of architectural performance monitoring.\r
///\r
- UINT32 ArchPerfMonVerID:8;\r
+ UINT32 ArchPerfMonVerID : 8;\r
///\r
/// [Bits 15:8] Number of general-purpose performance monitoring counter\r
/// per logical processor.\r
/// paired with a corresponding performance counter in the 0C1H address\r
/// block.\r
///\r
- UINT32 PerformanceMonitorCounters:8;\r
+ UINT32 PerformanceMonitorCounters : 8;\r
///\r
/// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.\r
///\r
/// may be written with any value, and the high-order bits are sign-extended\r
/// from the value of bit 31.\r
///\r
- UINT32 PerformanceMonitorCounterWidth:8;\r
+ UINT32 PerformanceMonitorCounterWidth : 8;\r
///\r
/// [Bits 31:24] Length of EBX bit vector to enumerate architectural\r
/// performance monitoring events.\r
///\r
- UINT32 EbxBitVectorLength:8;\r
+ UINT32 EbxBitVectorLength : 8;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;\r
\r
/**\r
///\r
/// [Bit 0] Core cycle event not available if 1.\r
///\r
- UINT32 UnhaltedCoreCycles:1;\r
+ UINT32 UnhaltedCoreCycles : 1;\r
///\r
/// [Bit 1] Instruction retired event not available if 1.\r
///\r
- UINT32 InstructionsRetired:1;\r
+ UINT32 InstructionsRetired : 1;\r
///\r
/// [Bit 2] Reference cycles event not available if 1.\r
///\r
- UINT32 UnhaltedReferenceCycles:1;\r
+ UINT32 UnhaltedReferenceCycles : 1;\r
///\r
/// [Bit 3] Last-level cache reference event not available if 1.\r
///\r
- UINT32 LastLevelCacheReferences:1;\r
+ UINT32 LastLevelCacheReferences : 1;\r
///\r
/// [Bit 4] Last-level cache misses event not available if 1.\r
///\r
- UINT32 LastLevelCacheMisses:1;\r
+ UINT32 LastLevelCacheMisses : 1;\r
///\r
/// [Bit 5] Branch instruction retired event not available if 1.\r
///\r
- UINT32 BranchInstructionsRetired:1;\r
+ UINT32 BranchInstructionsRetired : 1;\r
///\r
/// [Bit 6] Branch mispredict retired event not available if 1.\r
///\r
- UINT32 AllBranchMispredictRetired:1;\r
- UINT32 Reserved:25;\r
+ UINT32 AllBranchMispredictRetired : 1;\r
+ UINT32 Reserved : 25;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;\r
\r
/**\r
/// [Bits 4:0] Number of fixed-function performance counters\r
/// (if Version ID > 1).\r
///\r
- UINT32 FixedFunctionPerformanceCounters:5;\r
+ UINT32 FixedFunctionPerformanceCounters : 5;\r
///\r
/// [Bits 12:5] Bit width of fixed-function performance counters\r
/// (if Version ID > 1).\r
///\r
- UINT32 FixedFunctionPerformanceCounterWidth:8;\r
- UINT32 Reserved1:2;\r
+ UINT32 FixedFunctionPerformanceCounterWidth : 8;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bits 15] AnyThread deprecation.\r
///\r
- UINT32 AnyThreadDeprecation:1;\r
- UINT32 Reserved2:16;\r
+ UINT32 AnyThreadDeprecation : 1;\r
+ UINT32 Reserved2 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;\r
\r
-\r
/**\r
CPUID Extended Topology Information\r
\r
} while (Eax.Bits.ApicIdShift != 0);\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_TOPOLOGY 0x0B\r
+#define CPUID_EXTENDED_TOPOLOGY 0x0B\r
\r
/**\r
CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r
/// Software should use this field (EAX[4:0]) to enumerate processor\r
/// topology of the system.\r
///\r
- UINT32 ApicIdShift:5;\r
- UINT32 Reserved:27;\r
+ UINT32 ApicIdShift : 5;\r
+ UINT32 Reserved : 27;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_TOPOLOGY_EAX;\r
\r
/**\r
/// available to BIOS/OS/Applications may be different from the value of\r
/// EBX[15:0], depending on software and platform hardware configurations.\r
///\r
- UINT32 LogicalProcessors:16;\r
- UINT32 Reserved:16;\r
+ UINT32 LogicalProcessors : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_TOPOLOGY_EBX;\r
\r
/**\r
///\r
/// [Bits 7:0] Level number. Same value in ECX input.\r
///\r
- UINT32 LevelNumber:8;\r
+ UINT32 LevelNumber : 8;\r
///\r
/// [Bits 15:8] Level type.\r
///\r
/// The value of the "level type" field is not related to level numbers in\r
/// any way, higher "level type" values do not mean higher levels.\r
///\r
- UINT32 LevelType:8;\r
- UINT32 Reserved:16;\r
+ UINT32 LevelType : 8;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_TOPOLOGY_ECX;\r
\r
///\r
/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType\r
///\r
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00\r
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01\r
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02\r
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00\r
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01\r
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02\r
///\r
/// @}\r
///\r
\r
-\r
/**\r
CPUID Extended State Information\r
\r
CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).\r
Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.\r
**/\r
-#define CPUID_EXTENDED_STATE 0x0D\r
+#define CPUID_EXTENDED_STATE 0x0D\r
\r
/**\r
CPUID Extended State Information Main Leaf\r
);\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00\r
+#define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00\r
\r
/**\r
CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r
///\r
/// [Bit 0] x87 state.\r
///\r
- UINT32 x87:1;\r
+ UINT32 x87 : 1;\r
///\r
/// [Bit 1] SSE state.\r
///\r
- UINT32 SSE:1;\r
+ UINT32 SSE : 1;\r
///\r
/// [Bit 2] AVX state.\r
///\r
- UINT32 AVX:1;\r
+ UINT32 AVX : 1;\r
///\r
/// [Bits 4:3] MPX state.\r
///\r
- UINT32 MPX:2;\r
+ UINT32 MPX : 2;\r
///\r
/// [Bits 7:5] AVX-512 state.\r
///\r
- UINT32 AVX_512:3;\r
+ UINT32 AVX_512 : 3;\r
///\r
/// [Bit 8] Used for IA32_XSS.\r
///\r
- UINT32 IA32_XSS:1;\r
+ UINT32 IA32_XSS : 1;\r
///\r
/// [Bit 9] PKRU state.\r
///\r
- UINT32 PKRU:1;\r
- UINT32 Reserved1:3;\r
+ UINT32 PKRU : 1;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 13] Used for IA32_XSS, part 2.\r
///\r
- UINT32 IA32_XSS_2:1;\r
- UINT32 Reserved2:18;\r
+ UINT32 IA32_XSS_2 : 1;\r
+ UINT32 Reserved2 : 18;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;\r
\r
/**\r
);\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_STATE_SUB_LEAF 0x01\r
+#define CPUID_EXTENDED_STATE_SUB_LEAF 0x01\r
\r
/**\r
CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r
///\r
/// [Bit 0] XSAVEOPT is available.\r
///\r
- UINT32 XSAVEOPT:1;\r
+ UINT32 XSAVEOPT : 1;\r
///\r
/// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.\r
///\r
- UINT32 XSAVEC:1;\r
+ UINT32 XSAVEC : 1;\r
///\r
/// [Bit 2] Supports XGETBV with ECX = 1 if set.\r
///\r
- UINT32 XGETBV:1;\r
+ UINT32 XGETBV : 1;\r
///\r
/// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.\r
///\r
- UINT32 XSAVES:1;\r
- UINT32 Reserved:28;\r
+ UINT32 XSAVES : 1;\r
+ UINT32 Reserved : 28;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_STATE_SUB_LEAF_EAX;\r
\r
/**\r
///\r
/// [Bits 7:0] Used for XCR0.\r
///\r
- UINT32 XCR0:1;\r
+ UINT32 XCR0 : 1;\r
///\r
/// [Bit 8] PT STate.\r
///\r
- UINT32 PT:1;\r
+ UINT32 PT : 1;\r
///\r
/// [Bit 9] Used for XCR0.\r
///\r
- UINT32 XCR0_1:1;\r
- UINT32 Reserved1:3;\r
+ UINT32 XCR0_1 : 1;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 13] HWP state.\r
///\r
- UINT32 HWPState:1;\r
- UINT32 Reserved8:18;\r
+ UINT32 HWPState : 1;\r
+ UINT32 Reserved8 : 18;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_STATE_SUB_LEAF_ECX;\r
\r
/**\r
}\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02\r
+#define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02\r
\r
/**\r
CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,\r
/// supported in the IA32_XSS MSR; it is clear if bit n is instead supported\r
/// in XCR0.\r
///\r
- UINT32 XSS:1;\r
+ UINT32 XSS : 1;\r
///\r
/// [Bit 1] is set if, when the compacted format of an XSAVE area is used,\r
/// this extended state component located on the next 64-byte boundary\r
/// following the preceding state component (otherwise, it is located\r
/// immediately following the preceding state component).\r
///\r
- UINT32 Compacted:1;\r
- UINT32 Reserved:30;\r
+ UINT32 Compacted : 1;\r
+ UINT32 Reserved : 30;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;\r
\r
-\r
/**\r
CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r
\r
CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).\r
\r
**/\r
-#define CPUID_INTEL_RDT_MONITORING 0x0F\r
+#define CPUID_INTEL_RDT_MONITORING 0x0F\r
\r
/**\r
CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00\r
+#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00\r
\r
/**\r
CPUID Intel RDT Monitoring Information EDX for CPUID leaf\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.\r
///\r
- UINT32 L3CacheRDT_M:1;\r
- UINT32 Reserved2:30;\r
+ UINT32 L3CacheRDT_M : 1;\r
+ UINT32 Reserved2 : 30;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX;\r
\r
/**\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01\r
+#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01\r
\r
/**\r
CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf\r
///\r
/// [Bit 0] Supports L3 occupancy monitoring if 1.\r
///\r
- UINT32 L3CacheOccupancyMonitoring:1;\r
+ UINT32 L3CacheOccupancyMonitoring : 1;\r
///\r
/// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.\r
///\r
- UINT32 L3CacheTotalBandwidthMonitoring:1;\r
+ UINT32 L3CacheTotalBandwidthMonitoring : 1;\r
///\r
/// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.\r
///\r
- UINT32 L3CacheLocalBandwidthMonitoring:1;\r
- UINT32 Reserved:29;\r
+ UINT32 L3CacheLocalBandwidthMonitoring : 1;\r
+ UINT32 Reserved : 29;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX;\r
\r
-\r
/**\r
CPUID Intel Resource Director Technology (Intel RDT) Allocation Information\r
\r
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).\r
CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).\r
**/\r
-#define CPUID_INTEL_RDT_ALLOCATION 0x10\r
+#define CPUID_INTEL_RDT_ALLOCATION 0x10\r
\r
/**\r
Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00\r
+#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00\r
\r
/**\r
CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Supports L3 Cache Allocation Technology if 1.\r
///\r
- UINT32 L3CacheAllocation:1;\r
+ UINT32 L3CacheAllocation : 1;\r
///\r
/// [Bit 2] Supports L2 Cache Allocation Technology if 1.\r
///\r
- UINT32 L2CacheAllocation:1;\r
+ UINT32 L2CacheAllocation : 1;\r
///\r
/// [Bit 3] Supports Memory Bandwidth Allocation if 1.\r
///\r
- UINT32 MemoryBandwidth:1;\r
- UINT32 Reserved3:28;\r
+ UINT32 MemoryBandwidth : 1;\r
+ UINT32 Reserved3 : 28;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX;\r
\r
-\r
/**\r
L3 Cache Allocation Technology Enumeration Sub-leaf\r
\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01\r
+#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01\r
\r
/**\r
CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf\r
/// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r
/// using minus-one notation.\r
///\r
- UINT32 CapacityLength:5;\r
- UINT32 Reserved:27;\r
+ UINT32 CapacityLength : 5;\r
+ UINT32 Reserved : 27;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX;\r
\r
/**\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved3:2;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 2] Code and Data Prioritization Technology supported if 1.\r
///\r
- UINT32 CodeDataPrioritization:1;\r
- UINT32 Reserved2:29;\r
+ UINT32 CodeDataPrioritization : 1;\r
+ UINT32 Reserved2 : 29;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX;\r
\r
/**\r
///\r
/// [Bits 15:0] Highest COS number supported for this ResID.\r
///\r
- UINT32 HighestCosNumber:16;\r
- UINT32 Reserved:16;\r
+ UINT32 HighestCosNumber : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX;\r
\r
/**\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02\r
+#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02\r
\r
/**\r
CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf\r
/// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r
/// using minus-one notation.\r
///\r
- UINT32 CapacityLength:5;\r
- UINT32 Reserved:27;\r
+ UINT32 CapacityLength : 5;\r
+ UINT32 Reserved : 27;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX;\r
\r
/**\r
///\r
/// [Bits 15:0] Highest COS number supported for this ResID.\r
///\r
- UINT32 HighestCosNumber:16;\r
- UINT32 Reserved:16;\r
+ UINT32 HighestCosNumber : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX;\r
\r
/**\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03\r
+#define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03\r
\r
/**\r
CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf\r
/// [Bits 11:0] Reports the maximum MBA throttling value supported for\r
/// the corresponding ResID using minus-one notation.\r
///\r
- UINT32 MaximumMBAThrottling:12;\r
- UINT32 Reserved:20;\r
+ UINT32 MaximumMBAThrottling : 12;\r
+ UINT32 Reserved : 20;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX;\r
\r
/**\r
///\r
/// [Bits 1:0] Reserved.\r
///\r
- UINT32 Reserved1:2;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bits 3] Reports whether the response of the delay values is linear.\r
///\r
- UINT32 Liner:1;\r
- UINT32 Reserved2:29;\r
+ UINT32 Liner : 1;\r
+ UINT32 Reserved2 : 29;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX;\r
\r
/**\r
///\r
/// [Bits 15:0] Highest COS number supported for this ResID.\r
///\r
- UINT32 HighestCosNumber:16;\r
- UINT32 Reserved:16;\r
+ UINT32 HighestCosNumber : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX;\r
\r
/**\r
until the sub-leaf type is invalid.\r
\r
**/\r
-#define CPUID_INTEL_SGX 0x12\r
+#define CPUID_INTEL_SGX 0x12\r
\r
/**\r
Sub-Leaf 0 Enumeration of Intel SGX Capabilities.\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00\r
+#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00\r
\r
/**\r
Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,\r
///\r
/// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.\r
///\r
- UINT32 SGX1:1;\r
+ UINT32 SGX1 : 1;\r
///\r
/// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.\r
///\r
- UINT32 SGX2:1;\r
- UINT32 Reserved1:3;\r
+ UINT32 SGX2 : 1;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves\r
/// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT.\r
///\r
- UINT32 ENCLV:1;\r
+ UINT32 ENCLV : 1;\r
///\r
/// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC,\r
/// ERDINFO, ELDBC, and ELDUC.\r
///\r
- UINT32 ENCLS:1;\r
- UINT32 Reserved2:25;\r
+ UINT32 ENCLS : 1;\r
+ UINT32 Reserved2 : 25;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;\r
\r
/**\r
/// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes\r
/// when not in 64-bit mode.\r
///\r
- UINT32 MaxEnclaveSize_Not64:8;\r
+ UINT32 MaxEnclaveSize_Not64 : 8;\r
///\r
/// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes\r
/// when operating in 64-bit mode.\r
///\r
- UINT32 MaxEnclaveSize_64:8;\r
- UINT32 Reserved:16;\r
+ UINT32 MaxEnclaveSize_64 : 8;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;\r
\r
-\r
/**\r
Sub-Leaf 1 Enumeration of Intel SGX Capabilities.\r
Enumerates Intel SGX capability of processor state configuration and enclave\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01\r
-\r
+#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01\r
\r
/**\r
Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.\r
/// in EBX:EAX and EDX:ECX.\r
/// All other encoding are reserved.\r
///\r
- UINT32 SubLeafType:4;\r
- UINT32 Reserved:8;\r
+ UINT32 SubLeafType : 4;\r
+ UINT32 Reserved : 8;\r
///\r
/// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of\r
/// the base of the EPC section.\r
///\r
- UINT32 LowAddressOfEpcSection:20;\r
+ UINT32 LowAddressOfEpcSection : 20;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;\r
\r
/**\r
/// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of\r
/// the base of the EPC section.\r
///\r
- UINT32 HighAddressOfEpcSection:20;\r
- UINT32 Reserved:12;\r
+ UINT32 HighAddressOfEpcSection : 20;\r
+ UINT32 Reserved : 12;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;\r
\r
/**\r
/// 0001b: The EPC section is confidentiality, integrity and replay protected.\r
/// All other encoding are reserved.\r
///\r
- UINT32 EpcSection:4;\r
- UINT32 Reserved:8;\r
+ UINT32 EpcSection : 4;\r
+ UINT32 Reserved : 8;\r
///\r
/// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the\r
/// corresponding EPC section within the Processor Reserved Memory.\r
///\r
- UINT32 LowSizeOfEpcSection:20;\r
+ UINT32 LowSizeOfEpcSection : 20;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;\r
\r
/**\r
/// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the\r
/// corresponding EPC section within the Processor Reserved Memory.\r
///\r
- UINT32 HighSizeOfEpcSection:20;\r
- UINT32 Reserved:12;\r
+ UINT32 HighSizeOfEpcSection : 20;\r
+ UINT32 Reserved : 12;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;\r
\r
-\r
/**\r
CPUID Intel Processor Trace Information\r
\r
CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).\r
\r
**/\r
-#define CPUID_INTEL_PROCESSOR_TRACE 0x14\r
+#define CPUID_INTEL_PROCESSOR_TRACE 0x14\r
\r
/**\r
CPUID Intel Processor Trace Information Main Leaf\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00\r
+#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00\r
\r
/**\r
CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
/// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,\r
/// and that IA32_RTIT_CR3_MATCH MSR can be accessed.\r
///\r
- UINT32 Cr3Filter:1;\r
+ UINT32 Cr3Filter : 1;\r
///\r
/// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate\r
/// Mode.\r
///\r
- UINT32 ConfigurablePsb:1;\r
+ UINT32 ConfigurablePsb : 1;\r
///\r
/// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,\r
/// and preservation of Intel PT MSRs across warm reset.\r
///\r
- UINT32 IpTraceStopFiltering:1;\r
+ UINT32 IpTraceStopFiltering : 1;\r
///\r
/// [Bit 3] If 1, indicates support of MTC timing packet and suppression of\r
/// COFI-based packets.\r
///\r
- UINT32 Mtc:1;\r
+ UINT32 Mtc : 1;\r
///\r
/// [Bit 4] If 1, indicates support of PTWRITE. Writes can set\r
/// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE\r
/// can generate packets.\r
///\r
- UINT32 PTWrite:1;\r
+ UINT32 PTWrite : 1;\r
///\r
/// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set\r
/// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet\r
/// generation.\r
///\r
- UINT32 PowerEventTrace:1;\r
- UINT32 Reserved:26;\r
+ UINT32 PowerEventTrace : 1;\r
+ UINT32 Reserved : 26;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;\r
\r
/**\r
/// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and\r
/// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.\r
///\r
- UINT32 RTIT:1;\r
+ UINT32 RTIT : 1;\r
///\r
/// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to\r
/// the maximum allowed by the MaskOrTableOffset field of\r
/// IA32_RTIT_OUTPUT_MASK_PTRS.\r
///\r
- UINT32 ToPA:1;\r
+ UINT32 ToPA : 1;\r
///\r
/// [Bit 2] If 1, indicates support of Single-Range Output scheme.\r
///\r
- UINT32 SingleRangeOutput:1;\r
+ UINT32 SingleRangeOutput : 1;\r
///\r
/// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.\r
///\r
- UINT32 TraceTransportSubsystem:1;\r
- UINT32 Reserved:27;\r
+ UINT32 TraceTransportSubsystem : 1;\r
+ UINT32 Reserved : 27;\r
///\r
/// [Bit 31] If 1, generated packets which contain IP payloads have LIP\r
/// values, which include the CS base component.\r
///\r
- UINT32 LIP:1;\r
+ UINT32 LIP : 1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;\r
\r
-\r
/**\r
CPUID Intel Processor Trace Information Sub-leaf\r
\r
}\r
@endcode\r
**/\r
-#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01\r
+#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01\r
\r
/**\r
CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
///\r
/// [Bits 2:0] Number of configurable Address Ranges for filtering.\r
///\r
- UINT32 ConfigurableAddressRanges:3;\r
- UINT32 Reserved:13;\r
+ UINT32 ConfigurableAddressRanges : 3;\r
+ UINT32 Reserved : 13;\r
///\r
/// [Bits 31:16] Bitmap of supported MTC period encodings\r
///\r
- UINT32 MtcPeriodEncodings:16;\r
-\r
+ UINT32 MtcPeriodEncodings : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;\r
\r
/**\r
///\r
/// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.\r
///\r
- UINT32 CycleThresholdEncodings:16;\r
+ UINT32 CycleThresholdEncodings : 16;\r
///\r
/// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.\r
///\r
- UINT32 PsbFrequencyEncodings:16;\r
-\r
+ UINT32 PsbFrequencyEncodings : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;\r
\r
-\r
/**\r
CPUID Time Stamp Counter and Nominal Core Crystal Clock Information\r
\r
AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);\r
@endcode\r
**/\r
-#define CPUID_TIME_STAMP_COUNTER 0x15\r
-\r
+#define CPUID_TIME_STAMP_COUNTER 0x15\r
\r
/**\r
CPUID Processor Frequency Information\r
AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
@endcode\r
**/\r
-#define CPUID_PROCESSOR_FREQUENCY 0x16\r
+#define CPUID_PROCESSOR_FREQUENCY 0x16\r
\r
/**\r
CPUID Processor Frequency Information EAX for CPUID leaf\r
///\r
/// [Bits 15:0] Processor Base Frequency (in MHz).\r
///\r
- UINT32 ProcessorBaseFrequency:16;\r
- UINT32 Reserved:16;\r
+ UINT32 ProcessorBaseFrequency : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_PROCESSOR_FREQUENCY_EAX;\r
\r
/**\r
///\r
/// [Bits 15:0] Maximum Frequency (in MHz).\r
///\r
- UINT32 MaximumFrequency:16;\r
- UINT32 Reserved:16;\r
+ UINT32 MaximumFrequency : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_PROCESSOR_FREQUENCY_EBX;\r
\r
/**\r
///\r
/// [Bits 15:0] Bus (Reference) Frequency (in MHz).\r
///\r
- UINT32 BusFrequency:16;\r
- UINT32 Reserved:16;\r
+ UINT32 BusFrequency : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_PROCESSOR_FREQUENCY_ECX;\r
\r
-\r
/**\r
CPUID SoC Vendor Information\r
\r
EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.\r
\r
**/\r
-#define CPUID_SOC_VENDOR 0x17\r
+#define CPUID_SOC_VENDOR 0x17\r
\r
/**\r
CPUID SoC Vendor Information\r
);\r
@endcode\r
**/\r
-#define CPUID_SOC_VENDOR_MAIN_LEAF 0x00\r
+#define CPUID_SOC_VENDOR_MAIN_LEAF 0x00\r
\r
/**\r
CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf\r
///\r
/// [Bits 15:0] SOC Vendor ID.\r
///\r
- UINT32 SocVendorId:16;\r
+ UINT32 SocVendorId : 16;\r
///\r
/// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry\r
/// standard enumeration scheme. Otherwise, the SOC Vendor ID field is\r
/// assigned by Intel.\r
///\r
- UINT32 IsVendorScheme:1;\r
- UINT32 Reserved:15;\r
+ UINT32 IsVendorScheme : 1;\r
+ UINT32 Reserved : 15;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_SOC_VENDOR_MAIN_LEAF_EBX;\r
\r
/**\r
);\r
@endcode\r
**/\r
-#define CPUID_SOC_VENDOR_BRAND_STRING1 0x01\r
+#define CPUID_SOC_VENDOR_BRAND_STRING1 0x01\r
\r
/**\r
CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,\r
///\r
/// 4 UTF-8 characters of Soc Vendor Brand String\r
///\r
- CHAR8 BrandString[4];\r
+ CHAR8 BrandString[4];\r
///\r
/// All fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_SOC_VENDOR_BRAND_STRING_DATA;\r
\r
/**\r
);\r
@endcode\r
**/\r
-#define CPUID_SOC_VENDOR_BRAND_STRING2 0x02\r
+#define CPUID_SOC_VENDOR_BRAND_STRING2 0x02\r
\r
/**\r
CPUID SoC Vendor Information\r
);\r
@endcode\r
**/\r
-#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03\r
+#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03\r
\r
/**\r
CPUID Deterministic Address Translation Parameters\r
CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF (0x*)\r
\r
**/\r
-#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18\r
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18\r
\r
/**\r
CPUID Deterministic Address Translation Parameters\r
);\r
@endcode\r
**/\r
-#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00\r
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00\r
\r
/**\r
CPUID Deterministic Address Translation Parameters EBX for CPUID leafs.\r
///\r
/// [Bits 0] 4K page size entries supported by this structure.\r
///\r
- UINT32 Page4K:1;\r
+ UINT32 Page4K : 1;\r
///\r
/// [Bits 1] 2MB page size entries supported by this structure.\r
///\r
- UINT32 Page2M:1;\r
+ UINT32 Page2M : 1;\r
///\r
/// [Bits 2] 4MB page size entries supported by this structure.\r
///\r
- UINT32 Page4M:1;\r
+ UINT32 Page4M : 1;\r
///\r
/// [Bits 3] 1 GB page size entries supported by this structure.\r
///\r
- UINT32 Page1G:1;\r
+ UINT32 Page1G : 1;\r
///\r
/// [Bits 7:4] Reserved.\r
///\r
- UINT32 Reserved1:4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 10:8] Partitioning (0: Soft partitioning between the logical\r
/// processors sharing this structure)\r
///\r
- UINT32 Partitioning:3;\r
+ UINT32 Partitioning : 3;\r
///\r
/// [Bits 15:11] Reserved.\r
///\r
- UINT32 Reserved2:5;\r
+ UINT32 Reserved2 : 5;\r
///\r
/// [Bits 31:16] W = Ways of associativity.\r
///\r
- UINT32 Way:16;\r
+ UINT32 Way : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX;\r
\r
/**\r
///\r
/// [Bits 4:0] Translation cache type field.\r
///\r
- UINT32 TranslationCacheType:5;\r
+ UINT32 TranslationCacheType : 5;\r
///\r
/// [Bits 7:5] Translation cache level (starts at 1).\r
///\r
- UINT32 TranslationCacheLevel:3;\r
+ UINT32 TranslationCacheLevel : 3;\r
///\r
/// [Bits 8] Fully associative structure.\r
///\r
- UINT32 FullyAssociative:1;\r
+ UINT32 FullyAssociative : 1;\r
///\r
/// [Bits 13:9] Reserved.\r
///\r
- UINT32 Reserved1:5;\r
+ UINT32 Reserved1 : 5;\r
///\r
/// [Bits 25:14] Maximum number of addressable IDs for logical\r
/// processors sharing this translation cache.\r
///\r
- UINT32 MaximumNum:12;\r
+ UINT32 MaximumNum : 12;\r
///\r
/// [Bits 31:26] Reserved.\r
///\r
- UINT32 Reserved2:6;\r
+ UINT32 Reserved2 : 6;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX;\r
\r
///\r
/// @}\r
///\r
\r
-\r
/**\r
CPUID Hybrid Information Enumeration Leaf\r
\r
@endcode\r
\r
**/\r
-#define CPUID_HYBRID_INFORMATION 0x1A\r
+#define CPUID_HYBRID_INFORMATION 0x1A\r
\r
///\r
/// CPUID Hybrid Information Enumeration main leaf\r
///\r
-#define CPUID_HYBRID_INFORMATION_MAIN_LEAF 0x00\r
+#define CPUID_HYBRID_INFORMATION_MAIN_LEAF 0x00\r
\r
/**\r
CPUID Hybrid Information EAX for CPUID leaf #CPUID_HYBRID_INFORMATION,\r
/// across core types, and not related to the model ID reported in CPUID\r
/// leaf 01H, and does not identify the SOC.\r
///\r
- UINT32 NativeModelId:24;\r
+ UINT32 NativeModelId : 24;\r
///\r
/// [Bit 31:24] Core type\r
///\r
- UINT32 CoreType:8;\r
+ UINT32 CoreType : 8;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX;\r
\r
///\r
/// @{ Define value for CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX.CoreType\r
///\r
-#define CPUID_CORE_TYPE_INTEL_ATOM 0x20\r
-#define CPUID_CORE_TYPE_INTEL_CORE 0x40\r
+#define CPUID_CORE_TYPE_INTEL_ATOM 0x20\r
+#define CPUID_CORE_TYPE_INTEL_CORE 0x40\r
///\r
/// @}\r
///\r
\r
-\r
/**\r
CPUID V2 Extended Topology Enumeration Leaf\r
\r
@param ECX Level number\r
\r
**/\r
-#define CPUID_V2_EXTENDED_TOPOLOGY 0x1F\r
+#define CPUID_V2_EXTENDED_TOPOLOGY 0x1F\r
\r
///\r
/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType\r
/// The value of the "level type" field is not related to level numbers in\r
/// any way, higher "level type" values do not mean higher levels.\r
///\r
-#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03\r
-#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04\r
-#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05\r
+#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03\r
+#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04\r
+#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05\r
///\r
/// @}\r
///\r
AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_FUNCTION 0x80000000\r
-\r
+#define CPUID_EXTENDED_FUNCTION 0x80000000\r
\r
/**\r
CPUID Extended Processor Signature and Feature Bits\r
AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_CPU_SIG 0x80000001\r
+#define CPUID_EXTENDED_CPU_SIG 0x80000001\r
\r
/**\r
CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf\r
///\r
/// [Bit 0] LAHF/SAHF available in 64-bit mode.\r
///\r
- UINT32 LAHF_SAHF:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 LAHF_SAHF : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bit 5] LZCNT.\r
///\r
- UINT32 LZCNT:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 LZCNT : 1;\r
+ UINT32 Reserved2 : 2;\r
///\r
/// [Bit 8] PREFETCHW.\r
///\r
- UINT32 PREFETCHW:1;\r
- UINT32 Reserved3:23;\r
+ UINT32 PREFETCHW : 1;\r
+ UINT32 Reserved3 : 23;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_CPU_SIG_ECX;\r
\r
/**\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:11;\r
+ UINT32 Reserved1 : 11;\r
///\r
/// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.\r
///\r
- UINT32 SYSCALL_SYSRET:1;\r
- UINT32 Reserved2:8;\r
+ UINT32 SYSCALL_SYSRET : 1;\r
+ UINT32 Reserved2 : 8;\r
///\r
/// [Bit 20] Execute Disable Bit available.\r
///\r
- UINT32 NX:1;\r
- UINT32 Reserved3:5;\r
+ UINT32 NX : 1;\r
+ UINT32 Reserved3 : 5;\r
///\r
/// [Bit 26] 1-GByte pages are available if 1.\r
///\r
- UINT32 Page1GB:1;\r
+ UINT32 Page1GB : 1;\r
///\r
/// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.\r
///\r
- UINT32 RDTSCP:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 RDTSCP : 1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 29] Intel(R) 64 Architecture available if 1.\r
///\r
- UINT32 LM:1;\r
- UINT32 Reserved5:2;\r
+ UINT32 LM : 1;\r
+ UINT32 Reserved5 : 2;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_CPU_SIG_EDX;\r
\r
-\r
/**\r
CPUID Processor Brand String\r
\r
AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
@endcode\r
**/\r
-#define CPUID_BRAND_STRING1 0x80000002\r
+#define CPUID_BRAND_STRING1 0x80000002\r
\r
/**\r
CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,\r
///\r
/// 4 ASCII characters of Processor Brand String\r
///\r
- CHAR8 BrandString[4];\r
+ CHAR8 BrandString[4];\r
///\r
/// All fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_BRAND_STRING_DATA;\r
\r
/**\r
AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
@endcode\r
**/\r
-#define CPUID_BRAND_STRING2 0x80000003\r
+#define CPUID_BRAND_STRING2 0x80000003\r
\r
/**\r
CPUID Processor Brand String\r
AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
@endcode\r
**/\r
-#define CPUID_BRAND_STRING3 0x80000004\r
-\r
+#define CPUID_BRAND_STRING3 0x80000004\r
\r
/**\r
CPUID Extended Cache information\r
AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_CACHE_INFO 0x80000006\r
+#define CPUID_EXTENDED_CACHE_INFO 0x80000006\r
\r
/**\r
CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.\r
///\r
/// [Bits 7:0] Cache line size in bytes.\r
///\r
- UINT32 CacheLineSize:8;\r
- UINT32 Reserved:4;\r
+ UINT32 CacheLineSize : 8;\r
+ UINT32 Reserved : 4;\r
///\r
/// [Bits 15:12] L2 Associativity field. Supported values are in the range\r
/// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to\r
/// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL\r
///\r
- UINT32 L2Associativity:4;\r
+ UINT32 L2Associativity : 4;\r
///\r
/// [Bits 31:16] Cache size in 1K units.\r
///\r
- UINT32 CacheSize:16;\r
+ UINT32 CacheSize : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_CACHE_INFO_ECX;\r
\r
///\r
AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007\r
+#define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007\r
\r
/**\r
CPUID Extended Time Stamp Counter information EDX for CPUID leaf\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bit 8] Invariant TSC available if 1.\r
///\r
- UINT32 InvariantTsc:1;\r
- UINT32 Reserved2:23;\r
+ UINT32 InvariantTsc : 1;\r
+ UINT32 Reserved2 : 23;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX;\r
\r
-\r
/**\r
CPUID Linear Physical Address Size\r
\r
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);\r
@endcode\r
**/\r
-#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008\r
+#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008\r
\r
/**\r
CPUID Linear Physical Address Size EAX for CPUID leaf\r
/// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address\r
/// number supported should come from this field.\r
///\r
- UINT32 PhysicalAddressBits:8;\r
+ UINT32 PhysicalAddressBits : 8;\r
///\r
/// [Bits 15:8] Number of linear address bits.\r
///\r
- UINT32 LinearAddressBits:8;\r
- UINT32 Reserved:16;\r
+ UINT32 LinearAddressBits : 8;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_VIR_PHY_ADDRESS_SIZE_EAX;\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff