@endcode\r
@note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
**/\r
-#define MSR_CORE2_PLATFORM_ID 0x00000017\r
+#define MSR_CORE2_PLATFORM_ID 0x00000017\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r
///\r
- UINT32 MaximumQualifiedRatio:5;\r
- UINT32 Reserved2:19;\r
- UINT32 Reserved3:18;\r
+ UINT32 MaximumQualifiedRatio : 5;\r
+ UINT32 Reserved2 : 19;\r
+ UINT32 Reserved3 : 18;\r
///\r
/// [Bits 52:50] See Table 2-2.\r
///\r
- UINT32 PlatformId:3;\r
- UINT32 Reserved4:11;\r
+ UINT32 PlatformId : 3;\r
+ UINT32 Reserved4 : 11;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_PLATFORM_ID_REGISTER;\r
\r
-\r
/**\r
Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r
processor features; (R) indicates current processor configuration.\r
@endcode\r
@note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
**/\r
-#define MSR_CORE2_EBL_CR_POWERON 0x0000002A\r
+#define MSR_CORE2_EBL_CR_POWERON 0x0000002A\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
/// Note: Not all processor implements R/W.\r
///\r
- UINT32 DataErrorCheckingEnable:1;\r
+ UINT32 DataErrorCheckingEnable : 1;\r
///\r
/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
/// Note: Not all processor implements R/W.\r
///\r
- UINT32 ResponseErrorCheckingEnable:1;\r
+ UINT32 ResponseErrorCheckingEnable : 1;\r
///\r
/// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
/// all processor implements R/W.\r
///\r
- UINT32 MCERR_DriveEnable:1;\r
+ UINT32 MCERR_DriveEnable : 1;\r
///\r
/// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:\r
/// Not all processor implements R/W.\r
///\r
- UINT32 AddressParityEnable:1;\r
- UINT32 Reserved2:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 AddressParityEnable : 1;\r
+ UINT32 Reserved2 : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
/// all processor implements R/W.\r
///\r
- UINT32 BINIT_DriverEnable:1;\r
+ UINT32 BINIT_DriverEnable : 1;\r
///\r
/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 OutputTriStateEnable:1;\r
+ UINT32 OutputTriStateEnable : 1;\r
///\r
/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 ExecuteBIST:1;\r
+ UINT32 ExecuteBIST : 1;\r
///\r
/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 MCERR_ObservationEnabled:1;\r
+ UINT32 MCERR_ObservationEnabled : 1;\r
///\r
/// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present.\r
///\r
- UINT32 IntelTXTCapableChipset:1;\r
+ UINT32 IntelTXTCapableChipset : 1;\r
///\r
/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 BINIT_ObservationEnabled:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 BINIT_ObservationEnabled : 1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r
///\r
- UINT32 ResetVector:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 ResetVector : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bits 17:16] APIC Cluster ID (R/O).\r
///\r
- UINT32 APICClusterID:2;\r
+ UINT32 APICClusterID : 2;\r
///\r
/// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 =\r
/// Non-integer ratio.\r
///\r
- UINT32 NonIntegerBusRatio:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 NonIntegerBusRatio : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bits 21:20] Symmetric Arbitration ID (R/O).\r
///\r
- UINT32 SymmetricArbitrationID:2;\r
+ UINT32 SymmetricArbitrationID : 2;\r
///\r
/// [Bits 26:22] Integer Bus Frequency Ratio (R/O).\r
///\r
- UINT32 IntegerBusFrequencyRatio:5;\r
- UINT32 Reserved7:5;\r
- UINT32 Reserved8:32;\r
+ UINT32 IntegerBusFrequencyRatio : 5;\r
+ UINT32 Reserved7 : 5;\r
+ UINT32 Reserved8 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_EBL_CR_POWERON_REGISTER;\r
\r
-\r
/**\r
Unique. Control Features in Intel 64 Processor (R/W) See Table 2-2.\r
\r
@endcode\r
@note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_CORE2_FEATURE_CONTROL 0x0000003A\r
+#define MSR_CORE2_FEATURE_CONTROL 0x0000003A\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:3;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock\r
/// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read\r
/// visible and writeable while in SMM.\r
///\r
- UINT32 SMRREnable:1;\r
- UINT32 Reserved2:28;\r
- UINT32 Reserved3:32;\r
+ UINT32 SMRREnable : 1;\r
+ UINT32 Reserved2 : 28;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch\r
record registers on the last branch record stack. The From_IP part of the\r
MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
@{\r
**/\r
-#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040\r
-#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041\r
-#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042\r
-#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043\r
+#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040\r
+#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041\r
+#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042\r
+#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043\r
/// @}\r
\r
-\r
/**\r
Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch\r
record registers on the last branch record stack. This To_IP part of the\r
MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
@{\r
**/\r
-#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060\r
-#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061\r
-#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062\r
-#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063\r
+#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060\r
+#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061\r
+#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062\r
+#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063\r
/// @}\r
\r
-\r
/**\r
Unique. System Management Mode Base Address register (WO in SMM)\r
Model-specific implementation of SMRR-like interface, read visible and write\r
@endcode\r
@note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.\r
**/\r
-#define MSR_CORE2_SMRR_PHYSBASE 0x000000A0\r
+#define MSR_CORE2_SMRR_PHYSBASE 0x000000A0\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:12;\r
+ UINT32 Reserved1 : 12;\r
///\r
/// [Bits 31:12] PhysBase. SMRR physical Base Address.\r
///\r
- UINT32 PhysBase:20;\r
- UINT32 Reserved2:32;\r
+ UINT32 PhysBase : 20;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_SMRR_PHYSBASE_REGISTER;\r
\r
-\r
/**\r
Unique. System Management Mode Physical Address Mask register (WO in SMM)\r
Model-specific implementation of SMRR-like interface, read visible and write\r
@endcode\r
@note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.\r
**/\r
-#define MSR_CORE2_SMRR_PHYSMASK 0x000000A1\r
+#define MSR_CORE2_SMRR_PHYSMASK 0x000000A1\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:11;\r
+ UINT32 Reserved1 : 11;\r
///\r
/// [Bit 11] Valid. Physical address base and range mask are valid.\r
///\r
- UINT32 Valid:1;\r
+ UINT32 Valid : 1;\r
///\r
/// [Bits 31:12] PhysMask. SMRR physical address range mask.\r
///\r
- UINT32 PhysMask:20;\r
- UINT32 Reserved2:32;\r
+ UINT32 PhysMask : 20;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_SMRR_PHYSMASK_REGISTER;\r
\r
-\r
/**\r
Shared. Scalable Bus Speed(RO) This field indicates the intended scalable\r
bus clock speed for processors based on Intel Core microarchitecture:.\r
@endcode\r
@note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
**/\r
-#define MSR_CORE2_FSB_FREQ 0x000000CD\r
+#define MSR_CORE2_FSB_FREQ 0x000000CD\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_FSB_FREQ\r
/// Bus Speed when encoding is 000B. 333.33 MHz should be utilized if\r
/// performing calculation with System Bus Speed when encoding is 100B.\r
///\r
- UINT32 ScalableBusSpeed:3;\r
- UINT32 Reserved1:29;\r
- UINT32 Reserved2:32;\r
+ UINT32 ScalableBusSpeed : 3;\r
+ UINT32 Reserved1 : 29;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_FSB_FREQ_REGISTER;\r
\r
/**\r
@endcode\r
@note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r
**/\r
-#define MSR_CORE2_PERF_STATUS 0x00000198\r
+#define MSR_CORE2_PERF_STATUS 0x00000198\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_PERF_STATUS\r
///\r
/// [Bits 15:0] Current Performance State Value.\r
///\r
- UINT32 CurrentPerformanceStateValue:16;\r
- UINT32 Reserved1:15;\r
+ UINT32 CurrentPerformanceStateValue : 16;\r
+ UINT32 Reserved1 : 15;\r
///\r
/// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default\r
/// is cleared.\r
///\r
- UINT32 XEOperation:1;\r
- UINT32 Reserved2:8;\r
+ UINT32 XEOperation : 1;\r
+ UINT32 Reserved2 : 8;\r
///\r
/// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio\r
/// configured for the processor.\r
///\r
- UINT32 MaximumBusRatio:5;\r
- UINT32 Reserved3:1;\r
+ UINT32 MaximumBusRatio : 5;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio\r
/// is enabled. Applies processors based on Enhanced Intel Core\r
/// microarchitecture.\r
///\r
- UINT32 NonIntegerBusRatio:1;\r
- UINT32 Reserved4:17;\r
+ UINT32 NonIntegerBusRatio : 1;\r
+ UINT32 Reserved4 : 17;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_PERF_STATUS_REGISTER;\r
\r
-\r
/**\r
Unique.\r
\r
@endcode\r
@note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
**/\r
-#define MSR_CORE2_THERM2_CTL 0x0000019D\r
+#define MSR_CORE2_THERM2_CTL 0x0000019D\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_THERM2_CTL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
/// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
/// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.\r
///\r
- UINT32 TM_SELECT:1;\r
- UINT32 Reserved2:15;\r
- UINT32 Reserved3:32;\r
+ UINT32 TM_SELECT : 1;\r
+ UINT32 Reserved2 : 15;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_THERM2_CTL_REGISTER;\r
\r
-\r
/**\r
Enable Misc. Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE\r
///\r
/// [Bit 0] Fast-Strings Enable See Table 2-2.\r
///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 FastStrings : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
/// Table 2-2.\r
///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 AutomaticThermalControlCircuit : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the\r
/// hardware prefetcher operation on streams of data. When clear\r
/// (default), enables the prefetch queue. Disabling of the hardware\r
/// prefetcher may impact processor performance.\r
///\r
- UINT32 HardwarePrefetcherDisable:1;\r
+ UINT32 HardwarePrefetcherDisable : 1;\r
///\r
/// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r
/// the processor to indicate a pending break event within the processor 0\r
/// = Indicates compatible FERR# signaling behavior This bit must be set\r
/// to 1 to support XAPIC interrupt model usage.\r
///\r
- UINT32 FERR:1;\r
+ UINT32 FERR : 1;\r
///\r
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 2-2.\r
///\r
- UINT32 PEBS:1;\r
+ UINT32 PEBS : 1;\r
///\r
/// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r
/// thermal sensor indicates that the die temperature is at the\r
/// contents of the TM2 bit location. The processor is operating out of\r
/// specification if both this bit and the TM1 bit are set to 0.\r
///\r
- UINT32 TM2:1;\r
- UINT32 Reserved4:2;\r
+ UINT32 TM2 : 1;\r
+ UINT32 Reserved4 : 2;\r
///\r
/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
/// Table 2-2.\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
- UINT32 MONITOR:1;\r
+ UINT32 MONITOR : 1;\r
///\r
/// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set\r
/// to 1, the processor fetches the cache line that contains data\r
/// validation and testing. BIOS may contain a setup option that controls\r
/// the setting of this bit.\r
///\r
- UINT32 AdjacentCacheLinePrefetchDisable:1;\r
+ UINT32 AdjacentCacheLinePrefetchDisable : 1;\r
///\r
/// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock\r
/// (R/WO) When set, this bit causes the following bits to become\r
/// be set before an Enhanced Intel SpeedStep Technology transition is\r
/// requested. This bit is cleared on reset.\r
///\r
- UINT32 EISTLock:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 EISTLock : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2.\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
+ UINT32 LimitCpuidMaxval : 1;\r
///\r
/// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
+ UINT32 xTPR_Message_Disable : 1;\r
+ UINT32 Reserved7 : 8;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:2;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved9 : 2;\r
///\r
/// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU\r
/// L1 data cache prefetcher is disabled. The default value after reset is\r
/// assumes the next line will be required. The next line is prefetched in\r
/// to the L1 data cache from memory or L2.\r
///\r
- UINT32 DCUPrefetcherDisable:1;\r
+ UINT32 DCUPrefetcherDisable : 1;\r
///\r
/// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that\r
/// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled\r
/// power-on default value is 1, IDA is available in the processor. If\r
/// power-on default value is 0, IDA is not available.\r
///\r
- UINT32 IDADisable:1;\r
+ UINT32 IDADisable : 1;\r
///\r
/// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP\r
/// prefetcher is disabled. The default value after reset is 0. BIOS may\r
/// to determine whether to prefetch the next expected data into the L1\r
/// cache from memory or L2.\r
///\r
- UINT32 IPPrefetcherDisable:1;\r
- UINT32 Reserved10:24;\r
+ UINT32 IPPrefetcherDisable : 1;\r
+ UINT32 Reserved10 : 24;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
that points to the MSR containing the most recent branch record. See\r
@endcode\r
@note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_CORE2_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_CORE2_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r
@endcode\r
@note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
-#define MSR_CORE2_LER_FROM_LIP 0x000001DD\r
-\r
+#define MSR_CORE2_LER_FROM_LIP 0x000001DD\r
\r
/**\r
Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r
@endcode\r
@note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
-#define MSR_CORE2_LER_TO_LIP 0x000001DE\r
-\r
+#define MSR_CORE2_LER_TO_LIP 0x000001DE\r
\r
/**\r
Unique. Fixed-Function Performance Counter Register n (R/W).\r
MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM.\r
@{\r
**/\r
-#define MSR_CORE2_PERF_FIXED_CTR0 0x00000309\r
-#define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A\r
-#define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B\r
+#define MSR_CORE2_PERF_FIXED_CTR0 0x00000309\r
+#define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A\r
+#define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B\r
/// @}\r
\r
-\r
/**\r
Unique. RO. This applies to processors that do not support architectural\r
perfmon version 2.\r
@endcode\r
@note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM.\r
**/\r
-#define MSR_CORE2_PERF_CAPABILITIES 0x00000345\r
+#define MSR_CORE2_PERF_CAPABILITIES 0x00000345\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES\r
///\r
/// [Bits 5:0] LBR Format. See Table 2-2.\r
///\r
- UINT32 LBR_FMT:6;\r
+ UINT32 LBR_FMT : 6;\r
///\r
/// [Bit 6] PEBS Record Format.\r
///\r
- UINT32 PEBS_FMT:1;\r
+ UINT32 PEBS_FMT : 1;\r
///\r
/// [Bit 7] PEBSSaveArchRegs. See Table 2-2.\r
///\r
- UINT32 PEBS_ARCH_REG:1;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
+ UINT32 PEBS_ARCH_REG : 1;\r
+ UINT32 Reserved1 : 24;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_PERF_CAPABILITIES_REGISTER;\r
\r
-\r
/**\r
Unique. Fixed-Function-Counter Control Register (R/W).\r
\r
@endcode\r
@note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM.\r
**/\r
-#define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D\r
-\r
+#define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D\r
\r
/**\r
Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
@endcode\r
@note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E\r
-\r
+#define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E\r
\r
/**\r
Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
@endcode\r
@note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM.\r
**/\r
-#define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F\r
-\r
+#define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F\r
\r
/**\r
Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
@endcode\r
@note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.\r
**/\r
-#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390\r
-\r
+#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390\r
\r
/**\r
Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
@endcode\r
@note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_CORE2_PEBS_ENABLE 0x000003F1\r
+#define MSR_CORE2_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE\r
///\r
/// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 Enable : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon\r
processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.\r
MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.\r
@{\r
**/\r
-#define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC\r
-#define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD\r
-#define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE\r
-#define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF\r
-#define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0\r
-#define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1\r
-#define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2\r
-#define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3\r
+#define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC\r
+#define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD\r
+#define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE\r
+#define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF\r
+#define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0\r
+#define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1\r
+#define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2\r
+#define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3\r
/// @}\r
\r
-\r
/**\r
Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor\r
7400 series (processor signature 06_1D) only. See Section 17.2.2.\r
@endcode\r
@note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM.\r
**/\r
-#define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8\r
+#define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff