@endcode\r
@note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
**/\r
-#define MSR_CORE_P5_MC_ADDR 0x00000000\r
-\r
+#define MSR_CORE_P5_MC_ADDR 0x00000000\r
\r
/**\r
Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.\r
@endcode\r
@note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
**/\r
-#define MSR_CORE_P5_MC_TYPE 0x00000001\r
-\r
+#define MSR_CORE_P5_MC_TYPE 0x00000001\r
\r
/**\r
Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r
@endcode\r
@note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
**/\r
-#define MSR_CORE_EBL_CR_POWERON 0x0000002A\r
+#define MSR_CORE_EBL_CR_POWERON 0x0000002A\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
/// Note: Not all processor implements R/W.\r
///\r
- UINT32 DataErrorCheckingEnable:1;\r
+ UINT32 DataErrorCheckingEnable : 1;\r
///\r
/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
/// Note: Not all processor implements R/W.\r
///\r
- UINT32 ResponseErrorCheckingEnable:1;\r
+ UINT32 ResponseErrorCheckingEnable : 1;\r
///\r
/// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
/// all processor implements R/W.\r
///\r
- UINT32 MCERR_DriveEnable:1;\r
+ UINT32 MCERR_DriveEnable : 1;\r
///\r
/// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:\r
/// Not all processor implements R/W.\r
///\r
- UINT32 AddressParityEnable:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 AddressParityEnable : 1;\r
+ UINT32 Reserved2 : 2;\r
///\r
/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
/// all processor implements R/W.\r
///\r
- UINT32 BINIT_DriverEnable:1;\r
+ UINT32 BINIT_DriverEnable : 1;\r
///\r
/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 OutputTriStateEnable:1;\r
+ UINT32 OutputTriStateEnable : 1;\r
///\r
/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 ExecuteBIST:1;\r
+ UINT32 ExecuteBIST : 1;\r
///\r
/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 MCERR_ObservationEnabled:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 MCERR_ObservationEnabled : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 BINIT_ObservationEnabled:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 BINIT_ObservationEnabled : 1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r
///\r
- UINT32 ResetVector:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 ResetVector : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bits 17:16] APIC Cluster ID (R/O).\r
///\r
- UINT32 APICClusterID:2;\r
+ UINT32 APICClusterID : 2;\r
///\r
/// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.\r
///\r
- UINT32 SystemBusFrequency:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 SystemBusFrequency : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bits 21:20] Symmetric Arbitration ID (R/O).\r
///\r
- UINT32 SymmetricArbitrationID:2;\r
+ UINT32 SymmetricArbitrationID : 2;\r
///\r
/// [Bits 26:22] Clock Frequency Ratio (R/O).\r
///\r
- UINT32 ClockFrequencyRatio:5;\r
- UINT32 Reserved7:5;\r
- UINT32 Reserved8:32;\r
+ UINT32 ClockFrequencyRatio : 5;\r
+ UINT32 Reserved7 : 5;\r
+ UINT32 Reserved8 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE_EBL_CR_POWERON_REGISTER;\r
\r
-\r
/**\r
Unique. Last Branch Record n (R/W) One of 8 last branch record registers on\r
the last branch record stack: bits 31-0 hold the 'from' address and bits\r
MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.\r
@{\r
**/\r
-#define MSR_CORE_LASTBRANCH_0 0x00000040\r
-#define MSR_CORE_LASTBRANCH_1 0x00000041\r
-#define MSR_CORE_LASTBRANCH_2 0x00000042\r
-#define MSR_CORE_LASTBRANCH_3 0x00000043\r
-#define MSR_CORE_LASTBRANCH_4 0x00000044\r
-#define MSR_CORE_LASTBRANCH_5 0x00000045\r
-#define MSR_CORE_LASTBRANCH_6 0x00000046\r
-#define MSR_CORE_LASTBRANCH_7 0x00000047\r
+#define MSR_CORE_LASTBRANCH_0 0x00000040\r
+#define MSR_CORE_LASTBRANCH_1 0x00000041\r
+#define MSR_CORE_LASTBRANCH_2 0x00000042\r
+#define MSR_CORE_LASTBRANCH_3 0x00000043\r
+#define MSR_CORE_LASTBRANCH_4 0x00000044\r
+#define MSR_CORE_LASTBRANCH_5 0x00000045\r
+#define MSR_CORE_LASTBRANCH_6 0x00000046\r
+#define MSR_CORE_LASTBRANCH_7 0x00000047\r
/// @}\r
\r
-\r
/**\r
Shared. Scalable Bus Speed (RO) This field indicates the scalable bus\r
clock speed:.\r
@endcode\r
@note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
**/\r
-#define MSR_CORE_FSB_FREQ 0x000000CD\r
+#define MSR_CORE_FSB_FREQ 0x000000CD\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE_FSB_FREQ\r
/// Speed when encoding is 101B. 166.67 MHz should be utilized if\r
/// performing calculation with System Bus Speed when encoding is 001B.\r
///\r
- UINT32 ScalableBusSpeed:3;\r
- UINT32 Reserved1:29;\r
- UINT32 Reserved2:32;\r
+ UINT32 ScalableBusSpeed : 3;\r
+ UINT32 Reserved1 : 29;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE_FSB_FREQ_REGISTER;\r
\r
-\r
/**\r
Shared.\r
\r
@endcode\r
@note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
**/\r
-#define MSR_CORE_BBL_CR_CTL3 0x0000011E\r
+#define MSR_CORE_BBL_CR_CTL3 0x0000011E\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3\r
/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
/// Indicates if the L2 is hardware-disabled.\r
///\r
- UINT32 L2HardwareEnabled:1;\r
- UINT32 Reserved1:7;\r
+ UINT32 L2HardwareEnabled : 1;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r
/// Disabled (default) Until this bit is set the processor will not\r
/// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
///\r
- UINT32 L2Enabled:1;\r
- UINT32 Reserved2:14;\r
+ UINT32 L2Enabled : 1;\r
+ UINT32 Reserved2 : 14;\r
///\r
/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
///\r
- UINT32 L2NotPresent:1;\r
- UINT32 Reserved3:8;\r
- UINT32 Reserved4:32;\r
+ UINT32 L2NotPresent : 1;\r
+ UINT32 Reserved3 : 8;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE_BBL_CR_CTL3_REGISTER;\r
\r
-\r
/**\r
Unique.\r
\r
@endcode\r
@note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
**/\r
-#define MSR_CORE_THERM2_CTL 0x0000019D\r
+#define MSR_CORE_THERM2_CTL 0x0000019D\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE_THERM2_CTL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
/// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
/// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.\r
///\r
- UINT32 TM_SELECT:1;\r
- UINT32 Reserved2:15;\r
- UINT32 Reserved3:32;\r
+ UINT32 TM_SELECT : 1;\r
+ UINT32 Reserved2 : 15;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE_THERM2_CTL_REGISTER;\r
\r
-\r
/**\r
Enable Miscellaneous Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_CORE_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_CORE_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:3;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
/// Table 2-2.\r
///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 AutomaticThermalControlCircuit : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r
/// the processor to indicate a pending break event within the processor 0\r
/// = Indicates compatible FERR# signaling behavior This bit must be set\r
/// to 1 to support XAPIC interrupt model usage.\r
///\r
- UINT32 FERR:1;\r
+ UINT32 FERR : 1;\r
///\r
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
- UINT32 BTS:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 BTS : 1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r
/// thermal sensor indicates that the die temperature is at the\r
/// out of spec if both this bit and the TM1 bit are set to disabled\r
/// states.\r
///\r
- UINT32 TM2:1;\r
- UINT32 Reserved5:2;\r
+ UINT32 TM2 : 1;\r
+ UINT32 Reserved5 : 2;\r
///\r
/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =\r
/// Enhanced Intel SpeedStep Technology enabled.\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved7:1;\r
- UINT32 Reserved8:2;\r
+ UINT32 MONITOR : 1;\r
+ UINT32 Reserved7 : 1;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2. Setting this\r
/// bit may cause behavior in software that depends on the availability of\r
/// CPUID leaves greater than 2.\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
- UINT32 Reserved9:9;\r
- UINT32 Reserved10:2;\r
+ UINT32 LimitCpuidMaxval : 1;\r
+ UINT32 Reserved9 : 9;\r
+ UINT32 Reserved10 : 2;\r
///\r
/// [Bit 34] Shared. XD Bit Disable (R/W) See Table 2-2.\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved11:29;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved11 : 29;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
that points to the MSR containing the most recent branch record. See\r
@endcode\r
@note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_CORE_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_CORE_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r
@endcode\r
@note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
-#define MSR_CORE_LER_FROM_LIP 0x000001DD\r
-\r
+#define MSR_CORE_LER_FROM_LIP 0x000001DD\r
\r
/**\r
Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r
@endcode\r
@note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
-#define MSR_CORE_LER_TO_LIP 0x000001DE\r
+#define MSR_CORE_LER_TO_LIP 0x000001DE\r
\r
/**\r
Unique.\r
MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.\r
@{\r
**/\r
-#define MSR_CORE_MTRRPHYSBASE0 0x00000200\r
-#define MSR_CORE_MTRRPHYSBASE1 0x00000202\r
-#define MSR_CORE_MTRRPHYSBASE2 0x00000204\r
-#define MSR_CORE_MTRRPHYSBASE3 0x00000206\r
-#define MSR_CORE_MTRRPHYSBASE4 0x00000208\r
-#define MSR_CORE_MTRRPHYSBASE5 0x0000020A\r
-#define MSR_CORE_MTRRPHYSMASK6 0x0000020D\r
-#define MSR_CORE_MTRRPHYSMASK7 0x0000020F\r
+#define MSR_CORE_MTRRPHYSBASE0 0x00000200\r
+#define MSR_CORE_MTRRPHYSBASE1 0x00000202\r
+#define MSR_CORE_MTRRPHYSBASE2 0x00000204\r
+#define MSR_CORE_MTRRPHYSBASE3 0x00000206\r
+#define MSR_CORE_MTRRPHYSBASE4 0x00000208\r
+#define MSR_CORE_MTRRPHYSBASE5 0x0000020A\r
+#define MSR_CORE_MTRRPHYSMASK6 0x0000020D\r
+#define MSR_CORE_MTRRPHYSMASK7 0x0000020F\r
/// @}\r
\r
-\r
/**\r
Unique.\r
\r
MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.\r
@{\r
**/\r
-#define MSR_CORE_MTRRPHYSMASK0 0x00000201\r
-#define MSR_CORE_MTRRPHYSMASK1 0x00000203\r
-#define MSR_CORE_MTRRPHYSMASK2 0x00000205\r
-#define MSR_CORE_MTRRPHYSMASK3 0x00000207\r
-#define MSR_CORE_MTRRPHYSMASK4 0x00000209\r
-#define MSR_CORE_MTRRPHYSMASK5 0x0000020B\r
-#define MSR_CORE_MTRRPHYSBASE6 0x0000020C\r
-#define MSR_CORE_MTRRPHYSBASE7 0x0000020E\r
+#define MSR_CORE_MTRRPHYSMASK0 0x00000201\r
+#define MSR_CORE_MTRRPHYSMASK1 0x00000203\r
+#define MSR_CORE_MTRRPHYSMASK2 0x00000205\r
+#define MSR_CORE_MTRRPHYSMASK3 0x00000207\r
+#define MSR_CORE_MTRRPHYSMASK4 0x00000209\r
+#define MSR_CORE_MTRRPHYSMASK5 0x0000020B\r
+#define MSR_CORE_MTRRPHYSBASE6 0x0000020C\r
+#define MSR_CORE_MTRRPHYSBASE7 0x0000020E\r
/// @}\r
\r
-\r
/**\r
Unique.\r
\r
@endcode\r
@note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX64K_00000 0x00000250\r
-\r
+#define MSR_CORE_MTRRFIX64K_00000 0x00000250\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX16K_80000 0x00000258\r
-\r
+#define MSR_CORE_MTRRFIX16K_80000 0x00000258\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX16K_A0000 0x00000259\r
-\r
+#define MSR_CORE_MTRRFIX16K_A0000 0x00000259\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_C0000 0x00000268\r
-\r
+#define MSR_CORE_MTRRFIX4K_C0000 0x00000268\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_C8000 0x00000269\r
-\r
+#define MSR_CORE_MTRRFIX4K_C8000 0x00000269\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_D0000 0x0000026A\r
-\r
+#define MSR_CORE_MTRRFIX4K_D0000 0x0000026A\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_D8000 0x0000026B\r
-\r
+#define MSR_CORE_MTRRFIX4K_D8000 0x0000026B\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_E0000 0x0000026C\r
-\r
+#define MSR_CORE_MTRRFIX4K_E0000 0x0000026C\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_E8000 0x0000026D\r
-\r
+#define MSR_CORE_MTRRFIX4K_E8000 0x0000026D\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_F0000 0x0000026E\r
-\r
+#define MSR_CORE_MTRRFIX4K_F0000 0x0000026E\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_F8000 0x0000026F\r
-\r
+#define MSR_CORE_MTRRFIX4K_F8000 0x0000026F\r
\r
/**\r
Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
@endcode\r
@note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
**/\r
-#define MSR_CORE_MC4_CTL 0x0000040C\r
-\r
+#define MSR_CORE_MC4_CTL 0x0000040C\r
\r
/**\r
Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
@endcode\r
@note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
**/\r
-#define MSR_CORE_MC4_STATUS 0x0000040D\r
-\r
+#define MSR_CORE_MC4_STATUS 0x0000040D\r
\r
/**\r
Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR\r
@endcode\r
@note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
**/\r
-#define MSR_CORE_MC4_ADDR 0x0000040E\r
-\r
+#define MSR_CORE_MC4_ADDR 0x0000040E\r
\r
/**\r
Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR\r
@endcode\r
@note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
**/\r
-#define MSR_CORE_MC3_ADDR 0x00000412\r
-\r
+#define MSR_CORE_MC3_ADDR 0x00000412\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.\r
**/\r
-#define MSR_CORE_MC3_MISC 0x00000413\r
-\r
+#define MSR_CORE_MC3_MISC 0x00000413\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
**/\r
-#define MSR_CORE_MC5_CTL 0x00000414\r
-\r
+#define MSR_CORE_MC5_CTL 0x00000414\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
**/\r
-#define MSR_CORE_MC5_STATUS 0x00000415\r
-\r
+#define MSR_CORE_MC5_STATUS 0x00000415\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
**/\r
-#define MSR_CORE_MC5_ADDR 0x00000416\r
-\r
+#define MSR_CORE_MC5_ADDR 0x00000416\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
**/\r
-#define MSR_CORE_MC5_MISC 0x00000417\r
-\r
+#define MSR_CORE_MC5_MISC 0x00000417\r
\r
/**\r
Unique. See Table 2-2.\r
@endcode\r
@note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.\r
**/\r
-#define MSR_CORE_IA32_EFER 0xC0000080\r
+#define MSR_CORE_IA32_EFER 0xC0000080\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE_IA32_EFER\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:11;\r
+ UINT32 Reserved1 : 11;\r
///\r
/// [Bit 11] Execute Disable Bit Enable.\r
///\r
- UINT32 NXE:1;\r
- UINT32 Reserved2:20;\r
- UINT32 Reserved3:32;\r
+ UINT32 NXE : 1;\r
+ UINT32 Reserved2 : 20;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE_IA32_EFER_REGISTER;\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff