@endcode\r
@note MSR_GOLDMONT_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_GOLDMONT_FEATURE_CONTROL 0x0000003A\r
+#define MSR_GOLDMONT_FEATURE_CONTROL 0x0000003A\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_FEATURE_CONTROL\r
///\r
/// [Bit 0] Lock bit (R/WL)\r
///\r
- UINT32 Lock:1;\r
+ UINT32 Lock : 1;\r
///\r
/// [Bit 1] Enable VMX inside SMX operation (R/WL)\r
///\r
- UINT32 EnableVmxInsideSmx:1;\r
+ UINT32 EnableVmxInsideSmx : 1;\r
///\r
/// [Bit 2] Enable VMX outside SMX operation (R/WL)\r
///\r
- UINT32 EnableVmxOutsideSmx:1;\r
- UINT32 Reserved1:5;\r
+ UINT32 EnableVmxOutsideSmx : 1;\r
+ UINT32 Reserved1 : 5;\r
///\r
/// [Bits 14:8] SENTER local function enables (R/WL)\r
///\r
- UINT32 SenterLocalFunctionEnables:7;\r
+ UINT32 SenterLocalFunctionEnables : 7;\r
///\r
/// [Bit 15] SENTER global functions enable (R/WL)\r
///\r
- UINT32 SenterGlobalEnable:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 SenterGlobalEnable : 1;\r
+ UINT32 Reserved2 : 2;\r
///\r
/// [Bit 18] SGX global functions enable (R/WL)\r
///\r
- UINT32 SgxEnable:1;\r
- UINT32 Reserved3:13;\r
- UINT32 Reserved4:32;\r
+ UINT32 SgxEnable : 1;\r
+ UINT32 Reserved3 : 13;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. See http://biosbits.org.\r
\r
@endcode\r
@note MSR_GOLDMONT_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
-#define MSR_GOLDMONT_PLATFORM_INFO 0x000000CE\r
+#define MSR_GOLDMONT_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
/// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
/// MHz.\r
///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
+ UINT32 MaximumNonTurboRatio : 8;\r
+ UINT32 Reserved2 : 12;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
/// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
/// Turbo mode is disabled.\r
///\r
- UINT32 RatioLimit:1;\r
+ UINT32 RatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
/// and when set to 0, indicates TDP Limit for Turbo mode is not\r
/// programmable.\r
///\r
- UINT32 TDPLimit:1;\r
+ UINT32 TDPLimit : 1;\r
///\r
/// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,\r
/// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to\r
/// specify an temperature offset.\r
///\r
- UINT32 TJOFFSET:1;\r
- UINT32 Reserved3:1;\r
- UINT32 Reserved4:8;\r
+ UINT32 TJOFFSET : 1;\r
+ UINT32 Reserved3 : 1;\r
+ UINT32 Reserved4 : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
/// minimum ratio (maximum efficiency) that the processor can operates, in\r
/// units of 100MHz.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved5:16;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
+ UINT32 Reserved5 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_PLATFORM_INFO_REGISTER;\r
\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are\r
processor specific C-state code names, unrelated to MWAIT extension C-state\r
@endcode\r
@note MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL\r
/// No limit 0001b: C1 0010b: C3 0011b: C6 0100b: C7 0101b: C7S 0110b: C8\r
/// 0111b: C9 1000b: C10.\r
///\r
- UINT32 Limit:4;\r
- UINT32 Reserved1:6;\r
+ UINT32 Limit : 4;\r
+ UINT32 Reserved1 : 6;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
/// IO_read instructions sent to IO register specified by\r
/// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
/// until next reset.\r
///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:16;\r
- UINT32 Reserved4:32;\r
+ UINT32 CFGLock : 1;\r
+ UINT32 Reserved3 : 16;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Core. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement.\r
Accessible only while in SMM.\r
@endcode\r
@note MSR_GOLDMONT_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
**/\r
-#define MSR_GOLDMONT_SMM_MCA_CAP 0x0000017D\r
+#define MSR_GOLDMONT_SMM_MCA_CAP 0x0000017D\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_SMM_MCA_CAP\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:26;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 26;\r
///\r
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
/// SMM code access restriction is supported and the\r
/// MSR_SMM_FEATURE_CONTROL is supported.\r
///\r
- UINT32 SMM_Code_Access_Chk:1;\r
+ UINT32 SMM_Code_Access_Chk : 1;\r
///\r
/// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
/// SMM long flow indicator is supported and the MSR_SMM_DELAYED is\r
/// supported.\r
///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 Long_Flow_Indication : 1;\r
+ UINT32 Reserved3 : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_SMM_MCA_CAP_REGISTER;\r
\r
-\r
/**\r
Enable Misc. Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_GOLDMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_GOLDMONT_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_GOLDMONT_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_IA32_MISC_ENABLE\r
///\r
/// [Bit 0] Core. Fast-Strings Enable See Table 2-2.\r
///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 FastStrings : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See\r
/// Table 2-2. Default value is 1.\r
///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 AutomaticThermalControlCircuit : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:3;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved3 : 3;\r
///\r
/// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 2-2.\r
///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved4:3;\r
+ UINT32 PEBS : 1;\r
+ UINT32 Reserved4 : 3;\r
///\r
/// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
/// Table 2-2.\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved6:3;\r
+ UINT32 MONITOR : 1;\r
+ UINT32 Reserved6 : 3;\r
///\r
/// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
+ UINT32 LimitCpuidMaxval : 1;\r
///\r
/// [Bit 23] Package. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
+ UINT32 xTPR_Message_Disable : 1;\r
+ UINT32 Reserved7 : 8;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:3;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved9 : 3;\r
///\r
/// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
/// that support Intel Turbo Boost Technology, the turbo mode feature is\r
/// in the processor. If power-on default value is 0, turbo mode is not\r
/// available.\r
///\r
- UINT32 TurboModeDisable:1;\r
- UINT32 Reserved10:25;\r
+ UINT32 TurboModeDisable : 1;\r
+ UINT32 Reserved10 : 25;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Miscellaneous Feature Control (R/W).\r
\r
@endcode\r
@note MSR_GOLDMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_GOLDMONT_MISC_FEATURE_CONTROL 0x000001A4\r
+#define MSR_GOLDMONT_MISC_FEATURE_CONTROL 0x000001A4\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_MISC_FEATURE_CONTROL\r
/// L2 hardware prefetcher, which fetches additional lines of code or data\r
/// into the L2 cache.\r
///\r
- UINT32 L2HardwarePrefetcherDisable:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 L2HardwarePrefetcherDisable : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
/// the L1 data cache prefetcher, which fetches the next cache line into\r
/// L1 data cache.\r
///\r
- UINT32 DCUHardwarePrefetcherDisable:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
+ UINT32 DCUHardwarePrefetcherDisable : 1;\r
+ UINT32 Reserved2 : 29;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. See http://biosbits.org.\r
\r
@endcode\r
@note MSR_GOLDMONT_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r
**/\r
-#define MSR_GOLDMONT_MISC_PWR_MGMT 0x000001AA\r
+#define MSR_GOLDMONT_MISC_PWR_MGMT 0x000001AA\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_MISC_PWR_MGMT\r
/// from processor cores; When 1, disables hardware coordination of\r
/// Enhanced Intel Speedstep Technology requests.\r
///\r
- UINT32 EISTHardwareCoordinationDisable:1;\r
- UINT32 Reserved1:21;\r
+ UINT32 EISTHardwareCoordinationDisable : 1;\r
+ UINT32 Reserved1 : 21;\r
///\r
/// [Bit 22] Thermal Interrupt Coordination Enable (R/W) If set, then\r
/// thermal interrupt on one core is routed to all cores.\r
///\r
- UINT32 ThermalInterruptCoordinationEnable:1;\r
- UINT32 Reserved2:9;\r
- UINT32 Reserved3:32;\r
+ UINT32 ThermalInterruptCoordinationEnable : 1;\r
+ UINT32 Reserved2 : 9;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER;\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies\r
Maximum Ratio Limit for each Core Group. Max ratio for groups with more\r
@endcode\r
@note MSR_GOLDMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_GOLDMONT_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_GOLDMONT_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_TURBO_RATIO_LIMIT\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 0 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup0:8;\r
+ UINT32 MaxRatioLimitGroup0 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for Active cores in Group 1\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 1 threshold and greater than Group 0 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup1:8;\r
+ UINT32 MaxRatioLimitGroup1 : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for Active cores in Group 2\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 2 threshold and greater than Group 1 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup2:8;\r
+ UINT32 MaxRatioLimitGroup2 : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for Active cores in Group 3\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 3 threshold and greater than Group 2 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup3:8;\r
+ UINT32 MaxRatioLimitGroup3 : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for Active cores in Group 4\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 4 threshold and greater than Group 3 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup4:8;\r
+ UINT32 MaxRatioLimitGroup4 : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for Active cores in Group 5\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 5 threshold and greater than Group 4 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup5:8;\r
+ UINT32 MaxRatioLimitGroup5 : 8;\r
///\r
/// [Bits 55:48] Package. Maximum Ratio Limit for Active cores in Group 6\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 6 threshold and greater than Group 5 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup6:8;\r
+ UINT32 MaxRatioLimitGroup6 : 8;\r
///\r
/// [Bits 63:56] Package. Maximum Ratio Limit for Active cores in Group 7\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 7 threshold and greater than Group 6 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup7:8;\r
+ UINT32 MaxRatioLimitGroup7 : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. Group Size of Active Cores for Turbo Mode Operation (RW) Writes of\r
0 threshold is ignored.\r
@endcode\r
@note MSR_GOLDMONT_TURBO_GROUP_CORECNT is defined as MSR_TURBO_GROUP_CORECNT in SDM.\r
**/\r
-#define MSR_GOLDMONT_TURBO_GROUP_CORECNT 0x000001AE\r
+#define MSR_GOLDMONT_TURBO_GROUP_CORECNT 0x000001AE\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_TURBO_GROUP_CORECNT\r
/// [Bits 7:0] Package. Group 0 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 0 Max Turbo Ratio limit.\r
///\r
- UINT32 CoreCountThresholdGroup0:8;\r
+ UINT32 CoreCountThresholdGroup0 : 8;\r
///\r
/// [Bits 15:8] Package. Group 1 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 1 Max Turbo Ratio limit. Must be\r
/// greater than Group 0 Core Count.\r
///\r
- UINT32 CoreCountThresholdGroup1:8;\r
+ UINT32 CoreCountThresholdGroup1 : 8;\r
///\r
/// [Bits 23:16] Package. Group 2 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 2 Max Turbo Ratio limit. Must be\r
/// greater than Group 1 Core Count.\r
///\r
- UINT32 CoreCountThresholdGroup2:8;\r
+ UINT32 CoreCountThresholdGroup2 : 8;\r
///\r
/// [Bits 31:24] Package. Group 3 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 3 Max Turbo Ratio limit. Must be\r
/// greater than Group 2 Core Count.\r
///\r
- UINT32 CoreCountThresholdGroup3:8;\r
+ UINT32 CoreCountThresholdGroup3 : 8;\r
///\r
/// [Bits 39:32] Package. Group 4 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 4 Max Turbo Ratio limit. Must be\r
/// greater than Group 3 Core Count.\r
///\r
- UINT32 CoreCountThresholdGroup4:8;\r
+ UINT32 CoreCountThresholdGroup4 : 8;\r
///\r
/// [Bits 47:40] Package. Group 5 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 5 Max Turbo Ratio limit. Must be\r
/// greater than Group 4 Core Count.\r
///\r
- UINT32 CoreCountThresholdGroup5:8;\r
+ UINT32 CoreCountThresholdGroup5 : 8;\r
///\r
/// [Bits 55:48] Package. Group 6 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 6 Max Turbo Ratio limit. Must be\r
/// greater than Group 5 Core Count.\r
///\r
- UINT32 CoreCountThresholdGroup6:8;\r
+ UINT32 CoreCountThresholdGroup6 : 8;\r
///\r
/// [Bits 63:56] Package. Group 7 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 7 Max Turbo Ratio limit. Must be\r
/// greater than Group 6 Core Count and not less than the total number of\r
/// processor cores in the package. E.g. specify 255.\r
///\r
- UINT32 CoreCountThresholdGroup7:8;\r
+ UINT32 CoreCountThresholdGroup7 : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r
"Filtering of Last Branch Records.".\r
@endcode\r
@note MSR_GOLDMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
**/\r
-#define MSR_GOLDMONT_LBR_SELECT 0x000001C8\r
+#define MSR_GOLDMONT_LBR_SELECT 0x000001C8\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_LBR_SELECT\r
///\r
/// [Bit 0] CPL_EQ_0.\r
///\r
- UINT32 CPL_EQ_0:1;\r
+ UINT32 CPL_EQ_0 : 1;\r
///\r
/// [Bit 1] CPL_NEQ_0.\r
///\r
- UINT32 CPL_NEQ_0:1;\r
+ UINT32 CPL_NEQ_0 : 1;\r
///\r
/// [Bit 2] JCC.\r
///\r
- UINT32 JCC:1;\r
+ UINT32 JCC : 1;\r
///\r
/// [Bit 3] NEAR_REL_CALL.\r
///\r
- UINT32 NEAR_REL_CALL:1;\r
+ UINT32 NEAR_REL_CALL : 1;\r
///\r
/// [Bit 4] NEAR_IND_CALL.\r
///\r
- UINT32 NEAR_IND_CALL:1;\r
+ UINT32 NEAR_IND_CALL : 1;\r
///\r
/// [Bit 5] NEAR_RET.\r
///\r
- UINT32 NEAR_RET:1;\r
+ UINT32 NEAR_RET : 1;\r
///\r
/// [Bit 6] NEAR_IND_JMP.\r
///\r
- UINT32 NEAR_IND_JMP:1;\r
+ UINT32 NEAR_IND_JMP : 1;\r
///\r
/// [Bit 7] NEAR_REL_JMP.\r
///\r
- UINT32 NEAR_REL_JMP:1;\r
+ UINT32 NEAR_REL_JMP : 1;\r
///\r
/// [Bit 8] FAR_BRANCH.\r
///\r
- UINT32 FAR_BRANCH:1;\r
+ UINT32 FAR_BRANCH : 1;\r
///\r
/// [Bit 9] EN_CALL_STACK.\r
///\r
- UINT32 EN_CALL_STACK:1;\r
- UINT32 Reserved1:22;\r
- UINT32 Reserved2:32;\r
+ UINT32 EN_CALL_STACK : 1;\r
+ UINT32 Reserved1 : 22;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_LBR_SELECT_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that\r
points to the MSR containing the most recent branch record. See\r
@endcode\r
@note MSR_GOLDMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_GOLDMONT_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_GOLDMONT_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Core. Power Control Register. See http://biosbits.org.\r
@endcode\r
@note MSR_GOLDMONT_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r
**/\r
-#define MSR_GOLDMONT_POWER_CTL 0x000001FC\r
+#define MSR_GOLDMONT_POWER_CTL 0x000001FC\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_POWER_CTL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the\r
/// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology\r
/// operating point when all execution cores enter MWAIT (C1).\r
///\r
- UINT32 C1EEnable:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
+ UINT32 C1EEnable : 1;\r
+ UINT32 Reserved2 : 30;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_POWER_CTL_REGISTER;\r
\r
-\r
/**\r
Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r
CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r
@endcode\r
@note MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM.\r
**/\r
-#define MSR_GOLDMONT_SGXOWNEREPOCH0 0x00000300\r
-\r
+#define MSR_GOLDMONT_SGXOWNEREPOCH0 0x00000300\r
\r
//\r
// Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the SDM.\r
//\r
-#define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0\r
-\r
+#define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0\r
\r
/**\r
Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of\r
@endcode\r
@note MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM.\r
**/\r
-#define MSR_GOLDMONT_SGXOWNEREPOCH1 0x00000301\r
-\r
+#define MSR_GOLDMONT_SGXOWNEREPOCH1 0x00000301\r
\r
//\r
// Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the SDM.\r
//\r
-#define MSR_GOLDMONT_SGXOWNER1 MSR_GOLDMONT_SGXOWNEREPOCH1\r
-\r
+#define MSR_GOLDMONT_SGXOWNER1 MSR_GOLDMONT_SGXOWNEREPOCH1\r
\r
/**\r
Core. See Table 2-2. See Section 18.2.4, "Architectural Performance\r
@endcode\r
@note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
**/\r
-#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
+#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
\r
/**\r
MSR information returned for MSR index\r
///\r
/// [Bit 0] Set 1 to clear Ovf_PMC0.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Set 1 to clear Ovf_PMC1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Set 1 to clear Ovf_PMC2.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Set 1 to clear Ovf_PMC3.\r
///\r
- UINT32 Ovf_PMC3:1;\r
- UINT32 Reserved1:28;\r
+ UINT32 Ovf_PMC3 : 1;\r
+ UINT32 Reserved1 : 28;\r
///\r
/// [Bit 32] Set 1 to clear Ovf_FixedCtr0.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Set 1 to clear Ovf_FixedCtr1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Set 1 to clear Ovf_FixedCtr2.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 20;\r
///\r
/// [Bit 55] Set 1 to clear Trace_ToPA_PMI.\r
///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 Trace_ToPA_PMI : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 58] Set 1 to clear LBR_Frz.\r
///\r
- UINT32 LBR_Frz:1;\r
+ UINT32 LBR_Frz : 1;\r
///\r
/// [Bit 59] Set 1 to clear CTR_Frz.\r
///\r
- UINT32 CTR_Frz:1;\r
+ UINT32 CTR_Frz : 1;\r
///\r
/// [Bit 60] Set 1 to clear ASCI.\r
///\r
- UINT32 ASCI:1;\r
+ UINT32 ASCI : 1;\r
///\r
/// [Bit 61] Set 1 to clear Ovf_Uncore.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Set 1 to clear Ovf_BufDSSAVE.\r
///\r
- UINT32 Ovf_BufDSSAVE:1;\r
+ UINT32 Ovf_BufDSSAVE : 1;\r
///\r
/// [Bit 63] Set 1 to clear CondChgd.\r
///\r
- UINT32 CondChgd:1;\r
+ UINT32 CondChgd : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
\r
-\r
/**\r
Core. See Table 2-2. See Section 18.2.4, "Architectural Performance\r
Monitoring Version 4.".\r
@endcode\r
@note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r
**/\r
-#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
+#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
\r
/**\r
MSR information returned for MSR index\r
///\r
/// [Bit 0] Set 1 to cause Ovf_PMC0 = 1.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Set 1 to cause Ovf_PMC1 = 1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Set 1 to cause Ovf_PMC2 = 1.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Set 1 to cause Ovf_PMC3 = 1.\r
///\r
- UINT32 Ovf_PMC3:1;\r
- UINT32 Reserved1:28;\r
+ UINT32 Ovf_PMC3 : 1;\r
+ UINT32 Reserved1 : 28;\r
///\r
/// [Bit 32] Set 1 to cause Ovf_FixedCtr0 = 1.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Set 1 to cause Ovf_FixedCtr1 = 1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Set 1 to cause Ovf_FixedCtr2 = 1.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 20;\r
///\r
/// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1.\r
///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 Trace_ToPA_PMI : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 58] Set 1 to cause LBR_Frz = 1.\r
///\r
- UINT32 LBR_Frz:1;\r
+ UINT32 LBR_Frz : 1;\r
///\r
/// [Bit 59] Set 1 to cause CTR_Frz = 1.\r
///\r
- UINT32 CTR_Frz:1;\r
+ UINT32 CTR_Frz : 1;\r
///\r
/// [Bit 60] Set 1 to cause ASCI = 1.\r
///\r
- UINT32 ASCI:1;\r
+ UINT32 ASCI : 1;\r
///\r
/// [Bit 61] Set 1 to cause Ovf_Uncore.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Set 1 to cause Ovf_BufDSSAVE.\r
///\r
- UINT32 Ovf_BufDSSAVE:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 Ovf_BufDSSAVE : 1;\r
+ UINT32 Reserved4 : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
\r
-\r
/**\r
Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
(PEBS).".\r
@endcode\r
@note MSR_GOLDMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_GOLDMONT_PEBS_ENABLE 0x000003F1\r
+#define MSR_GOLDMONT_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_PEBS_ENABLE\r
/// [Bit 0] Enable PEBS trigger and recording for the programmed event\r
/// (precise or otherwise) on IA32_PMC0. (R/W).\r
///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 Enable : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
@endcode\r
@note MSR_GOLDMONT_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_C3_RESIDENCY 0x000003F8\r
-\r
+#define MSR_GOLDMONT_PKG_C3_RESIDENCY 0x000003F8\r
\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_GOLDMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_C6_RESIDENCY 0x000003F9\r
-\r
+#define MSR_GOLDMONT_PKG_C6_RESIDENCY 0x000003F9\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_GOLDMONT_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r
**/\r
-#define MSR_GOLDMONT_CORE_C3_RESIDENCY 0x000003FC\r
-\r
+#define MSR_GOLDMONT_CORE_C3_RESIDENCY 0x000003FC\r
\r
/**\r
Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability\r
@endcode\r
@note MSR_GOLDMONT_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_GOLDMONT_SMM_FEATURE_CONTROL 0x000004E0\r
+#define MSR_GOLDMONT_SMM_FEATURE_CONTROL 0x000004E0\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_SMM_FEATURE_CONTROL\r
/// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from\r
/// further changes.\r
///\r
- UINT32 Lock:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 Lock : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if\r
/// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the\r
/// the package that attempts to execute SMM code not within the ranges\r
/// defined by the SMRR will assert an unrecoverable MCE.\r
///\r
- UINT32 SMM_Code_Chk_En:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
+ UINT32 SMM_Code_Chk_En : 1;\r
+ UINT32 Reserved2 : 29;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical\r
processors in the package. Available only while in SMM and\r
@endcode\r
@note MSR_GOLDMONT_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.\r
**/\r
-#define MSR_GOLDMONT_SMM_DELAYED 0x000004E2\r
-\r
+#define MSR_GOLDMONT_SMM_DELAYED 0x000004E2\r
\r
/**\r
Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical\r
@endcode\r
@note MSR_GOLDMONT_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.\r
**/\r
-#define MSR_GOLDMONT_SMM_BLOCKED 0x000004E3\r
-\r
+#define MSR_GOLDMONT_SMM_BLOCKED 0x000004E3\r
\r
/**\r
Core. Trace Control Register (R/W).\r
@endcode\r
@note MSR_GOLDMONT_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.\r
**/\r
-#define MSR_IA32_RTIT_CTL 0x00000570\r
+#define MSR_IA32_RTIT_CTL 0x00000570\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_RTIT_CTL\r
///\r
/// [Bit 0] TraceEn.\r
///\r
- UINT32 TraceEn:1;\r
+ UINT32 TraceEn : 1;\r
///\r
/// [Bit 1] CYCEn.\r
///\r
- UINT32 CYCEn:1;\r
+ UINT32 CYCEn : 1;\r
///\r
/// [Bit 2] OS.\r
///\r
- UINT32 OS:1;\r
+ UINT32 OS : 1;\r
///\r
/// [Bit 3] User.\r
///\r
- UINT32 User:1;\r
- UINT32 Reserved1:3;\r
+ UINT32 User : 1;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 7] CR3 filter.\r
///\r
- UINT32 CR3:1;\r
+ UINT32 CR3 : 1;\r
///\r
/// [Bit 8] ToPA. Writing 0 will #GP if also setting TraceEn.\r
///\r
- UINT32 ToPA:1;\r
+ UINT32 ToPA : 1;\r
///\r
/// [Bit 9] MTCEn.\r
///\r
- UINT32 MTCEn:1;\r
+ UINT32 MTCEn : 1;\r
///\r
/// [Bit 10] TSCEn.\r
///\r
- UINT32 TSCEn:1;\r
+ UINT32 TSCEn : 1;\r
///\r
/// [Bit 11] DisRETC.\r
///\r
- UINT32 DisRETC:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 DisRETC : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 13] BranchEn.\r
///\r
- UINT32 BranchEn:1;\r
+ UINT32 BranchEn : 1;\r
///\r
/// [Bits 17:14] MTCFreq.\r
///\r
- UINT32 MTCFreq:4;\r
- UINT32 Reserved3:1;\r
+ UINT32 MTCFreq : 4;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bits 22:19] CYCThresh.\r
///\r
- UINT32 CYCThresh:4;\r
- UINT32 Reserved4:1;\r
+ UINT32 CYCThresh : 4;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bits 27:24] PSBFreq.\r
///\r
- UINT32 PSBFreq:4;\r
- UINT32 Reserved5:4;\r
+ UINT32 PSBFreq : 4;\r
+ UINT32 Reserved5 : 4;\r
///\r
/// [Bits 35:32] ADDR0_CFG.\r
///\r
- UINT32 ADDR0_CFG:4;\r
+ UINT32 ADDR0_CFG : 4;\r
///\r
/// [Bits 39:36] ADDR1_CFG.\r
///\r
- UINT32 ADDR1_CFG:4;\r
- UINT32 Reserved6:24;\r
+ UINT32 ADDR1_CFG : 4;\r
+ UINT32 Reserved6 : 24;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER;\r
\r
-\r
/**\r
Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r
"RAPL Interfaces.".\r
@endcode\r
@note MSR_GOLDMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
-#define MSR_GOLDMONT_RAPL_POWER_UNIT 0x00000606\r
+#define MSR_GOLDMONT_RAPL_POWER_UNIT 0x00000606\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_RAPL_POWER_UNIT\r
/// 3:0. Default value is 1000b, indicating power unit is in 3.9\r
/// milliWatts increment.\r
///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
+ UINT32 PowerUnits : 4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 12:8] Energy Status Units. Energy related information (in\r
/// Joules) is in unit of, 1Joule/ (2^ESU); where ESU is an unsigned\r
/// integer represented by bits 12:8. Default value is 01110b, indicating\r
/// energy unit is in 61 microJoules.\r
///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
+ UINT32 EnergyStatusUnits : 5;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 19:16] Time Unit. Time related information (in seconds) is in\r
/// unit of, 1S/2^TU; where TU is an unsigned integer represented by bits\r
/// 19:16. Default value is 1010b, indicating power unit is in 0.977\r
/// millisecond.\r
///\r
- UINT32 TimeUnit:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
+ UINT32 TimeUnit : 4;\r
+ UINT32 Reserved3 : 12;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER;\r
\r
-\r
/**\r
Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are\r
processor specific C-state code names, unrelated to MWAIT extension C-state\r
@endcode\r
@note MSR_GOLDMONT_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKGC3_IRTL 0x0000060A\r
+#define MSR_GOLDMONT_PKGC3_IRTL 0x0000060A\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_PKGC3_IRTL\r
/// that should be used to decide if the package should be put into a\r
/// package C3 state.\r
///\r
- UINT32 InterruptResponseTimeLimit:10;\r
+ UINT32 InterruptResponseTimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
/// of the interrupt response time limit. See Table 2-19 for supported\r
/// time unit encodings.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_PKGC3_IRTL_REGISTER;\r
\r
-\r
/**\r
Package. Package C6/C7S Interrupt Response Limit 1 (R/W) This MSR defines\r
the interrupt response time limit used by the processor to manage transition\r
@endcode\r
@note MSR_GOLDMONT_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKGC_IRTL1 0x0000060B\r
+#define MSR_GOLDMONT_PKGC_IRTL1 0x0000060B\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL1\r
/// that should be used to decide if the package should be put into a\r
/// package C6 or C7S state.\r
///\r
- UINT32 InterruptResponseTimeLimit:10;\r
+ UINT32 InterruptResponseTimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
/// of the interrupt response time limit. See Table 2-19 for supported\r
/// time unit encodings.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_PKGC_IRTL1_REGISTER;\r
\r
-\r
/**\r
Package. Package C7 Interrupt Response Limit 2 (R/W) This MSR defines the\r
interrupt response time limit used by the processor to manage transition to\r
@endcode\r
@note MSR_GOLDMONT_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKGC_IRTL2 0x0000060C\r
+#define MSR_GOLDMONT_PKGC_IRTL2 0x0000060C\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL2\r
/// that should be used to decide if the package should be put into a\r
/// package C7 state.\r
///\r
- UINT32 InterruptResponseTimeLimit:10;\r
+ UINT32 InterruptResponseTimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
/// of the interrupt response time limit. See Table 2-19 for supported\r
/// time unit encodings.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_PKGC_IRTL2_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2\r
@endcode\r
@note MSR_GOLDMONT_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_C2_RESIDENCY 0x0000060D\r
-\r
+#define MSR_GOLDMONT_PKG_C2_RESIDENCY 0x0000060D\r
\r
/**\r
Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
@endcode\r
@note MSR_GOLDMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_POWER_LIMIT 0x00000610\r
-\r
+#define MSR_GOLDMONT_PKG_POWER_LIMIT 0x00000610\r
\r
/**\r
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
@endcode\r
@note MSR_GOLDMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_ENERGY_STATUS 0x00000611\r
-\r
+#define MSR_GOLDMONT_PKG_ENERGY_STATUS 0x00000611\r
\r
/**\r
Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
@endcode\r
@note MSR_GOLDMONT_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_PERF_STATUS 0x00000613\r
-\r
+#define MSR_GOLDMONT_PKG_PERF_STATUS 0x00000613\r
\r
/**\r
Package. PKG RAPL Parameters (R/W).\r
@endcode\r
@note MSR_GOLDMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_POWER_INFO 0x00000614\r
+#define MSR_GOLDMONT_PKG_POWER_INFO 0x00000614\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_PKG_POWER_INFO\r
/// [Bits 14:0] Thermal Spec Power (R/W) See Section 14.9.3, "Package\r
/// RAPL Domain.".\r
///\r
- UINT32 ThermalSpecPower:15;\r
- UINT32 Reserved1:1;\r
+ UINT32 ThermalSpecPower : 15;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 30:16] Minimum Power (R/W) See Section 14.9.3, "Package RAPL\r
/// Domain.".\r
///\r
- UINT32 MinimumPower:15;\r
- UINT32 Reserved2:1;\r
+ UINT32 MinimumPower : 15;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bits 46:32] Maximum Power (R/W) See Section 14.9.3, "Package RAPL\r
/// Domain.".\r
///\r
- UINT32 MaximumPower:15;\r
- UINT32 Reserved3:1;\r
+ UINT32 MaximumPower : 15;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bits 54:48] Maximum Time Window (R/W) Specified by 2^Y * (1.0 +\r
/// Z/4.0) * Time_Unit, where "Y" is the unsigned integer value\r
/// bits 54:53. "Time_Unit" is specified by the "Time Units" field of\r
/// MSR_RAPL_POWER_UNIT.\r
///\r
- UINT32 MaximumTimeWindow:7;\r
- UINT32 Reserved4:9;\r
+ UINT32 MaximumTimeWindow : 7;\r
+ UINT32 Reserved4 : 9;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_PKG_POWER_INFO_REGISTER;\r
\r
-\r
/**\r
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
Domain.".\r
@endcode\r
@note MSR_GOLDMONT_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_GOLDMONT_DRAM_POWER_LIMIT 0x00000618\r
-\r
+#define MSR_GOLDMONT_DRAM_POWER_LIMIT 0x00000618\r
\r
/**\r
Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_GOLDMONT_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_GOLDMONT_DRAM_ENERGY_STATUS 0x00000619\r
-\r
+#define MSR_GOLDMONT_DRAM_ENERGY_STATUS 0x00000619\r
\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
@endcode\r
@note MSR_GOLDMONT_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
-#define MSR_GOLDMONT_DRAM_PERF_STATUS 0x0000061B\r
-\r
+#define MSR_GOLDMONT_DRAM_PERF_STATUS 0x0000061B\r
\r
/**\r
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_GOLDMONT_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
**/\r
-#define MSR_GOLDMONT_DRAM_POWER_INFO 0x0000061C\r
-\r
+#define MSR_GOLDMONT_DRAM_POWER_INFO 0x0000061C\r
\r
/**\r
Package. Note: C-state values are processor specific C-state code names,.\r
@endcode\r
@note MSR_GOLDMONT_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_C10_RESIDENCY 0x00000632\r
-\r
+#define MSR_GOLDMONT_PKG_C10_RESIDENCY 0x00000632\r
\r
/**\r
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_GOLDMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_GOLDMONT_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_GOLDMONT_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_GOLDMONT_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_GOLDMONT_PP1_ENERGY_STATUS 0x00000641\r
-\r
+#define MSR_GOLDMONT_PP1_ENERGY_STATUS 0x00000641\r
\r
/**\r
Package. ConfigTDP Control (R/W).\r
@endcode\r
@note MSR_GOLDMONT_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
**/\r
-#define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO 0x0000064C\r
+#define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO 0x0000064C\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_TURBO_ACTIVATION_RATIO\r
/// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r
/// field.\r
///\r
- UINT32 MAX_NON_TURBO_RATIO:8;\r
- UINT32 Reserved1:23;\r
+ UINT32 MAX_NON_TURBO_RATIO : 8;\r
+ UINT32 Reserved1 : 23;\r
///\r
/// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r
/// content of this register is locked until a reset.\r
///\r
- UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r
- UINT32 Reserved2:32;\r
+ UINT32 TURBO_ACTIVATION_RATIO_Lock : 1;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER;\r
\r
-\r
/**\r
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
refers to processor core frequency).\r
@endcode\r
@note MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
**/\r
-#define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS 0x0000064F\r
+#define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS 0x0000064F\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS\r
/// reduced below the operating system request due to assertion of\r
/// external PROCHOT.\r
///\r
- UINT32 PROCHOTStatus:1;\r
+ UINT32 PROCHOTStatus : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
/// operating system request due to a thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
+ UINT32 ThermalStatus : 1;\r
///\r
/// [Bit 2] Package-Level Power Limiting PL1 Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL1.\r
///\r
- UINT32 PL1Status:1;\r
+ UINT32 PL1Status : 1;\r
///\r
/// [Bit 3] Package-Level PL2 Power Limiting Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL2.\r
///\r
- UINT32 PL2Status:1;\r
- UINT32 Reserved1:5;\r
+ UINT32 PL2Status : 1;\r
+ UINT32 Reserved1 : 5;\r
///\r
/// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced\r
/// below the operating system request due to domain-level power limiting.\r
///\r
- UINT32 PowerLimitingStatus:1;\r
+ UINT32 PowerLimitingStatus : 1;\r
///\r
/// [Bit 10] VR Therm Alert Status (R0) When set, frequency is reduced\r
/// below the operating system request due to a thermal alert from the\r
/// Voltage Regulator.\r
///\r
- UINT32 VRThermAlertStatus:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
///\r
/// [Bit 11] Max Turbo Limit Status (R0) When set, frequency is reduced\r
/// below the operating system request due to multi-core turbo limits.\r
///\r
- UINT32 MaxTurboLimitStatus:1;\r
+ UINT32 MaxTurboLimitStatus : 1;\r
///\r
/// [Bit 12] Electrical Design Point Status (R0) When set, frequency is\r
/// reduced below the operating system request due to electrical design\r
/// point constraints (e.g. maximum electrical current consumption).\r
///\r
- UINT32 ElectricalDesignPointStatus:1;\r
+ UINT32 ElectricalDesignPointStatus : 1;\r
///\r
/// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
/// is reduced below the operating system request due to Turbo transition\r
/// attenuation. This prevents performance degradation due to frequent\r
/// operating ratio changes.\r
///\r
- UINT32 TurboTransitionAttenuationStatus:1;\r
+ UINT32 TurboTransitionAttenuationStatus : 1;\r
///\r
/// [Bit 14] Maximum Efficiency Frequency Status (R0) When set, frequency\r
/// is reduced below the maximum efficiency frequency.\r
///\r
- UINT32 MaximumEfficiencyFrequencyStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 MaximumEfficiencyFrequencyStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT:1;\r
+ UINT32 PROCHOT : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
+ UINT32 ThermalLog : 1;\r
///\r
/// [Bit 18] Package-Level PL1 Power Limiting Log When set, indicates\r
/// that the Package Level PL1 Power Limiting Status bit has asserted\r
/// since the log bit was last cleared. This log bit will remain set until\r
/// cleared by software writing 0.\r
///\r
- UINT32 PL1Log:1;\r
+ UINT32 PL1Log : 1;\r
///\r
/// [Bit 19] Package-Level PL2 Power Limiting Log When set, indicates that\r
/// the Package Level PL2 Power Limiting Status bit has asserted since the\r
/// log bit was last cleared. This log bit will remain set until cleared\r
/// by software writing 0.\r
///\r
- UINT32 PL2Log:1;\r
- UINT32 Reserved3:5;\r
+ UINT32 PL2Log : 1;\r
+ UINT32 Reserved3 : 5;\r
///\r
/// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
/// Power Limiting Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 CorePowerLimitingLog:1;\r
+ UINT32 CorePowerLimitingLog : 1;\r
///\r
/// [Bit 26] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
+ UINT32 VRThermAlertLog : 1;\r
///\r
/// [Bit 27] Max Turbo Limit Log When set, indicates that the Max Turbo\r
/// Limit Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 MaxTurboLimitLog:1;\r
+ UINT32 MaxTurboLimitLog : 1;\r
///\r
/// [Bit 28] Electrical Design Point Log When set, indicates that the EDP\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 ElectricalDesignPointLog:1;\r
+ UINT32 ElectricalDesignPointLog : 1;\r
///\r
/// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
/// Turbo Transition Attenuation Status bit has asserted since the log bit\r
/// was last cleared. This log bit will remain set until cleared by\r
/// software writing 0.\r
///\r
- UINT32 TurboTransitionAttenuationLog:1;\r
+ UINT32 TurboTransitionAttenuationLog : 1;\r
///\r
/// [Bit 30] Maximum Efficiency Frequency Log When set, indicates that\r
/// the Maximum Efficiency Frequency Status bit has asserted since the log\r
/// bit was last cleared. This log bit will remain set until cleared by\r
/// software writing 0.\r
///\r
- UINT32 MaximumEfficiencyFrequencyLog:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:32;\r
+ UINT32 MaximumEfficiencyFrequencyLog : 1;\r
+ UINT32 Reserved4 : 1;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch\r
record registers on the last branch record stack. The From_IP part of the\r
MSR_GOLDMONT_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.\r
@{\r
**/\r
-#define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP 0x00000680\r
-#define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP 0x00000681\r
-#define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP 0x00000682\r
-#define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP 0x00000683\r
-#define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP 0x00000684\r
-#define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP 0x00000685\r
-#define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP 0x00000686\r
-#define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP 0x00000687\r
-#define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP 0x00000688\r
-#define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP 0x00000689\r
-#define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP 0x0000068A\r
-#define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP 0x0000068B\r
-#define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP 0x0000068C\r
-#define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP 0x0000068D\r
-#define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP 0x0000068E\r
-#define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP 0x0000068F\r
-#define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP 0x00000690\r
-#define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP 0x00000691\r
-#define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP 0x00000692\r
-#define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP 0x00000693\r
-#define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP 0x00000694\r
-#define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP 0x00000695\r
-#define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP 0x00000696\r
-#define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP 0x00000697\r
-#define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP 0x00000698\r
-#define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP 0x00000699\r
-#define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP 0x0000069A\r
-#define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP 0x0000069B\r
-#define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP 0x0000069C\r
-#define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP 0x0000069D\r
-#define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP 0x0000069E\r
-#define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP 0x0000069F\r
+#define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP 0x00000680\r
+#define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP 0x00000681\r
+#define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP 0x00000682\r
+#define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP 0x00000683\r
+#define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP 0x00000684\r
+#define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP 0x00000685\r
+#define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP 0x00000686\r
+#define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP 0x00000687\r
+#define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP 0x00000688\r
+#define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP 0x00000689\r
+#define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP 0x0000068A\r
+#define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP 0x0000068B\r
+#define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP 0x0000068C\r
+#define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP 0x0000068D\r
+#define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP 0x0000068E\r
+#define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP 0x0000068F\r
+#define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP 0x00000690\r
+#define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP 0x00000691\r
+#define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP 0x00000692\r
+#define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP 0x00000693\r
+#define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP 0x00000694\r
+#define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP 0x00000695\r
+#define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP 0x00000696\r
+#define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP 0x00000697\r
+#define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP 0x00000698\r
+#define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP 0x00000699\r
+#define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP 0x0000069A\r
+#define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP 0x0000069B\r
+#define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP 0x0000069C\r
+#define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP 0x0000069D\r
+#define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP 0x0000069E\r
+#define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP 0x0000069F\r
/// @}\r
\r
/**\r
///\r
/// [Bit 31:0] From Linear Address (R/W).\r
///\r
- UINT32 FromLinearAddress:32;\r
+ UINT32 FromLinearAddress : 32;\r
///\r
/// [Bit 47:32] From Linear Address (R/W).\r
///\r
- UINT32 FromLinearAddressHi:16;\r
+ UINT32 FromLinearAddressHi : 16;\r
///\r
/// [Bits 62:48] Signed extension of bits 47:0.\r
///\r
- UINT32 SignedExtension:15;\r
+ UINT32 SignedExtension : 15;\r
///\r
/// [Bit 63] Mispred.\r
///\r
- UINT32 Mispred:1;\r
+ UINT32 Mispred : 1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record\r
registers on the last branch record stack. The To_IP part of the stack\r
MSR_GOLDMONT_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.\r
@{\r
**/\r
-#define MSR_GOLDMONT_LASTBRANCH_0_TO_IP 0x000006C0\r
-#define MSR_GOLDMONT_LASTBRANCH_1_TO_IP 0x000006C1\r
-#define MSR_GOLDMONT_LASTBRANCH_2_TO_IP 0x000006C2\r
-#define MSR_GOLDMONT_LASTBRANCH_3_TO_IP 0x000006C3\r
-#define MSR_GOLDMONT_LASTBRANCH_4_TO_IP 0x000006C4\r
-#define MSR_GOLDMONT_LASTBRANCH_5_TO_IP 0x000006C5\r
-#define MSR_GOLDMONT_LASTBRANCH_6_TO_IP 0x000006C6\r
-#define MSR_GOLDMONT_LASTBRANCH_7_TO_IP 0x000006C7\r
-#define MSR_GOLDMONT_LASTBRANCH_8_TO_IP 0x000006C8\r
-#define MSR_GOLDMONT_LASTBRANCH_9_TO_IP 0x000006C9\r
-#define MSR_GOLDMONT_LASTBRANCH_10_TO_IP 0x000006CA\r
-#define MSR_GOLDMONT_LASTBRANCH_11_TO_IP 0x000006CB\r
-#define MSR_GOLDMONT_LASTBRANCH_12_TO_IP 0x000006CC\r
-#define MSR_GOLDMONT_LASTBRANCH_13_TO_IP 0x000006CD\r
-#define MSR_GOLDMONT_LASTBRANCH_14_TO_IP 0x000006CE\r
-#define MSR_GOLDMONT_LASTBRANCH_15_TO_IP 0x000006CF\r
-#define MSR_GOLDMONT_LASTBRANCH_16_TO_IP 0x000006D0\r
-#define MSR_GOLDMONT_LASTBRANCH_17_TO_IP 0x000006D1\r
-#define MSR_GOLDMONT_LASTBRANCH_18_TO_IP 0x000006D2\r
-#define MSR_GOLDMONT_LASTBRANCH_19_TO_IP 0x000006D3\r
-#define MSR_GOLDMONT_LASTBRANCH_20_TO_IP 0x000006D4\r
-#define MSR_GOLDMONT_LASTBRANCH_21_TO_IP 0x000006D5\r
-#define MSR_GOLDMONT_LASTBRANCH_22_TO_IP 0x000006D6\r
-#define MSR_GOLDMONT_LASTBRANCH_23_TO_IP 0x000006D7\r
-#define MSR_GOLDMONT_LASTBRANCH_24_TO_IP 0x000006D8\r
-#define MSR_GOLDMONT_LASTBRANCH_25_TO_IP 0x000006D9\r
-#define MSR_GOLDMONT_LASTBRANCH_26_TO_IP 0x000006DA\r
-#define MSR_GOLDMONT_LASTBRANCH_27_TO_IP 0x000006DB\r
-#define MSR_GOLDMONT_LASTBRANCH_28_TO_IP 0x000006DC\r
-#define MSR_GOLDMONT_LASTBRANCH_29_TO_IP 0x000006DD\r
-#define MSR_GOLDMONT_LASTBRANCH_30_TO_IP 0x000006DE\r
-#define MSR_GOLDMONT_LASTBRANCH_31_TO_IP 0x000006DF\r
+#define MSR_GOLDMONT_LASTBRANCH_0_TO_IP 0x000006C0\r
+#define MSR_GOLDMONT_LASTBRANCH_1_TO_IP 0x000006C1\r
+#define MSR_GOLDMONT_LASTBRANCH_2_TO_IP 0x000006C2\r
+#define MSR_GOLDMONT_LASTBRANCH_3_TO_IP 0x000006C3\r
+#define MSR_GOLDMONT_LASTBRANCH_4_TO_IP 0x000006C4\r
+#define MSR_GOLDMONT_LASTBRANCH_5_TO_IP 0x000006C5\r
+#define MSR_GOLDMONT_LASTBRANCH_6_TO_IP 0x000006C6\r
+#define MSR_GOLDMONT_LASTBRANCH_7_TO_IP 0x000006C7\r
+#define MSR_GOLDMONT_LASTBRANCH_8_TO_IP 0x000006C8\r
+#define MSR_GOLDMONT_LASTBRANCH_9_TO_IP 0x000006C9\r
+#define MSR_GOLDMONT_LASTBRANCH_10_TO_IP 0x000006CA\r
+#define MSR_GOLDMONT_LASTBRANCH_11_TO_IP 0x000006CB\r
+#define MSR_GOLDMONT_LASTBRANCH_12_TO_IP 0x000006CC\r
+#define MSR_GOLDMONT_LASTBRANCH_13_TO_IP 0x000006CD\r
+#define MSR_GOLDMONT_LASTBRANCH_14_TO_IP 0x000006CE\r
+#define MSR_GOLDMONT_LASTBRANCH_15_TO_IP 0x000006CF\r
+#define MSR_GOLDMONT_LASTBRANCH_16_TO_IP 0x000006D0\r
+#define MSR_GOLDMONT_LASTBRANCH_17_TO_IP 0x000006D1\r
+#define MSR_GOLDMONT_LASTBRANCH_18_TO_IP 0x000006D2\r
+#define MSR_GOLDMONT_LASTBRANCH_19_TO_IP 0x000006D3\r
+#define MSR_GOLDMONT_LASTBRANCH_20_TO_IP 0x000006D4\r
+#define MSR_GOLDMONT_LASTBRANCH_21_TO_IP 0x000006D5\r
+#define MSR_GOLDMONT_LASTBRANCH_22_TO_IP 0x000006D6\r
+#define MSR_GOLDMONT_LASTBRANCH_23_TO_IP 0x000006D7\r
+#define MSR_GOLDMONT_LASTBRANCH_24_TO_IP 0x000006D8\r
+#define MSR_GOLDMONT_LASTBRANCH_25_TO_IP 0x000006D9\r
+#define MSR_GOLDMONT_LASTBRANCH_26_TO_IP 0x000006DA\r
+#define MSR_GOLDMONT_LASTBRANCH_27_TO_IP 0x000006DB\r
+#define MSR_GOLDMONT_LASTBRANCH_28_TO_IP 0x000006DC\r
+#define MSR_GOLDMONT_LASTBRANCH_29_TO_IP 0x000006DD\r
+#define MSR_GOLDMONT_LASTBRANCH_30_TO_IP 0x000006DE\r
+#define MSR_GOLDMONT_LASTBRANCH_31_TO_IP 0x000006DF\r
/// @}\r
\r
/**\r
///\r
/// [Bit 31:0] Target Linear Address (R/W).\r
///\r
- UINT32 TargetLinearAddress:32;\r
+ UINT32 TargetLinearAddress : 32;\r
///\r
/// [Bit 47:32] Target Linear Address (R/W).\r
///\r
- UINT32 TargetLinearAddressHi:16;\r
+ UINT32 TargetLinearAddressHi : 16;\r
///\r
/// [Bits 63:48] Elapsed cycles from last update to the LBR.\r
///\r
- UINT32 ElapsedCycles:16;\r
+ UINT32 ElapsedCycles : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER;\r
\r
-\r
/**\r
Core. Resource Association Register (R/W).\r
\r
@endcode\r
@note MSR_GOLDMONT_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
**/\r
-#define MSR_GOLDMONT_IA32_PQR_ASSOC 0x00000C8F\r
+#define MSR_GOLDMONT_IA32_PQR_ASSOC 0x00000C8F\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_IA32_PQR_ASSOC\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
+ UINT32 Reserved1 : 32;\r
///\r
/// [Bits 33:32] COS (R/W).\r
///\r
- UINT32 COS:2;\r
- UINT32 Reserved2:30;\r
+ UINT32 COS : 2;\r
+ UINT32 Reserved2 : 30;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER;\r
\r
-\r
/**\r
Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,\r
ECX=1):EDX.COS_MAX[15:0] >=n.\r
MSR_GOLDMONT_IA32_L2_QOS_MASK_2 is defined as IA32_L2_QOS_MASK_2 in SDM.\r
@{\r
**/\r
-#define MSR_GOLDMONT_IA32_L2_QOS_MASK_0 0x00000D10\r
-#define MSR_GOLDMONT_IA32_L2_QOS_MASK_1 0x00000D11\r
-#define MSR_GOLDMONT_IA32_L2_QOS_MASK_2 0x00000D12\r
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_0 0x00000D10\r
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_1 0x00000D11\r
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_2 0x00000D12\r
/// @}\r
\r
/**\r
///\r
/// [Bits 7:0] CBM: Bit vector of available L2 ways for COS 0 enforcement\r
///\r
- UINT32 CBM:8;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
+ UINT32 CBM : 8;\r
+ UINT32 Reserved1 : 24;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER;\r
\r
-\r
/**\r
Package. L2 Class Of Service Mask - COS 3 (R/W) if CPUID.(EAX=10H,\r
ECX=1):EDX.COS_MAX[15:0] >=3.\r
@endcode\r
@note MSR_GOLDMONT_IA32_L2_QOS_MASK_3 is defined as IA32_L2_QOS_MASK_3 in SDM.\r
**/\r
-#define MSR_GOLDMONT_IA32_L2_QOS_MASK_3 0x00000D13\r
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_3 0x00000D13\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_IA32_L2_QOS_MASK_3.\r
///\r
/// [Bits 19:0] CBM: Bit vector of available L2 ways for COS 0 enforcement\r
///\r
- UINT32 CBM:20;\r
- UINT32 Reserved1:12;\r
- UINT32 Reserved2:32;\r
+ UINT32 CBM : 20;\r
+ UINT32 Reserved1 : 12;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER;\r
\r
-\r
#endif\r
projects / mirror_edk2.git / blobdiff