MdePkg: Apply uncrustify changes

[mirror_edk2.git] / MdePkg / Include / Register / Intel / Msr / HaswellEMsr.h

diff --git a/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h b/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h
index 6c8e29d2acf38fd2d64a02b7b9a4b4f2adef4078..2bcc20d3f2b1584ae6c62e29219e594c79d8ba81 100644 (file)
--- a/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h
+++ b/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h
@@ -60,7 +60,7 @@
   @endcode\r
   @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.\r
 **/\r
-#define MSR_HASWELL_E_CORE_THREAD_COUNT          0x00000035\r
+#define MSR_HASWELL_E_CORE_THREAD_COUNT  0x00000035\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT\r
@@ -75,26 +75,25 @@ typedef union {
     /// currently enabled (by either factory configuration or BIOS\r
     /// configuration) in the physical package.\r
     ///\r
-    UINT32  Core_Count:16;\r
+    UINT32    Core_Count   : 16;\r
     ///\r
     /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that\r
     /// are currently enabled (by either factory configuration or BIOS\r
     /// configuration) in the physical package.\r
     ///\r
-    UINT32  Thread_Count:16;\r
-    UINT32  Reserved:32;\r
+    UINT32    Thread_Count : 16;\r
+    UINT32    Reserved     : 32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
-  UINT32  Uint32;\r
+  UINT32    Uint32;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER;\r
 \r
-\r
 /**\r
   Thread. A Hardware Assigned ID for the Logical Processor (RO).\r
 \r
@@ -112,7 +111,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.\r
 **/\r
-#define MSR_HASWELL_E_THREAD_ID_INFO             0x00000053\r
+#define MSR_HASWELL_E_THREAD_ID_INFO  0x00000053\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO\r
@@ -128,21 +127,20 @@ typedef union {
     /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within\r
     /// a physical package.\r
     ///\r
-    UINT32  Logical_Processor_ID:8;\r
-    UINT32  Reserved1:24;\r
-    UINT32  Reserved2:32;\r
+    UINT32    Logical_Processor_ID : 8;\r
+    UINT32    Reserved1            : 24;\r
+    UINT32    Reserved2            : 32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
-  UINT32  Uint32;\r
+  UINT32    Uint32;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_THREAD_ID_INFO_REGISTER;\r
 \r
-\r
 /**\r
   Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
   specific C-state code names, unrelated to MWAIT extension C-state parameters\r
@@ -163,7 +161,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL     0x000000E2\r
+#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL  0x000000E2\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL\r
@@ -182,56 +180,55 @@ typedef union {
     /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
     /// supported by the processor are available.\r
     ///\r
-    UINT32  Limit:3;\r
-    UINT32  Reserved1:7;\r
+    UINT32    Limit            : 3;\r
+    UINT32    Reserved1        : 7;\r
     ///\r
     /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
     ///\r
-    UINT32  IO_MWAIT:1;\r
-    UINT32  Reserved2:4;\r
+    UINT32    IO_MWAIT         : 1;\r
+    UINT32    Reserved2        : 4;\r
     ///\r
     /// [Bit 15] CFG Lock (R/WO).\r
     ///\r
-    UINT32  CFGLock:1;\r
-    UINT32  Reserved3:9;\r
+    UINT32    CFGLock          : 1;\r
+    UINT32    Reserved3        : 9;\r
     ///\r
     /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
     ///\r
-    UINT32  C3AutoDemotion:1;\r
+    UINT32    C3AutoDemotion   : 1;\r
     ///\r
     /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
     ///\r
-    UINT32  C1AutoDemotion:1;\r
+    UINT32    C1AutoDemotion   : 1;\r
     ///\r
     /// [Bit 27] Enable C3 Undemotion (R/W).\r
     ///\r
-    UINT32  C3Undemotion:1;\r
+    UINT32    C3Undemotion     : 1;\r
     ///\r
     /// [Bit 28] Enable C1 Undemotion (R/W).\r
     ///\r
-    UINT32  C1Undemotion:1;\r
+    UINT32    C1Undemotion     : 1;\r
     ///\r
     /// [Bit 29] Package C State Demotion Enable (R/W).\r
     ///\r
-    UINT32  CStateDemotion:1;\r
+    UINT32    CStateDemotion   : 1;\r
     ///\r
     /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
     ///\r
-    UINT32  CStateUndemotion:1;\r
-    UINT32  Reserved4:1;\r
-    UINT32  Reserved5:32;\r
+    UINT32    CStateUndemotion : 1;\r
+    UINT32    Reserved4        : 1;\r
+    UINT32    Reserved5        : 32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
-  UINT32  Uint32;\r
+  UINT32    Uint32;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER;\r
 \r
-\r
 /**\r
   Thread. Global Machine Check Capability (R/O).\r
 \r
@@ -249,7 +246,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
 **/\r
-#define MSR_HASWELL_E_IA32_MCG_CAP               0x00000179\r
+#define MSR_HASWELL_E_IA32_MCG_CAP  0x00000179\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP\r
@@ -262,54 +259,53 @@ typedef union {
     ///\r
     /// [Bits 7:0] Count.\r
     ///\r
-    UINT32  Count:8;\r
+    UINT32    Count       : 8;\r
     ///\r
     /// [Bit 8] MCG_CTL_P.\r
     ///\r
-    UINT32  MCG_CTL_P:1;\r
+    UINT32    MCG_CTL_P   : 1;\r
     ///\r
     /// [Bit 9] MCG_EXT_P.\r
     ///\r
-    UINT32  MCG_EXT_P:1;\r
+    UINT32    MCG_EXT_P   : 1;\r
     ///\r
     /// [Bit 10] MCP_CMCI_P.\r
     ///\r
-    UINT32  MCP_CMCI_P:1;\r
+    UINT32    MCP_CMCI_P  : 1;\r
     ///\r
     /// [Bit 11] MCG_TES_P.\r
     ///\r
-    UINT32  MCG_TES_P:1;\r
-    UINT32  Reserved1:4;\r
+    UINT32    MCG_TES_P   : 1;\r
+    UINT32    Reserved1   : 4;\r
     ///\r
     /// [Bits 23:16] MCG_EXT_CNT.\r
     ///\r
-    UINT32  MCG_EXT_CNT:8;\r
+    UINT32    MCG_EXT_CNT : 8;\r
     ///\r
     /// [Bit 24] MCG_SER_P.\r
     ///\r
-    UINT32  MCG_SER_P:1;\r
+    UINT32    MCG_SER_P   : 1;\r
     ///\r
     /// [Bit 25] MCG_EM_P.\r
     ///\r
-    UINT32  MCG_EM_P:1;\r
+    UINT32    MCG_EM_P    : 1;\r
     ///\r
     /// [Bit 26] MCG_ELOG_P.\r
     ///\r
-    UINT32  MCG_ELOG_P:1;\r
-    UINT32  Reserved2:5;\r
-    UINT32  Reserved3:32;\r
+    UINT32    MCG_ELOG_P  : 1;\r
+    UINT32    Reserved2   : 5;\r
+    UINT32    Reserved3   : 32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
-  UINT32  Uint32;\r
+  UINT32    Uint32;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_IA32_MCG_CAP_REGISTER;\r
 \r
-\r
 /**\r
   THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
   Enhancement. Accessible only while in SMM.\r
@@ -329,7 +325,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
 **/\r
-#define MSR_HASWELL_E_SMM_MCA_CAP                0x0000017D\r
+#define MSR_HASWELL_E_SMM_MCA_CAP  0x0000017D\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP\r
@@ -339,29 +335,28 @@ typedef union {
   /// Individual bit fields\r
   ///\r
   struct {\r
-    UINT32  Reserved1:32;\r
-    UINT32  Reserved2:26;\r
+    UINT32    Reserved1            : 32;\r
+    UINT32    Reserved2            : 26;\r
     ///\r
     /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
     /// SMM code access restriction is supported and a host-space interface\r
     /// available to SMM handler.\r
     ///\r
-    UINT32  SMM_Code_Access_Chk:1;\r
+    UINT32    SMM_Code_Access_Chk  : 1;\r
     ///\r
     /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
     /// SMM long flow indicator is supported and a host-space interface\r
     /// available to SMM handler.\r
     ///\r
-    UINT32  Long_Flow_Indication:1;\r
-    UINT32  Reserved3:4;\r
+    UINT32    Long_Flow_Indication : 1;\r
+    UINT32    Reserved3            : 4;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_SMM_MCA_CAP_REGISTER;\r
 \r
-\r
 /**\r
   Package. MC Bank Error Configuration (R/W).\r
 \r
@@ -380,7 +375,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_ERROR_CONTROL              0x0000017F\r
+#define MSR_HASWELL_E_ERROR_CONTROL  0x0000017F\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL\r
@@ -390,26 +385,25 @@ typedef union {
   /// Individual bit fields\r
   ///\r
   struct {\r
-    UINT32  Reserved1:1;\r
+    UINT32    Reserved1         : 1;\r
     ///\r
     /// [Bit 1] MemError Log Enable (R/W)  When set, enables IMC status bank\r
     /// to log additional info in bits 36:32.\r
     ///\r
-    UINT32  MemErrorLogEnable:1;\r
-    UINT32  Reserved2:30;\r
-    UINT32  Reserved3:32;\r
+    UINT32    MemErrorLogEnable : 1;\r
+    UINT32    Reserved2         : 30;\r
+    UINT32    Reserved3         : 32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
-  UINT32  Uint32;\r
+  UINT32    Uint32;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_ERROR_CONTROL_REGISTER;\r
 \r
-\r
 /**\r
   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
   RW if MSR_PLATFORM_INFO.[28] = 1.\r
@@ -428,7 +422,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
 **/\r
-#define MSR_HASWELL_E_TURBO_RATIO_LIMIT          0x000001AD\r
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT  0x000001AD\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT\r
@@ -442,50 +436,49 @@ typedef union {
     /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
     /// limit of 1 core active.\r
     ///\r
-    UINT32  Maximum1C:8;\r
+    UINT32    Maximum1C : 8;\r
     ///\r
     /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
     /// limit of 2 core active.\r
     ///\r
-    UINT32  Maximum2C:8;\r
+    UINT32    Maximum2C : 8;\r
     ///\r
     /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
     /// limit of 3 core active.\r
     ///\r
-    UINT32  Maximum3C:8;\r
+    UINT32    Maximum3C : 8;\r
     ///\r
     /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
     /// limit of 4 core active.\r
     ///\r
-    UINT32  Maximum4C:8;\r
+    UINT32    Maximum4C : 8;\r
     ///\r
     /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
     /// limit of 5 core active.\r
     ///\r
-    UINT32  Maximum5C:8;\r
+    UINT32    Maximum5C : 8;\r
     ///\r
     /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
     /// limit of 6 core active.\r
     ///\r
-    UINT32  Maximum6C:8;\r
+    UINT32    Maximum6C : 8;\r
     ///\r
     /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
     /// limit of 7 core active.\r
     ///\r
-    UINT32  Maximum7C:8;\r
+    UINT32    Maximum7C : 8;\r
     ///\r
     /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
     /// limit of 8 core active.\r
     ///\r
-    UINT32  Maximum8C:8;\r
+    UINT32    Maximum8C : 8;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER;\r
 \r
-\r
 /**\r
   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
   RW if MSR_PLATFORM_INFO.[28] = 1.\r
@@ -504,7 +497,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1         0x000001AE\r
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1  0x000001AE\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1\r
@@ -518,50 +511,49 @@ typedef union {
     /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r
     /// limit of 9 core active.\r
     ///\r
-    UINT32  Maximum9C:8;\r
+    UINT32    Maximum9C  : 8;\r
     ///\r
     /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r
     /// limit of 10 core active.\r
     ///\r
-    UINT32  Maximum10C:8;\r
+    UINT32    Maximum10C : 8;\r
     ///\r
     /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r
     /// limit of 11 core active.\r
     ///\r
-    UINT32  Maximum11C:8;\r
+    UINT32    Maximum11C : 8;\r
     ///\r
     /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r
     /// limit of 12 core active.\r
     ///\r
-    UINT32  Maximum12C:8;\r
+    UINT32    Maximum12C : 8;\r
     ///\r
     /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r
     /// limit of 13 core active.\r
     ///\r
-    UINT32  Maximum13C:8;\r
+    UINT32    Maximum13C : 8;\r
     ///\r
     /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r
     /// limit of 14 core active.\r
     ///\r
-    UINT32  Maximum14C:8;\r
+    UINT32    Maximum14C : 8;\r
     ///\r
     /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r
     /// limit of 15 core active.\r
     ///\r
-    UINT32  Maximum15C:8;\r
+    UINT32    Maximum15C : 8;\r
     ///\r
     /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio\r
     /// limit of 16 core active.\r
     ///\r
-    UINT32  Maximum16C:8;\r
+    UINT32    Maximum16C : 8;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER;\r
 \r
-\r
 /**\r
   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
   RW if MSR_PLATFORM_INFO.[28] = 1.\r
@@ -580,7 +572,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2         0x000001AF\r
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2  0x000001AF\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2\r
@@ -594,14 +586,14 @@ typedef union {
     /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio\r
     /// limit of 17 core active.\r
     ///\r
-    UINT32  Maximum17C:8;\r
+    UINT32    Maximum17C                            : 8;\r
     ///\r
     /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio\r
     /// limit of 18 core active.\r
     ///\r
-    UINT32  Maximum18C:8;\r
-    UINT32  Reserved1:16;\r
-    UINT32  Reserved2:31;\r
+    UINT32    Maximum18C                            : 8;\r
+    UINT32    Reserved1                             : 16;\r
+    UINT32    Reserved2                             : 31;\r
     ///\r
     /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
     /// the processor uses override configuration specified in\r
@@ -609,15 +601,14 @@ typedef union {
     /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set\r
     /// configuration (Default).\r
     ///\r
-    UINT32  TurboRatioLimitConfigurationSemaphore:1;\r
+    UINT32    TurboRatioLimitConfigurationSemaphore : 1;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;\r
 \r
-\r
 /**\r
   Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
 \r
@@ -635,7 +626,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
 **/\r
-#define MSR_HASWELL_E_RAPL_POWER_UNIT            0x00000606\r
+#define MSR_HASWELL_E_RAPL_POWER_UNIT  0x00000606\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT\r
@@ -648,35 +639,34 @@ typedef union {
     ///\r
     /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
     ///\r
-    UINT32  PowerUnits:4;\r
-    UINT32  Reserved1:4;\r
+    UINT32    PowerUnits        : 4;\r
+    UINT32    Reserved1         : 4;\r
     ///\r
     /// [Bits 12:8] Package. Energy Status Units Energy related information\r
     /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
     /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
     /// micro-joules).\r
     ///\r
-    UINT32  EnergyStatusUnits:5;\r
-    UINT32  Reserved2:3;\r
+    UINT32    EnergyStatusUnits : 5;\r
+    UINT32    Reserved2         : 3;\r
     ///\r
     /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
     /// Interfaces.".\r
     ///\r
-    UINT32  TimeUnits:4;\r
-    UINT32  Reserved3:12;\r
-    UINT32  Reserved4:32;\r
+    UINT32    TimeUnits         : 4;\r
+    UINT32    Reserved3         : 12;\r
+    UINT32    Reserved4         : 32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
-  UINT32  Uint32;\r
+  UINT32    Uint32;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER;\r
 \r
-\r
 /**\r
   Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL\r
   Domain.".\r
@@ -694,8 +684,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
 **/\r
-#define MSR_HASWELL_E_DRAM_POWER_LIMIT           0x00000618\r
-\r
+#define MSR_HASWELL_E_DRAM_POWER_LIMIT  0x00000618\r
 \r
 /**\r
   Package. DRAM Energy Status (R/O)  Energy Consumed by DRAM devices.\r
@@ -714,7 +703,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_DRAM_ENERGY_STATUS         0x00000619\r
+#define MSR_HASWELL_E_DRAM_ENERGY_STATUS  0x00000619\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS\r
@@ -728,20 +717,19 @@ typedef union {
     /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
     /// to enable DRAM RAPL mode 0 (Direct VR).\r
     ///\r
-    UINT32  Energy:32;\r
-    UINT32  Reserved:32;\r
+    UINT32    Energy   : 32;\r
+    UINT32    Reserved : 32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
-  UINT32  Uint32;\r
+  UINT32    Uint32;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER;\r
 \r
-\r
 /**\r
   Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
   RAPL Domain.".\r
@@ -758,8 +746,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_DRAM_PERF_STATUS           0x0000061B\r
-\r
+#define MSR_HASWELL_E_DRAM_PERF_STATUS  0x0000061B\r
 \r
 /**\r
   Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
@@ -777,8 +764,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
 **/\r
-#define MSR_HASWELL_E_DRAM_POWER_INFO            0x0000061C\r
-\r
+#define MSR_HASWELL_E_DRAM_POWER_INFO  0x0000061C\r
 \r
 /**\r
   Package. Configuration of PCIE PLL Relative to BCLK(R/W).\r
@@ -798,7 +784,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PCIE_PLL_RATIO             0x0000061E\r
+#define MSR_HASWELL_E_PCIE_PLL_RATIO  0x0000061E\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO\r
@@ -814,31 +800,30 @@ typedef union {
     /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz\r
     /// operation.\r
     ///\r
-    UINT32  PCIERatio:2;\r
+    UINT32    PCIERatio  : 2;\r
     ///\r
     /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of\r
     /// PCIE Ratio.\r
     ///\r
-    UINT32  LPLLSelect:1;\r
+    UINT32    LPLLSelect : 1;\r
     ///\r
     /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out\r
     /// before re-locking Gen2/Gen3 PLLs.\r
     ///\r
-    UINT32  LONGRESET:1;\r
-    UINT32  Reserved1:28;\r
-    UINT32  Reserved2:32;\r
+    UINT32    LONGRESET  : 1;\r
+    UINT32    Reserved1  : 28;\r
+    UINT32    Reserved2  : 32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
-  UINT32  Uint32;\r
+  UINT32    Uint32;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER;\r
 \r
-\r
 /**\r
   Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
   fields represent the widest possible range of uncore frequencies. Writing to\r
@@ -859,7 +844,7 @@ typedef union {
   AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
   @endcode\r
 **/\r
-#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT      0x00000620\r
+#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT  0x00000620\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT\r
@@ -873,24 +858,24 @@ typedef union {
     /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
     /// LLC/Ring.\r
     ///\r
-    UINT32  MAX_RATIO:7;\r
-    UINT32  Reserved1:1;\r
+    UINT32    MAX_RATIO : 7;\r
+    UINT32    Reserved1 : 1;\r
     ///\r
     /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
     /// possible ratio of the LLC/Ring.\r
     ///\r
-    UINT32  MIN_RATIO:7;\r
-    UINT32  Reserved2:17;\r
-    UINT32  Reserved3:32;\r
+    UINT32    MIN_RATIO : 7;\r
+    UINT32    Reserved2 : 17;\r
+    UINT32    Reserved3 : 32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
-  UINT32  Uint32;\r
+  UINT32    Uint32;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
 \r
 /**\r
@@ -908,8 +893,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PP0_ENERGY_STATUS          0x00000639\r
-\r
+#define MSR_HASWELL_E_PP0_ENERGY_STATUS  0x00000639\r
 \r
 /**\r
   Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
@@ -930,7 +914,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS    0x00000690\r
+#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS  0x00000690\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS\r
@@ -945,152 +929,151 @@ typedef union {
     /// reduced below the operating system request due to assertion of\r
     /// external PROCHOT.\r
     ///\r
-    UINT32  PROCHOT_Status:1;\r
+    UINT32    PROCHOT_Status                                   : 1;\r
     ///\r
     /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
     /// operating system request due to a thermal event.\r
     ///\r
-    UINT32  ThermalStatus:1;\r
+    UINT32    ThermalStatus                                    : 1;\r
     ///\r
     /// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r
     /// reduced below the operating system request due to PBM limit.\r
     ///\r
-    UINT32  PowerBudgetManagementStatus:1;\r
+    UINT32    PowerBudgetManagementStatus                      : 1;\r
     ///\r
     /// [Bit 3] Platform Configuration Services Status (R0) When set,\r
     /// frequency is reduced below the operating system request due to PCS\r
     /// limit.\r
     ///\r
-    UINT32  PlatformConfigurationServicesStatus:1;\r
-    UINT32  Reserved1:1;\r
+    UINT32    PlatformConfigurationServicesStatus              : 1;\r
+    UINT32    Reserved1                                        : 1;\r
     ///\r
     /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
     /// When set, frequency is reduced below the operating system request\r
     /// because the processor has detected that utilization is low.\r
     ///\r
-    UINT32  AutonomousUtilizationBasedFrequencyControlStatus:1;\r
+    UINT32    AutonomousUtilizationBasedFrequencyControlStatus : 1;\r
     ///\r
     /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
     /// below the operating system request due to a thermal alert from the\r
     /// Voltage Regulator.\r
     ///\r
-    UINT32  VRThermAlertStatus:1;\r
-    UINT32  Reserved2:1;\r
+    UINT32    VRThermAlertStatus                               : 1;\r
+    UINT32    Reserved2                                        : 1;\r
     ///\r
     /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
     /// reduced below the operating system request due to electrical design\r
     /// point constraints (e.g. maximum electrical current consumption).\r
     ///\r
-    UINT32  ElectricalDesignPointStatus:1;\r
-    UINT32  Reserved3:1;\r
+    UINT32    ElectricalDesignPointStatus                      : 1;\r
+    UINT32    Reserved3                                        : 1;\r
     ///\r
     /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r
     /// below the operating system request due to Multi-Core Turbo limits.\r
     ///\r
-    UINT32  MultiCoreTurboStatus:1;\r
-    UINT32  Reserved4:2;\r
+    UINT32    MultiCoreTurboStatus                             : 1;\r
+    UINT32    Reserved4                                        : 2;\r
     ///\r
     /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r
     /// below max non-turbo P1.\r
     ///\r
-    UINT32  FrequencyP1Status:1;\r
+    UINT32    FrequencyP1Status                                : 1;\r
     ///\r
     /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r
     /// set, frequency is reduced below max n-core turbo frequency.\r
     ///\r
-    UINT32  TurboFrequencyLimitingStatus:1;\r
+    UINT32    TurboFrequencyLimitingStatus                     : 1;\r
     ///\r
     /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r
     /// reduced below the operating system request.\r
     ///\r
-    UINT32  FrequencyLimitingStatus:1;\r
+    UINT32    FrequencyLimitingStatus                          : 1;\r
     ///\r
     /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit\r
     /// has asserted since the log bit was last cleared. This log bit will\r
     /// remain set until cleared by software writing 0.\r
     ///\r
-    UINT32  PROCHOT_Log:1;\r
+    UINT32    PROCHOT_Log                                      : 1;\r
     ///\r
     /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit\r
     /// has asserted since the log bit was last cleared. This log bit will\r
     /// remain set until cleared by software writing 0.\r
     ///\r
-    UINT32  ThermalLog:1;\r
+    UINT32    ThermalLog                                       : 1;\r
     ///\r
     /// [Bit 18] Power Budget Management Log  When set, indicates that the PBM\r
     /// Status bit has asserted since the log bit was last cleared. This log\r
     /// bit will remain set until cleared by software writing 0.\r
     ///\r
-    UINT32  PowerBudgetManagementLog:1;\r
+    UINT32    PowerBudgetManagementLog                         : 1;\r
     ///\r
     /// [Bit 19] Platform Configuration Services Log  When set, indicates that\r
     /// the PCS Status bit has asserted since the log bit was last cleared.\r
     /// This log bit will remain set until cleared by software writing 0.\r
     ///\r
-    UINT32  PlatformConfigurationServicesLog:1;\r
-    UINT32  Reserved5:1;\r
+    UINT32    PlatformConfigurationServicesLog                 : 1;\r
+    UINT32    Reserved5                                        : 1;\r
     ///\r
     /// [Bit 21] Autonomous Utilization-Based Frequency Control Log  When set,\r
     /// indicates that the AUBFC Status bit has asserted since the log bit was\r
     /// last cleared. This log bit will remain set until cleared by software\r
     /// writing 0.\r
     ///\r
-    UINT32  AutonomousUtilizationBasedFrequencyControlLog:1;\r
+    UINT32    AutonomousUtilizationBasedFrequencyControlLog    : 1;\r
     ///\r
     /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm\r
     /// Alert Status bit has asserted since the log bit was last cleared. This\r
     /// log bit will remain set until cleared by software writing 0.\r
     ///\r
-    UINT32  VRThermAlertLog:1;\r
-    UINT32  Reserved6:1;\r
+    UINT32    VRThermAlertLog                                  : 1;\r
+    UINT32    Reserved6                                        : 1;\r
     ///\r
     /// [Bit 24] Electrical Design Point Log  When set, indicates that the EDP\r
     /// Status bit has asserted since the log bit was last cleared. This log\r
     /// bit will remain set until cleared by software writing 0.\r
     ///\r
-    UINT32  ElectricalDesignPointLog:1;\r
-    UINT32  Reserved7:1;\r
+    UINT32    ElectricalDesignPointLog                         : 1;\r
+    UINT32    Reserved7                                        : 1;\r
     ///\r
     /// [Bit 26] Multi-Core Turbo Log  When set, indicates that the Multi-Core\r
     /// Turbo Status bit has asserted since the log bit was last cleared. This\r
     /// log bit will remain set until cleared by software writing 0.\r
     ///\r
-    UINT32  MultiCoreTurboLog:1;\r
-    UINT32  Reserved8:2;\r
+    UINT32    MultiCoreTurboLog                                : 1;\r
+    UINT32    Reserved8                                        : 2;\r
     ///\r
     /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r
     /// Frequency P1 Status bit has asserted since the log bit was last\r
     /// cleared. This log bit will remain set until cleared by software\r
     /// writing 0.\r
     ///\r
-    UINT32  CoreFrequencyP1Log:1;\r
+    UINT32    CoreFrequencyP1Log                               : 1;\r
     ///\r
     /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r
     /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r
     /// has asserted since the log bit was last cleared. This log bit will\r
     /// remain set until cleared by software writing 0.\r
     ///\r
-    UINT32  TurboFrequencyLimitingLog:1;\r
+    UINT32    TurboFrequencyLimitingLog                        : 1;\r
     ///\r
     /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r
     /// Frequency Limiting Status bit has asserted since the log bit was last\r
     /// cleared. This log bit will remain set until cleared by software\r
     /// writing 0.\r
     ///\r
-    UINT32  CoreFrequencyLimitingLog:1;\r
-    UINT32  Reserved9:32;\r
+    UINT32    CoreFrequencyLimitingLog                         : 1;\r
+    UINT32    Reserved9                                        : 32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
-  UINT32  Uint32;\r
+  UINT32    Uint32;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER;\r
 \r
-\r
 /**\r
   THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,\r
   ECX=0):EBX.RDT-M[bit 12] = 1.\r
@@ -1110,7 +1093,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_IA32_QM_EVTSEL             0x00000C8D\r
+#define MSR_HASWELL_E_IA32_QM_EVTSEL  0x00000C8D\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL\r
@@ -1124,21 +1107,20 @@ typedef union {
     /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3\r
     /// occupancy monitoring all other encoding reserved..\r
     ///\r
-    UINT32  EventID:8;\r
-    UINT32  Reserved1:24;\r
+    UINT32    EventID   : 8;\r
+    UINT32    Reserved1 : 24;\r
     ///\r
     /// [Bits 41:32] RMID (RW).\r
     ///\r
-    UINT32  RMID:10;\r
-    UINT32  Reserved2:22;\r
+    UINT32    RMID      : 10;\r
+    UINT32    Reserved2 : 22;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER;\r
 \r
-\r
 /**\r
   THREAD. Resource Association Register (R/W)..\r
 \r
@@ -1157,7 +1139,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
 **/\r
-#define MSR_HASWELL_E_IA32_PQR_ASSOC             0x00000C8F\r
+#define MSR_HASWELL_E_IA32_PQR_ASSOC  0x00000C8F\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC\r
@@ -1170,21 +1152,20 @@ typedef union {
     ///\r
     /// [Bits 9:0] RMID.\r
     ///\r
-    UINT32  RMID:10;\r
-    UINT32  Reserved1:22;\r
-    UINT32  Reserved2:32;\r
+    UINT32    RMID      : 10;\r
+    UINT32    Reserved1 : 22;\r
+    UINT32    Reserved2 : 32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
-  UINT32  Uint32;\r
+  UINT32    Uint32;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER;\r
 \r
-\r
 /**\r
   Package. Uncore perfmon per-socket global control.\r
 \r
@@ -1201,8 +1182,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PMON_GLOBAL_CTL            0x00000700\r
-\r
+#define MSR_HASWELL_E_PMON_GLOBAL_CTL  0x00000700\r
 \r
 /**\r
   Package. Uncore perfmon per-socket global status.\r
@@ -1220,8 +1200,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PMON_GLOBAL_STATUS         0x00000701\r
-\r
+#define MSR_HASWELL_E_PMON_GLOBAL_STATUS  0x00000701\r
 \r
 /**\r
   Package. Uncore perfmon per-socket global configuration.\r
@@ -1239,8 +1218,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG         0x00000702\r
-\r
+#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG  0x00000702\r
 \r
 /**\r
   Package. Uncore U-box UCLK fixed counter control.\r
@@ -1258,8 +1236,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL      0x00000703\r
-\r
+#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL  0x00000703\r
 \r
 /**\r
   Package. Uncore U-box UCLK fixed counter.\r
@@ -1277,8 +1254,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.\r
 **/\r
-#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR      0x00000704\r
-\r
+#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR  0x00000704\r
 \r
 /**\r
   Package. Uncore U-box perfmon event select for U-box counter 0.\r
@@ -1296,8 +1272,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_U_PMON_EVNTSEL0            0x00000705\r
-\r
+#define MSR_HASWELL_E_U_PMON_EVNTSEL0  0x00000705\r
 \r
 /**\r
   Package. Uncore U-box perfmon event select for U-box counter 1.\r
@@ -1315,8 +1290,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_U_PMON_EVNTSEL1            0x00000706\r
-\r
+#define MSR_HASWELL_E_U_PMON_EVNTSEL1  0x00000706\r
 \r
 /**\r
   Package. Uncore U-box perfmon U-box wide status.\r
@@ -1334,8 +1308,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_U_PMON_BOX_STATUS          0x00000708\r
-\r
+#define MSR_HASWELL_E_U_PMON_BOX_STATUS  0x00000708\r
 \r
 /**\r
   Package. Uncore U-box perfmon counter 0.\r
@@ -1353,8 +1326,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_U_PMON_CTR0                0x00000709\r
-\r
+#define MSR_HASWELL_E_U_PMON_CTR0  0x00000709\r
 \r
 /**\r
   Package. Uncore U-box perfmon counter 1.\r
@@ -1372,8 +1344,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_U_PMON_CTR1                0x0000070A\r
-\r
+#define MSR_HASWELL_E_U_PMON_CTR1  0x0000070A\r
 \r
 /**\r
   Package. Uncore PCU perfmon for PCU-box-wide control.\r
@@ -1391,8 +1362,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PCU_PMON_BOX_CTL           0x00000710\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_BOX_CTL  0x00000710\r
 \r
 /**\r
   Package. Uncore PCU perfmon event select for PCU counter 0.\r
@@ -1410,8 +1380,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0          0x00000711\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0  0x00000711\r
 \r
 /**\r
   Package. Uncore PCU perfmon event select for PCU counter 1.\r
@@ -1429,8 +1398,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1          0x00000712\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1  0x00000712\r
 \r
 /**\r
   Package. Uncore PCU perfmon event select for PCU counter 2.\r
@@ -1448,8 +1416,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2          0x00000713\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2  0x00000713\r
 \r
 /**\r
   Package. Uncore PCU perfmon event select for PCU counter 3.\r
@@ -1467,8 +1434,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3          0x00000714\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3  0x00000714\r
 \r
 /**\r
   Package. Uncore PCU perfmon box-wide filter.\r
@@ -1486,8 +1452,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER        0x00000715\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER  0x00000715\r
 \r
 /**\r
   Package. Uncore PCU perfmon box wide status.\r
@@ -1505,8 +1470,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS        0x00000716\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS  0x00000716\r
 \r
 /**\r
   Package. Uncore PCU perfmon counter 0.\r
@@ -1524,8 +1488,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PCU_PMON_CTR0              0x00000717\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_CTR0  0x00000717\r
 \r
 /**\r
   Package. Uncore PCU perfmon counter 1.\r
@@ -1543,8 +1506,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PCU_PMON_CTR1              0x00000718\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_CTR1  0x00000718\r
 \r
 /**\r
   Package. Uncore PCU perfmon counter 2.\r
@@ -1562,8 +1524,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PCU_PMON_CTR2              0x00000719\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_CTR2  0x00000719\r
 \r
 /**\r
   Package. Uncore PCU perfmon counter 3.\r
@@ -1581,8 +1542,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_PCU_PMON_CTR3              0x0000071A\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_CTR3  0x0000071A\r
 \r
 /**\r
   Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.\r
@@ -1600,8 +1560,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S0_PMON_BOX_CTL            0x00000720\r
-\r
+#define MSR_HASWELL_E_S0_PMON_BOX_CTL  0x00000720\r
 \r
 /**\r
   Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.\r
@@ -1619,8 +1578,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL0           0x00000721\r
-\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL0  0x00000721\r
 \r
 /**\r
   Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.\r
@@ -1638,8 +1596,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL1           0x00000722\r
-\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL1  0x00000722\r
 \r
 /**\r
   Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.\r
@@ -1657,8 +1614,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL2           0x00000723\r
-\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL2  0x00000723\r
 \r
 /**\r
   Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.\r
@@ -1676,8 +1632,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL3           0x00000724\r
-\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL3  0x00000724\r
 \r
 /**\r
   Package. Uncore SBo 0 perfmon box-wide filter.\r
@@ -1695,8 +1650,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S0_PMON_BOX_FILTER         0x00000725\r
-\r
+#define MSR_HASWELL_E_S0_PMON_BOX_FILTER  0x00000725\r
 \r
 /**\r
   Package. Uncore SBo 0 perfmon counter 0.\r
@@ -1714,8 +1668,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S0_PMON_CTR0               0x00000726\r
-\r
+#define MSR_HASWELL_E_S0_PMON_CTR0  0x00000726\r
 \r
 /**\r
   Package. Uncore SBo 0 perfmon counter 1.\r
@@ -1733,8 +1686,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S0_PMON_CTR1               0x00000727\r
-\r
+#define MSR_HASWELL_E_S0_PMON_CTR1  0x00000727\r
 \r
 /**\r
   Package. Uncore SBo 0 perfmon counter 2.\r
@@ -1752,8 +1704,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S0_PMON_CTR2               0x00000728\r
-\r
+#define MSR_HASWELL_E_S0_PMON_CTR2  0x00000728\r
 \r
 /**\r
   Package. Uncore SBo 0 perfmon counter 3.\r
@@ -1771,8 +1722,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S0_PMON_CTR3               0x00000729\r
-\r
+#define MSR_HASWELL_E_S0_PMON_CTR3  0x00000729\r
 \r
 /**\r
   Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.\r
@@ -1790,8 +1740,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S1_PMON_BOX_CTL            0x0000072A\r
-\r
+#define MSR_HASWELL_E_S1_PMON_BOX_CTL  0x0000072A\r
 \r
 /**\r
   Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.\r
@@ -1809,8 +1758,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL0           0x0000072B\r
-\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL0  0x0000072B\r
 \r
 /**\r
   Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.\r
@@ -1828,8 +1776,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL1           0x0000072C\r
-\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL1  0x0000072C\r
 \r
 /**\r
   Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.\r
@@ -1847,8 +1794,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL2           0x0000072D\r
-\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL2  0x0000072D\r
 \r
 /**\r
   Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.\r
@@ -1866,8 +1812,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL3           0x0000072E\r
-\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL3  0x0000072E\r
 \r
 /**\r
   Package. Uncore SBo 1 perfmon box-wide filter.\r
@@ -1885,8 +1830,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S1_PMON_BOX_FILTER         0x0000072F\r
-\r
+#define MSR_HASWELL_E_S1_PMON_BOX_FILTER  0x0000072F\r
 \r
 /**\r
   Package. Uncore SBo 1 perfmon counter 0.\r
@@ -1904,8 +1848,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S1_PMON_CTR0               0x00000730\r
-\r
+#define MSR_HASWELL_E_S1_PMON_CTR0  0x00000730\r
 \r
 /**\r
   Package. Uncore SBo 1 perfmon counter 1.\r
@@ -1923,8 +1866,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S1_PMON_CTR1               0x00000731\r
-\r
+#define MSR_HASWELL_E_S1_PMON_CTR1  0x00000731\r
 \r
 /**\r
   Package. Uncore SBo 1 perfmon counter 2.\r
@@ -1942,8 +1884,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S1_PMON_CTR2               0x00000732\r
-\r
+#define MSR_HASWELL_E_S1_PMON_CTR2  0x00000732\r
 \r
 /**\r
   Package. Uncore SBo 1 perfmon counter 3.\r
@@ -1961,8 +1902,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S1_PMON_CTR3               0x00000733\r
-\r
+#define MSR_HASWELL_E_S1_PMON_CTR3  0x00000733\r
 \r
 /**\r
   Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.\r
@@ -1980,8 +1920,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S2_PMON_BOX_CTL            0x00000734\r
-\r
+#define MSR_HASWELL_E_S2_PMON_BOX_CTL  0x00000734\r
 \r
 /**\r
   Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.\r
@@ -1999,8 +1938,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL0           0x00000735\r
-\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL0  0x00000735\r
 \r
 /**\r
   Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.\r
@@ -2018,8 +1956,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL1           0x00000736\r
-\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL1  0x00000736\r
 \r
 /**\r
   Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.\r
@@ -2037,8 +1974,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL2           0x00000737\r
-\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL2  0x00000737\r
 \r
 /**\r
   Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.\r
@@ -2056,8 +1992,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL3           0x00000738\r
-\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL3  0x00000738\r
 \r
 /**\r
   Package. Uncore SBo 2 perfmon box-wide filter.\r
@@ -2075,8 +2010,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S2_PMON_BOX_FILTER         0x00000739\r
-\r
+#define MSR_HASWELL_E_S2_PMON_BOX_FILTER  0x00000739\r
 \r
 /**\r
   Package. Uncore SBo 2 perfmon counter 0.\r
@@ -2094,8 +2028,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S2_PMON_CTR0               0x0000073A\r
-\r
+#define MSR_HASWELL_E_S2_PMON_CTR0  0x0000073A\r
 \r
 /**\r
   Package. Uncore SBo 2 perfmon counter 1.\r
@@ -2113,8 +2046,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S2_PMON_CTR1               0x0000073B\r
-\r
+#define MSR_HASWELL_E_S2_PMON_CTR1  0x0000073B\r
 \r
 /**\r
   Package. Uncore SBo 2 perfmon counter 2.\r
@@ -2132,8 +2064,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S2_PMON_CTR2               0x0000073C\r
-\r
+#define MSR_HASWELL_E_S2_PMON_CTR2  0x0000073C\r
 \r
 /**\r
   Package. Uncore SBo 2 perfmon counter 3.\r
@@ -2151,8 +2082,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S2_PMON_CTR3               0x0000073D\r
-\r
+#define MSR_HASWELL_E_S2_PMON_CTR3  0x0000073D\r
 \r
 /**\r
   Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.\r
@@ -2170,8 +2100,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S3_PMON_BOX_CTL            0x0000073E\r
-\r
+#define MSR_HASWELL_E_S3_PMON_BOX_CTL  0x0000073E\r
 \r
 /**\r
   Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.\r
@@ -2189,8 +2118,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL0           0x0000073F\r
-\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL0  0x0000073F\r
 \r
 /**\r
   Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.\r
@@ -2208,8 +2136,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL1           0x00000740\r
-\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL1  0x00000740\r
 \r
 /**\r
   Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.\r
@@ -2227,8 +2154,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL2           0x00000741\r
-\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL2  0x00000741\r
 \r
 /**\r
   Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.\r
@@ -2246,8 +2172,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL3           0x00000742\r
-\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL3  0x00000742\r
 \r
 /**\r
   Package. Uncore SBo 3 perfmon box-wide filter.\r
@@ -2265,8 +2190,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S3_PMON_BOX_FILTER         0x00000743\r
-\r
+#define MSR_HASWELL_E_S3_PMON_BOX_FILTER  0x00000743\r
 \r
 /**\r
   Package. Uncore SBo 3 perfmon counter 0.\r
@@ -2284,8 +2208,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S3_PMON_CTR0               0x00000744\r
-\r
+#define MSR_HASWELL_E_S3_PMON_CTR0  0x00000744\r
 \r
 /**\r
   Package. Uncore SBo 3 perfmon counter 1.\r
@@ -2303,8 +2226,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S3_PMON_CTR1               0x00000745\r
-\r
+#define MSR_HASWELL_E_S3_PMON_CTR1  0x00000745\r
 \r
 /**\r
   Package. Uncore SBo 3 perfmon counter 2.\r
@@ -2322,8 +2244,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S3_PMON_CTR2               0x00000746\r
-\r
+#define MSR_HASWELL_E_S3_PMON_CTR2  0x00000746\r
 \r
 /**\r
   Package. Uncore SBo 3 perfmon counter 3.\r
@@ -2341,8 +2262,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_S3_PMON_CTR3               0x00000747\r
-\r
+#define MSR_HASWELL_E_S3_PMON_CTR3  0x00000747\r
 \r
 /**\r
   Package. Uncore C-box 0 perfmon for box-wide control.\r
@@ -2360,8 +2280,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C0_PMON_BOX_CTL            0x00000E00\r
-\r
+#define MSR_HASWELL_E_C0_PMON_BOX_CTL  0x00000E00\r
 \r
 /**\r
   Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.\r
@@ -2379,8 +2298,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL0           0x00000E01\r
-\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL0  0x00000E01\r
 \r
 /**\r
   Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.\r
@@ -2398,8 +2316,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL1           0x00000E02\r
-\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL1  0x00000E02\r
 \r
 /**\r
   Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.\r
@@ -2417,8 +2334,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL2           0x00000E03\r
-\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL2  0x00000E03\r
 \r
 /**\r
   Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.\r
@@ -2436,8 +2352,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL3           0x00000E04\r
-\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL3  0x00000E04\r
 \r
 /**\r
   Package. Uncore C-box 0 perfmon box wide filter 0.\r
@@ -2455,8 +2370,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0        0x00000E05\r
-\r
+#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0  0x00000E05\r
 \r
 /**\r
   Package. Uncore C-box 0 perfmon box wide filter 1.\r
@@ -2474,8 +2388,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1        0x00000E06\r
-\r
+#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1  0x00000E06\r
 \r
 /**\r
   Package. Uncore C-box 0 perfmon box wide status.\r
@@ -2493,8 +2406,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C0_PMON_BOX_STATUS         0x00000E07\r
-\r
+#define MSR_HASWELL_E_C0_PMON_BOX_STATUS  0x00000E07\r
 \r
 /**\r
   Package. Uncore C-box 0 perfmon counter 0.\r
@@ -2512,8 +2424,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C0_PMON_CTR0               0x00000E08\r
-\r
+#define MSR_HASWELL_E_C0_PMON_CTR0  0x00000E08\r
 \r
 /**\r
   Package. Uncore C-box 0 perfmon counter 1.\r
@@ -2531,8 +2442,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C0_PMON_CTR1               0x00000E09\r
-\r
+#define MSR_HASWELL_E_C0_PMON_CTR1  0x00000E09\r
 \r
 /**\r
   Package. Uncore C-box 0 perfmon counter 2.\r
@@ -2550,8 +2460,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C0_PMON_CTR2               0x00000E0A\r
-\r
+#define MSR_HASWELL_E_C0_PMON_CTR2  0x00000E0A\r
 \r
 /**\r
   Package. Uncore C-box 0 perfmon counter 3.\r
@@ -2569,8 +2478,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C0_PMON_CTR3               0x00000E0B\r
-\r
+#define MSR_HASWELL_E_C0_PMON_CTR3  0x00000E0B\r
 \r
 /**\r
   Package. Uncore C-box 1 perfmon for box-wide control.\r
@@ -2588,8 +2496,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C1_PMON_BOX_CTL            0x00000E10\r
-\r
+#define MSR_HASWELL_E_C1_PMON_BOX_CTL  0x00000E10\r
 \r
 /**\r
   Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.\r
@@ -2607,8 +2514,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL0           0x00000E11\r
-\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL0  0x00000E11\r
 \r
 /**\r
   Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.\r
@@ -2626,8 +2532,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL1           0x00000E12\r
-\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL1  0x00000E12\r
 \r
 /**\r
   Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.\r
@@ -2645,8 +2550,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL2           0x00000E13\r
-\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL2  0x00000E13\r
 \r
 /**\r
   Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.\r
@@ -2664,8 +2568,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL3           0x00000E14\r
-\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL3  0x00000E14\r
 \r
 /**\r
   Package. Uncore C-box 1 perfmon box wide filter 0.\r
@@ -2683,8 +2586,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0        0x00000E15\r
-\r
+#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0  0x00000E15\r
 \r
 /**\r
   Package. Uncore C-box 1 perfmon box wide filter1.\r
@@ -2702,8 +2604,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1        0x00000E16\r
-\r
+#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1  0x00000E16\r
 \r
 /**\r
   Package. Uncore C-box 1 perfmon box wide status.\r
@@ -2721,8 +2622,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C1_PMON_BOX_STATUS         0x00000E17\r
-\r
+#define MSR_HASWELL_E_C1_PMON_BOX_STATUS  0x00000E17\r
 \r
 /**\r
   Package. Uncore C-box 1 perfmon counter 0.\r
@@ -2740,8 +2640,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C1_PMON_CTR0               0x00000E18\r
-\r
+#define MSR_HASWELL_E_C1_PMON_CTR0  0x00000E18\r
 \r
 /**\r
   Package. Uncore C-box 1 perfmon counter 1.\r
@@ -2759,8 +2658,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C1_PMON_CTR1               0x00000E19\r
-\r
+#define MSR_HASWELL_E_C1_PMON_CTR1  0x00000E19\r
 \r
 /**\r
   Package. Uncore C-box 1 perfmon counter 2.\r
@@ -2778,8 +2676,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C1_PMON_CTR2               0x00000E1A\r
-\r
+#define MSR_HASWELL_E_C1_PMON_CTR2  0x00000E1A\r
 \r
 /**\r
   Package. Uncore C-box 1 perfmon counter 3.\r
@@ -2797,8 +2694,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C1_PMON_CTR3               0x00000E1B\r
-\r
+#define MSR_HASWELL_E_C1_PMON_CTR3  0x00000E1B\r
 \r
 /**\r
   Package. Uncore C-box 2 perfmon for box-wide control.\r
@@ -2816,8 +2712,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C2_PMON_BOX_CTL            0x00000E20\r
-\r
+#define MSR_HASWELL_E_C2_PMON_BOX_CTL  0x00000E20\r
 \r
 /**\r
   Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.\r
@@ -2835,8 +2730,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL0           0x00000E21\r
-\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL0  0x00000E21\r
 \r
 /**\r
   Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.\r
@@ -2854,8 +2748,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL1           0x00000E22\r
-\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL1  0x00000E22\r
 \r
 /**\r
   Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.\r
@@ -2873,8 +2766,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL2           0x00000E23\r
-\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL2  0x00000E23\r
 \r
 /**\r
   Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.\r
@@ -2892,8 +2784,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL3           0x00000E24\r
-\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL3  0x00000E24\r
 \r
 /**\r
   Package. Uncore C-box 2 perfmon box wide filter 0.\r
@@ -2911,8 +2802,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0        0x00000E25\r
-\r
+#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0  0x00000E25\r
 \r
 /**\r
   Package. Uncore C-box 2 perfmon box wide filter1.\r
@@ -2930,8 +2820,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1        0x00000E26\r
-\r
+#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1  0x00000E26\r
 \r
 /**\r
   Package. Uncore C-box 2 perfmon box wide status.\r
@@ -2949,8 +2838,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C2_PMON_BOX_STATUS         0x00000E27\r
-\r
+#define MSR_HASWELL_E_C2_PMON_BOX_STATUS  0x00000E27\r
 \r
 /**\r
   Package. Uncore C-box 2 perfmon counter 0.\r
@@ -2968,8 +2856,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C2_PMON_CTR0               0x00000E28\r
-\r
+#define MSR_HASWELL_E_C2_PMON_CTR0  0x00000E28\r
 \r
 /**\r
   Package. Uncore C-box 2 perfmon counter 1.\r
@@ -2987,8 +2874,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C2_PMON_CTR1               0x00000E29\r
-\r
+#define MSR_HASWELL_E_C2_PMON_CTR1  0x00000E29\r
 \r
 /**\r
   Package. Uncore C-box 2 perfmon counter 2.\r
@@ -3006,8 +2892,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C2_PMON_CTR2               0x00000E2A\r
-\r
+#define MSR_HASWELL_E_C2_PMON_CTR2  0x00000E2A\r
 \r
 /**\r
   Package. Uncore C-box 2 perfmon counter 3.\r
@@ -3025,8 +2910,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C2_PMON_CTR3               0x00000E2B\r
-\r
+#define MSR_HASWELL_E_C2_PMON_CTR3  0x00000E2B\r
 \r
 /**\r
   Package. Uncore C-box 3 perfmon for box-wide control.\r
@@ -3044,8 +2928,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C3_PMON_BOX_CTL            0x00000E30\r
-\r
+#define MSR_HASWELL_E_C3_PMON_BOX_CTL  0x00000E30\r
 \r
 /**\r
   Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.\r
@@ -3063,8 +2946,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL0           0x00000E31\r
-\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL0  0x00000E31\r
 \r
 /**\r
   Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.\r
@@ -3082,8 +2964,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL1           0x00000E32\r
-\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL1  0x00000E32\r
 \r
 /**\r
   Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.\r
@@ -3101,8 +2982,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL2           0x00000E33\r
-\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL2  0x00000E33\r
 \r
 /**\r
   Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.\r
@@ -3120,8 +3000,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL3           0x00000E34\r
-\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL3  0x00000E34\r
 \r
 /**\r
   Package. Uncore C-box 3 perfmon box wide filter 0.\r
@@ -3139,8 +3018,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0        0x00000E35\r
-\r
+#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0  0x00000E35\r
 \r
 /**\r
   Package. Uncore C-box 3 perfmon box wide filter1.\r
@@ -3158,8 +3036,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1        0x00000E36\r
-\r
+#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1  0x00000E36\r
 \r
 /**\r
   Package. Uncore C-box 3 perfmon box wide status.\r
@@ -3177,8 +3054,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C3_PMON_BOX_STATUS         0x00000E37\r
-\r
+#define MSR_HASWELL_E_C3_PMON_BOX_STATUS  0x00000E37\r
 \r
 /**\r
   Package. Uncore C-box 3 perfmon counter 0.\r
@@ -3196,8 +3072,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C3_PMON_CTR0               0x00000E38\r
-\r
+#define MSR_HASWELL_E_C3_PMON_CTR0  0x00000E38\r
 \r
 /**\r
   Package. Uncore C-box 3 perfmon counter 1.\r
@@ -3215,8 +3090,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C3_PMON_CTR1               0x00000E39\r
-\r
+#define MSR_HASWELL_E_C3_PMON_CTR1  0x00000E39\r
 \r
 /**\r
   Package. Uncore C-box 3 perfmon counter 2.\r
@@ -3234,8 +3108,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C3_PMON_CTR2               0x00000E3A\r
-\r
+#define MSR_HASWELL_E_C3_PMON_CTR2  0x00000E3A\r
 \r
 /**\r
   Package. Uncore C-box 3 perfmon counter 3.\r
@@ -3253,8 +3126,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C3_PMON_CTR3               0x00000E3B\r
-\r
+#define MSR_HASWELL_E_C3_PMON_CTR3  0x00000E3B\r
 \r
 /**\r
   Package. Uncore C-box 4 perfmon for box-wide control.\r
@@ -3272,8 +3144,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C4_PMON_BOX_CTL            0x00000E40\r
-\r
+#define MSR_HASWELL_E_C4_PMON_BOX_CTL  0x00000E40\r
 \r
 /**\r
   Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.\r
@@ -3291,8 +3162,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL0           0x00000E41\r
-\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL0  0x00000E41\r
 \r
 /**\r
   Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.\r
@@ -3310,8 +3180,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL1           0x00000E42\r
-\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL1  0x00000E42\r
 \r
 /**\r
   Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.\r
@@ -3329,8 +3198,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL2           0x00000E43\r
-\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL2  0x00000E43\r
 \r
 /**\r
   Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.\r
@@ -3348,8 +3216,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL3           0x00000E44\r
-\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL3  0x00000E44\r
 \r
 /**\r
   Package. Uncore C-box 4 perfmon box wide filter 0.\r
@@ -3367,8 +3234,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0        0x00000E45\r
-\r
+#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0  0x00000E45\r
 \r
 /**\r
   Package. Uncore C-box 4 perfmon box wide filter1.\r
@@ -3386,8 +3252,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1        0x00000E46\r
-\r
+#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1  0x00000E46\r
 \r
 /**\r
   Package. Uncore C-box 4 perfmon box wide status.\r
@@ -3405,8 +3270,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C4_PMON_BOX_STATUS         0x00000E47\r
-\r
+#define MSR_HASWELL_E_C4_PMON_BOX_STATUS  0x00000E47\r
 \r
 /**\r
   Package. Uncore C-box 4 perfmon counter 0.\r
@@ -3424,8 +3288,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C4_PMON_CTR0               0x00000E48\r
-\r
+#define MSR_HASWELL_E_C4_PMON_CTR0  0x00000E48\r
 \r
 /**\r
   Package. Uncore C-box 4 perfmon counter 1.\r
@@ -3443,8 +3306,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C4_PMON_CTR1               0x00000E49\r
-\r
+#define MSR_HASWELL_E_C4_PMON_CTR1  0x00000E49\r
 \r
 /**\r
   Package. Uncore C-box 4 perfmon counter 2.\r
@@ -3462,8 +3324,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C4_PMON_CTR2               0x00000E4A\r
-\r
+#define MSR_HASWELL_E_C4_PMON_CTR2  0x00000E4A\r
 \r
 /**\r
   Package. Uncore C-box 4 perfmon counter 3.\r
@@ -3481,8 +3342,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C4_PMON_CTR3               0x00000E4B\r
-\r
+#define MSR_HASWELL_E_C4_PMON_CTR3  0x00000E4B\r
 \r
 /**\r
   Package. Uncore C-box 5 perfmon for box-wide control.\r
@@ -3500,8 +3360,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C5_PMON_BOX_CTL            0x00000E50\r
-\r
+#define MSR_HASWELL_E_C5_PMON_BOX_CTL  0x00000E50\r
 \r
 /**\r
   Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.\r
@@ -3519,8 +3378,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL0           0x00000E51\r
-\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL0  0x00000E51\r
 \r
 /**\r
   Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.\r
@@ -3538,8 +3396,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL1           0x00000E52\r
-\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL1  0x00000E52\r
 \r
 /**\r
   Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.\r
@@ -3557,8 +3414,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL2           0x00000E53\r
-\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL2  0x00000E53\r
 \r
 /**\r
   Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.\r
@@ -3576,8 +3432,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL3           0x00000E54\r
-\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL3  0x00000E54\r
 \r
 /**\r
   Package. Uncore C-box 5 perfmon box wide filter 0.\r
@@ -3595,8 +3450,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0        0x00000E55\r
-\r
+#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0  0x00000E55\r
 \r
 /**\r
   Package. Uncore C-box 5 perfmon box wide filter1.\r
@@ -3614,8 +3468,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1        0x00000E56\r
-\r
+#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1  0x00000E56\r
 \r
 /**\r
   Package. Uncore C-box 5 perfmon box wide status.\r
@@ -3633,8 +3486,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C5_PMON_BOX_STATUS         0x00000E57\r
-\r
+#define MSR_HASWELL_E_C5_PMON_BOX_STATUS  0x00000E57\r
 \r
 /**\r
   Package. Uncore C-box 5 perfmon counter 0.\r
@@ -3652,8 +3504,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C5_PMON_CTR0               0x00000E58\r
-\r
+#define MSR_HASWELL_E_C5_PMON_CTR0  0x00000E58\r
 \r
 /**\r
   Package. Uncore C-box 5 perfmon counter 1.\r
@@ -3671,8 +3522,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C5_PMON_CTR1               0x00000E59\r
-\r
+#define MSR_HASWELL_E_C5_PMON_CTR1  0x00000E59\r
 \r
 /**\r
   Package. Uncore C-box 5 perfmon counter 2.\r
@@ -3690,8 +3540,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C5_PMON_CTR2               0x00000E5A\r
-\r
+#define MSR_HASWELL_E_C5_PMON_CTR2  0x00000E5A\r
 \r
 /**\r
   Package. Uncore C-box 5 perfmon counter 3.\r
@@ -3709,8 +3558,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C5_PMON_CTR3               0x00000E5B\r
-\r
+#define MSR_HASWELL_E_C5_PMON_CTR3  0x00000E5B\r
 \r
 /**\r
   Package. Uncore C-box 6 perfmon for box-wide control.\r
@@ -3728,8 +3576,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C6_PMON_BOX_CTL            0x00000E60\r
-\r
+#define MSR_HASWELL_E_C6_PMON_BOX_CTL  0x00000E60\r
 \r
 /**\r
   Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.\r
@@ -3747,8 +3594,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL0           0x00000E61\r
-\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL0  0x00000E61\r
 \r
 /**\r
   Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.\r
@@ -3766,8 +3612,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL1           0x00000E62\r
-\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL1  0x00000E62\r
 \r
 /**\r
   Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.\r
@@ -3785,8 +3630,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL2           0x00000E63\r
-\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL2  0x00000E63\r
 \r
 /**\r
   Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.\r
@@ -3804,8 +3648,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL3           0x00000E64\r
-\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL3  0x00000E64\r
 \r
 /**\r
   Package. Uncore C-box 6 perfmon box wide filter 0.\r
@@ -3823,8 +3666,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0        0x00000E65\r
-\r
+#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0  0x00000E65\r
 \r
 /**\r
   Package. Uncore C-box 6 perfmon box wide filter1.\r
@@ -3842,8 +3684,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1        0x00000E66\r
-\r
+#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1  0x00000E66\r
 \r
 /**\r
   Package. Uncore C-box 6 perfmon box wide status.\r
@@ -3861,8 +3702,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C6_PMON_BOX_STATUS         0x00000E67\r
-\r
+#define MSR_HASWELL_E_C6_PMON_BOX_STATUS  0x00000E67\r
 \r
 /**\r
   Package. Uncore C-box 6 perfmon counter 0.\r
@@ -3880,8 +3720,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C6_PMON_CTR0               0x00000E68\r
-\r
+#define MSR_HASWELL_E_C6_PMON_CTR0  0x00000E68\r
 \r
 /**\r
   Package. Uncore C-box 6 perfmon counter 1.\r
@@ -3899,8 +3738,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C6_PMON_CTR1               0x00000E69\r
-\r
+#define MSR_HASWELL_E_C6_PMON_CTR1  0x00000E69\r
 \r
 /**\r
   Package. Uncore C-box 6 perfmon counter 2.\r
@@ -3918,8 +3756,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C6_PMON_CTR2               0x00000E6A\r
-\r
+#define MSR_HASWELL_E_C6_PMON_CTR2  0x00000E6A\r
 \r
 /**\r
   Package. Uncore C-box 6 perfmon counter 3.\r
@@ -3937,8 +3774,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C6_PMON_CTR3               0x00000E6B\r
-\r
+#define MSR_HASWELL_E_C6_PMON_CTR3  0x00000E6B\r
 \r
 /**\r
   Package. Uncore C-box 7 perfmon for box-wide control.\r
@@ -3956,8 +3792,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C7_PMON_BOX_CTL            0x00000E70\r
-\r
+#define MSR_HASWELL_E_C7_PMON_BOX_CTL  0x00000E70\r
 \r
 /**\r
   Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.\r
@@ -3975,8 +3810,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL0           0x00000E71\r
-\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL0  0x00000E71\r
 \r
 /**\r
   Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.\r
@@ -3994,8 +3828,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL1           0x00000E72\r
-\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL1  0x00000E72\r
 \r
 /**\r
   Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.\r
@@ -4013,8 +3846,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL2           0x00000E73\r
-\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL2  0x00000E73\r
 \r
 /**\r
   Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.\r
@@ -4032,8 +3864,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL3           0x00000E74\r
-\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL3  0x00000E74\r
 \r
 /**\r
   Package. Uncore C-box 7 perfmon box wide filter 0.\r
@@ -4051,8 +3882,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0        0x00000E75\r
-\r
+#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0  0x00000E75\r
 \r
 /**\r
   Package. Uncore C-box 7 perfmon box wide filter1.\r
@@ -4070,8 +3900,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1        0x00000E76\r
-\r
+#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1  0x00000E76\r
 \r
 /**\r
   Package. Uncore C-box 7 perfmon box wide status.\r
@@ -4089,8 +3918,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C7_PMON_BOX_STATUS         0x00000E77\r
-\r
+#define MSR_HASWELL_E_C7_PMON_BOX_STATUS  0x00000E77\r
 \r
 /**\r
   Package. Uncore C-box 7 perfmon counter 0.\r
@@ -4108,8 +3936,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C7_PMON_CTR0               0x00000E78\r
-\r
+#define MSR_HASWELL_E_C7_PMON_CTR0  0x00000E78\r
 \r
 /**\r
   Package. Uncore C-box 7 perfmon counter 1.\r
@@ -4127,8 +3954,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C7_PMON_CTR1               0x00000E79\r
-\r
+#define MSR_HASWELL_E_C7_PMON_CTR1  0x00000E79\r
 \r
 /**\r
   Package. Uncore C-box 7 perfmon counter 2.\r
@@ -4146,8 +3972,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C7_PMON_CTR2               0x00000E7A\r
-\r
+#define MSR_HASWELL_E_C7_PMON_CTR2  0x00000E7A\r
 \r
 /**\r
   Package. Uncore C-box 7 perfmon counter 3.\r
@@ -4165,8 +3990,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C7_PMON_CTR3               0x00000E7B\r
-\r
+#define MSR_HASWELL_E_C7_PMON_CTR3  0x00000E7B\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon local box wide control.\r
@@ -4184,8 +4008,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C8_PMON_BOX_CTL            0x00000E80\r
-\r
+#define MSR_HASWELL_E_C8_PMON_BOX_CTL  0x00000E80\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r
@@ -4203,8 +4026,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL0           0x00000E81\r
-\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL0  0x00000E81\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r
@@ -4222,8 +4044,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL1           0x00000E82\r
-\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL1  0x00000E82\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r
@@ -4241,8 +4062,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL2           0x00000E83\r
-\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL2  0x00000E83\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r
@@ -4260,8 +4080,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL3           0x00000E84\r
-\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL3  0x00000E84\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon box wide filter0.\r
@@ -4279,8 +4098,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0        0x00000E85\r
-\r
+#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0  0x00000E85\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon box wide filter1.\r
@@ -4298,8 +4116,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1        0x00000E86\r
-\r
+#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1  0x00000E86\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon box wide status.\r
@@ -4317,8 +4134,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C8_PMON_BOX_STATUS         0x00000E87\r
-\r
+#define MSR_HASWELL_E_C8_PMON_BOX_STATUS  0x00000E87\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon counter 0.\r
@@ -4336,8 +4152,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C8_PMON_CTR0               0x00000E88\r
-\r
+#define MSR_HASWELL_E_C8_PMON_CTR0  0x00000E88\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon counter 1.\r
@@ -4355,8 +4170,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C8_PMON_CTR1               0x00000E89\r
-\r
+#define MSR_HASWELL_E_C8_PMON_CTR1  0x00000E89\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon counter 2.\r
@@ -4374,8 +4188,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C8_PMON_CTR2               0x00000E8A\r
-\r
+#define MSR_HASWELL_E_C8_PMON_CTR2  0x00000E8A\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon counter 3.\r
@@ -4393,8 +4206,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C8_PMON_CTR3               0x00000E8B\r
-\r
+#define MSR_HASWELL_E_C8_PMON_CTR3  0x00000E8B\r
 \r
 /**\r
   Package. Uncore C-box 9 perfmon local box wide control.\r
@@ -4412,8 +4224,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C9_PMON_BOX_CTL            0x00000E90\r
-\r
+#define MSR_HASWELL_E_C9_PMON_BOX_CTL  0x00000E90\r
 \r
 /**\r
   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r
@@ -4431,8 +4242,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL0           0x00000E91\r
-\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL0  0x00000E91\r
 \r
 /**\r
   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r
@@ -4450,8 +4260,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL1           0x00000E92\r
-\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL1  0x00000E92\r
 \r
 /**\r
   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r
@@ -4469,8 +4278,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL2           0x00000E93\r
-\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL2  0x00000E93\r
 \r
 /**\r
   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r
@@ -4488,8 +4296,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL3           0x00000E94\r
-\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL3  0x00000E94\r
 \r
 /**\r
   Package. Uncore C-box 9 perfmon box wide filter0.\r
@@ -4507,8 +4314,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0        0x00000E95\r
-\r
+#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0  0x00000E95\r
 \r
 /**\r
   Package. Uncore C-box 9 perfmon box wide filter1.\r
@@ -4526,8 +4332,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1        0x00000E96\r
-\r
+#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1  0x00000E96\r
 \r
 /**\r
   Package. Uncore C-box 9 perfmon box wide status.\r
@@ -4545,8 +4350,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C9_PMON_BOX_STATUS         0x00000E97\r
-\r
+#define MSR_HASWELL_E_C9_PMON_BOX_STATUS  0x00000E97\r
 \r
 /**\r
   Package. Uncore C-box 9 perfmon counter 0.\r
@@ -4564,8 +4368,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C9_PMON_CTR0               0x00000E98\r
-\r
+#define MSR_HASWELL_E_C9_PMON_CTR0  0x00000E98\r
 \r
 /**\r
   Package. Uncore C-box 9 perfmon counter 1.\r
@@ -4583,8 +4386,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C9_PMON_CTR1               0x00000E99\r
-\r
+#define MSR_HASWELL_E_C9_PMON_CTR1  0x00000E99\r
 \r
 /**\r
   Package. Uncore C-box 9 perfmon counter 2.\r
@@ -4602,8 +4404,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C9_PMON_CTR2               0x00000E9A\r
-\r
+#define MSR_HASWELL_E_C9_PMON_CTR2  0x00000E9A\r
 \r
 /**\r
   Package. Uncore C-box 9 perfmon counter 3.\r
@@ -4621,8 +4422,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C9_PMON_CTR3               0x00000E9B\r
-\r
+#define MSR_HASWELL_E_C9_PMON_CTR3  0x00000E9B\r
 \r
 /**\r
   Package. Uncore C-box 10 perfmon local box wide control.\r
@@ -4640,8 +4440,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C10_PMON_BOX_CTL           0x00000EA0\r
-\r
+#define MSR_HASWELL_E_C10_PMON_BOX_CTL  0x00000EA0\r
 \r
 /**\r
   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r
@@ -4659,8 +4458,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL0          0x00000EA1\r
-\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL0  0x00000EA1\r
 \r
 /**\r
   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r
@@ -4678,8 +4476,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL1          0x00000EA2\r
-\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL1  0x00000EA2\r
 \r
 /**\r
   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r
@@ -4697,8 +4494,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL2          0x00000EA3\r
-\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL2  0x00000EA3\r
 \r
 /**\r
   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r
@@ -4716,8 +4512,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL3          0x00000EA4\r
-\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL3  0x00000EA4\r
 \r
 /**\r
   Package. Uncore C-box 10 perfmon box wide filter0.\r
@@ -4735,8 +4530,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0       0x00000EA5\r
-\r
+#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0  0x00000EA5\r
 \r
 /**\r
   Package. Uncore C-box 10 perfmon box wide filter1.\r
@@ -4754,8 +4548,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1       0x00000EA6\r
-\r
+#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1  0x00000EA6\r
 \r
 /**\r
   Package. Uncore C-box 10 perfmon box wide status.\r
@@ -4773,8 +4566,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C10_PMON_BOX_STATUS        0x00000EA7\r
-\r
+#define MSR_HASWELL_E_C10_PMON_BOX_STATUS  0x00000EA7\r
 \r
 /**\r
   Package. Uncore C-box 10 perfmon counter 0.\r
@@ -4792,8 +4584,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C10_PMON_CTR0              0x00000EA8\r
-\r
+#define MSR_HASWELL_E_C10_PMON_CTR0  0x00000EA8\r
 \r
 /**\r
   Package. Uncore C-box 10 perfmon counter 1.\r
@@ -4811,8 +4602,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C10_PMON_CTR1              0x00000EA9\r
-\r
+#define MSR_HASWELL_E_C10_PMON_CTR1  0x00000EA9\r
 \r
 /**\r
   Package. Uncore C-box 10 perfmon counter 2.\r
@@ -4830,8 +4620,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C10_PMON_CTR2              0x00000EAA\r
-\r
+#define MSR_HASWELL_E_C10_PMON_CTR2  0x00000EAA\r
 \r
 /**\r
   Package. Uncore C-box 10 perfmon counter 3.\r
@@ -4849,8 +4638,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C10_PMON_CTR3              0x00000EAB\r
-\r
+#define MSR_HASWELL_E_C10_PMON_CTR3  0x00000EAB\r
 \r
 /**\r
   Package. Uncore C-box 11 perfmon local box wide control.\r
@@ -4868,8 +4656,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C11_PMON_BOX_CTL           0x00000EB0\r
-\r
+#define MSR_HASWELL_E_C11_PMON_BOX_CTL  0x00000EB0\r
 \r
 /**\r
   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r
@@ -4887,8 +4674,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL0          0x00000EB1\r
-\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL0  0x00000EB1\r
 \r
 /**\r
   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r
@@ -4906,8 +4692,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL1          0x00000EB2\r
-\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL1  0x00000EB2\r
 \r
 /**\r
   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r
@@ -4925,8 +4710,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL2          0x00000EB3\r
-\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL2  0x00000EB3\r
 \r
 /**\r
   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r
@@ -4944,8 +4728,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL3          0x00000EB4\r
-\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL3  0x00000EB4\r
 \r
 /**\r
   Package. Uncore C-box 11 perfmon box wide filter0.\r
@@ -4963,8 +4746,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0       0x00000EB5\r
-\r
+#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0  0x00000EB5\r
 \r
 /**\r
   Package. Uncore C-box 11 perfmon box wide filter1.\r
@@ -4982,8 +4764,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1       0x00000EB6\r
-\r
+#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1  0x00000EB6\r
 \r
 /**\r
   Package. Uncore C-box 11 perfmon box wide status.\r
@@ -5001,8 +4782,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C11_PMON_BOX_STATUS        0x00000EB7\r
-\r
+#define MSR_HASWELL_E_C11_PMON_BOX_STATUS  0x00000EB7\r
 \r
 /**\r
   Package. Uncore C-box 11 perfmon counter 0.\r
@@ -5020,8 +4800,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C11_PMON_CTR0              0x00000EB8\r
-\r
+#define MSR_HASWELL_E_C11_PMON_CTR0  0x00000EB8\r
 \r
 /**\r
   Package. Uncore C-box 11 perfmon counter 1.\r
@@ -5039,8 +4818,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C11_PMON_CTR1              0x00000EB9\r
-\r
+#define MSR_HASWELL_E_C11_PMON_CTR1  0x00000EB9\r
 \r
 /**\r
   Package. Uncore C-box 11 perfmon counter 2.\r
@@ -5058,8 +4836,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C11_PMON_CTR2              0x00000EBA\r
-\r
+#define MSR_HASWELL_E_C11_PMON_CTR2  0x00000EBA\r
 \r
 /**\r
   Package. Uncore C-box 11 perfmon counter 3.\r
@@ -5077,8 +4854,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C11_PMON_CTR3              0x00000EBB\r
-\r
+#define MSR_HASWELL_E_C11_PMON_CTR3  0x00000EBB\r
 \r
 /**\r
   Package. Uncore C-box 12 perfmon local box wide control.\r
@@ -5096,8 +4872,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C12_PMON_BOX_CTL           0x00000EC0\r
-\r
+#define MSR_HASWELL_E_C12_PMON_BOX_CTL  0x00000EC0\r
 \r
 /**\r
   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r
@@ -5115,8 +4890,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL0          0x00000EC1\r
-\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL0  0x00000EC1\r
 \r
 /**\r
   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r
@@ -5134,8 +4908,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL1          0x00000EC2\r
-\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL1  0x00000EC2\r
 \r
 /**\r
   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r
@@ -5153,8 +4926,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL2          0x00000EC3\r
-\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL2  0x00000EC3\r
 \r
 /**\r
   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r
@@ -5172,8 +4944,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL3          0x00000EC4\r
-\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL3  0x00000EC4\r
 \r
 /**\r
   Package. Uncore C-box 12 perfmon box wide filter0.\r
@@ -5191,8 +4962,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0       0x00000EC5\r
-\r
+#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0  0x00000EC5\r
 \r
 /**\r
   Package. Uncore C-box 12 perfmon box wide filter1.\r
@@ -5210,8 +4980,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1       0x00000EC6\r
-\r
+#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1  0x00000EC6\r
 \r
 /**\r
   Package. Uncore C-box 12 perfmon box wide status.\r
@@ -5229,8 +4998,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C12_PMON_BOX_STATUS        0x00000EC7\r
-\r
+#define MSR_HASWELL_E_C12_PMON_BOX_STATUS  0x00000EC7\r
 \r
 /**\r
   Package. Uncore C-box 12 perfmon counter 0.\r
@@ -5248,8 +5016,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C12_PMON_CTR0              0x00000EC8\r
-\r
+#define MSR_HASWELL_E_C12_PMON_CTR0  0x00000EC8\r
 \r
 /**\r
   Package. Uncore C-box 12 perfmon counter 1.\r
@@ -5267,8 +5034,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C12_PMON_CTR1              0x00000EC9\r
-\r
+#define MSR_HASWELL_E_C12_PMON_CTR1  0x00000EC9\r
 \r
 /**\r
   Package. Uncore C-box 12 perfmon counter 2.\r
@@ -5286,8 +5052,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C12_PMON_CTR2              0x00000ECA\r
-\r
+#define MSR_HASWELL_E_C12_PMON_CTR2  0x00000ECA\r
 \r
 /**\r
   Package. Uncore C-box 12 perfmon counter 3.\r
@@ -5305,8 +5070,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C12_PMON_CTR3              0x00000ECB\r
-\r
+#define MSR_HASWELL_E_C12_PMON_CTR3  0x00000ECB\r
 \r
 /**\r
   Package. Uncore C-box 13 perfmon local box wide control.\r
@@ -5324,8 +5088,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C13_PMON_BOX_CTL           0x00000ED0\r
-\r
+#define MSR_HASWELL_E_C13_PMON_BOX_CTL  0x00000ED0\r
 \r
 /**\r
   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r
@@ -5343,8 +5106,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL0          0x00000ED1\r
-\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL0  0x00000ED1\r
 \r
 /**\r
   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r
@@ -5362,8 +5124,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL1          0x00000ED2\r
-\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL1  0x00000ED2\r
 \r
 /**\r
   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r
@@ -5381,8 +5142,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL2          0x00000ED3\r
-\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL2  0x00000ED3\r
 \r
 /**\r
   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r
@@ -5400,8 +5160,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL3          0x00000ED4\r
-\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL3  0x00000ED4\r
 \r
 /**\r
   Package. Uncore C-box 13 perfmon box wide filter0.\r
@@ -5419,8 +5178,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0       0x00000ED5\r
-\r
+#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0  0x00000ED5\r
 \r
 /**\r
   Package. Uncore C-box 13 perfmon box wide filter1.\r
@@ -5438,8 +5196,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1       0x00000ED6\r
-\r
+#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1  0x00000ED6\r
 \r
 /**\r
   Package. Uncore C-box 13 perfmon box wide status.\r
@@ -5457,8 +5214,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C13_PMON_BOX_STATUS        0x00000ED7\r
-\r
+#define MSR_HASWELL_E_C13_PMON_BOX_STATUS  0x00000ED7\r
 \r
 /**\r
   Package. Uncore C-box 13 perfmon counter 0.\r
@@ -5476,8 +5232,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C13_PMON_CTR0              0x00000ED8\r
-\r
+#define MSR_HASWELL_E_C13_PMON_CTR0  0x00000ED8\r
 \r
 /**\r
   Package. Uncore C-box 13 perfmon counter 1.\r
@@ -5495,8 +5250,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C13_PMON_CTR1              0x00000ED9\r
-\r
+#define MSR_HASWELL_E_C13_PMON_CTR1  0x00000ED9\r
 \r
 /**\r
   Package. Uncore C-box 13 perfmon counter 2.\r
@@ -5514,8 +5268,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C13_PMON_CTR2              0x00000EDA\r
-\r
+#define MSR_HASWELL_E_C13_PMON_CTR2  0x00000EDA\r
 \r
 /**\r
   Package. Uncore C-box 13 perfmon counter 3.\r
@@ -5533,8 +5286,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C13_PMON_CTR3              0x00000EDB\r
-\r
+#define MSR_HASWELL_E_C13_PMON_CTR3  0x00000EDB\r
 \r
 /**\r
   Package. Uncore C-box 14 perfmon local box wide control.\r
@@ -5552,8 +5304,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C14_PMON_BOX_CTL           0x00000EE0\r
-\r
+#define MSR_HASWELL_E_C14_PMON_BOX_CTL  0x00000EE0\r
 \r
 /**\r
   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r
@@ -5571,8 +5322,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL0          0x00000EE1\r
-\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL0  0x00000EE1\r
 \r
 /**\r
   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r
@@ -5590,8 +5340,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL1          0x00000EE2\r
-\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL1  0x00000EE2\r
 \r
 /**\r
   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r
@@ -5609,8 +5358,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL2          0x00000EE3\r
-\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL2  0x00000EE3\r
 \r
 /**\r
   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r
@@ -5628,8 +5376,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL3          0x00000EE4\r
-\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL3  0x00000EE4\r
 \r
 /**\r
   Package. Uncore C-box 14 perfmon box wide filter0.\r
@@ -5647,8 +5394,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C14_PMON_BOX_FILTER        0x00000EE5\r
-\r
+#define MSR_HASWELL_E_C14_PMON_BOX_FILTER  0x00000EE5\r
 \r
 /**\r
   Package. Uncore C-box 14 perfmon box wide filter1.\r
@@ -5666,8 +5412,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1       0x00000EE6\r
-\r
+#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1  0x00000EE6\r
 \r
 /**\r
   Package. Uncore C-box 14 perfmon box wide status.\r
@@ -5685,8 +5430,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C14_PMON_BOX_STATUS        0x00000EE7\r
-\r
+#define MSR_HASWELL_E_C14_PMON_BOX_STATUS  0x00000EE7\r
 \r
 /**\r
   Package. Uncore C-box 14 perfmon counter 0.\r
@@ -5704,8 +5448,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C14_PMON_CTR0              0x00000EE8\r
-\r
+#define MSR_HASWELL_E_C14_PMON_CTR0  0x00000EE8\r
 \r
 /**\r
   Package. Uncore C-box 14 perfmon counter 1.\r
@@ -5723,8 +5466,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C14_PMON_CTR1              0x00000EE9\r
-\r
+#define MSR_HASWELL_E_C14_PMON_CTR1  0x00000EE9\r
 \r
 /**\r
   Package. Uncore C-box 14 perfmon counter 2.\r
@@ -5742,8 +5484,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C14_PMON_CTR2              0x00000EEA\r
-\r
+#define MSR_HASWELL_E_C14_PMON_CTR2  0x00000EEA\r
 \r
 /**\r
   Package. Uncore C-box 14 perfmon counter 3.\r
@@ -5761,8 +5502,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C14_PMON_CTR3              0x00000EEB\r
-\r
+#define MSR_HASWELL_E_C14_PMON_CTR3  0x00000EEB\r
 \r
 /**\r
   Package. Uncore C-box 15 perfmon local box wide control.\r
@@ -5780,8 +5520,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C15_PMON_BOX_CTL           0x00000EF0\r
-\r
+#define MSR_HASWELL_E_C15_PMON_BOX_CTL  0x00000EF0\r
 \r
 /**\r
   Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.\r
@@ -5799,8 +5538,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL0          0x00000EF1\r
-\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL0  0x00000EF1\r
 \r
 /**\r
   Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.\r
@@ -5818,8 +5556,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL1          0x00000EF2\r
-\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL1  0x00000EF2\r
 \r
 /**\r
   Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.\r
@@ -5837,8 +5574,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL2          0x00000EF3\r
-\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL2  0x00000EF3\r
 \r
 /**\r
   Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.\r
@@ -5856,8 +5592,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL3          0x00000EF4\r
-\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL3  0x00000EF4\r
 \r
 /**\r
   Package. Uncore C-box 15 perfmon box wide filter0.\r
@@ -5875,8 +5610,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0       0x00000EF5\r
-\r
+#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0  0x00000EF5\r
 \r
 /**\r
   Package. Uncore C-box 15 perfmon box wide filter1.\r
@@ -5894,8 +5628,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1       0x00000EF6\r
-\r
+#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1  0x00000EF6\r
 \r
 /**\r
   Package. Uncore C-box 15 perfmon box wide status.\r
@@ -5913,8 +5646,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C15_PMON_BOX_STATUS        0x00000EF7\r
-\r
+#define MSR_HASWELL_E_C15_PMON_BOX_STATUS  0x00000EF7\r
 \r
 /**\r
   Package. Uncore C-box 15 perfmon counter 0.\r
@@ -5932,8 +5664,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C15_PMON_CTR0              0x00000EF8\r
-\r
+#define MSR_HASWELL_E_C15_PMON_CTR0  0x00000EF8\r
 \r
 /**\r
   Package. Uncore C-box 15 perfmon counter 1.\r
@@ -5951,8 +5682,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C15_PMON_CTR1              0x00000EF9\r
-\r
+#define MSR_HASWELL_E_C15_PMON_CTR1  0x00000EF9\r
 \r
 /**\r
   Package. Uncore C-box 15 perfmon counter 2.\r
@@ -5970,8 +5700,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C15_PMON_CTR2              0x00000EFA\r
-\r
+#define MSR_HASWELL_E_C15_PMON_CTR2  0x00000EFA\r
 \r
 /**\r
   Package. Uncore C-box 15 perfmon counter 3.\r
@@ -5989,8 +5718,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C15_PMON_CTR3              0x00000EFB\r
-\r
+#define MSR_HASWELL_E_C15_PMON_CTR3  0x00000EFB\r
 \r
 /**\r
   Package. Uncore C-box 16 perfmon for box-wide control.\r
@@ -6008,8 +5736,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C16_PMON_BOX_CTL           0x00000F00\r
-\r
+#define MSR_HASWELL_E_C16_PMON_BOX_CTL  0x00000F00\r
 \r
 /**\r
   Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.\r
@@ -6027,8 +5754,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL0          0x00000F01\r
-\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL0  0x00000F01\r
 \r
 /**\r
   Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.\r
@@ -6046,8 +5772,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL1          0x00000F02\r
-\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL1  0x00000F02\r
 \r
 /**\r
   Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.\r
@@ -6065,8 +5790,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL2          0x00000F03\r
-\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL2  0x00000F03\r
 \r
 /**\r
   Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.\r
@@ -6084,8 +5808,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL3          0x00000F04\r
-\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL3  0x00000F04\r
 \r
 /**\r
   Package. Uncore C-box 16 perfmon box wide filter 0.\r
@@ -6103,8 +5826,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0       0x00000F05\r
-\r
+#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0  0x00000F05\r
 \r
 /**\r
   Package. Uncore C-box 16 perfmon box wide filter 1.\r
@@ -6122,8 +5844,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1       0x00000F06\r
-\r
+#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1  0x00000F06\r
 \r
 /**\r
   Package. Uncore C-box 16 perfmon box wide status.\r
@@ -6141,8 +5862,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C16_PMON_BOX_STATUS        0x00000F07\r
-\r
+#define MSR_HASWELL_E_C16_PMON_BOX_STATUS  0x00000F07\r
 \r
 /**\r
   Package. Uncore C-box 16 perfmon counter 0.\r
@@ -6160,8 +5880,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C16_PMON_CTR0              0x00000F08\r
-\r
+#define MSR_HASWELL_E_C16_PMON_CTR0  0x00000F08\r
 \r
 /**\r
   Package. Uncore C-box 16 perfmon counter 1.\r
@@ -6179,8 +5898,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C16_PMON_CTR1              0x00000F09\r
-\r
+#define MSR_HASWELL_E_C16_PMON_CTR1  0x00000F09\r
 \r
 /**\r
   Package. Uncore C-box 16 perfmon counter 2.\r
@@ -6198,8 +5916,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C16_PMON_CTR2              0x00000F0A\r
-\r
+#define MSR_HASWELL_E_C16_PMON_CTR2  0x00000F0A\r
 \r
 /**\r
   Package. Uncore C-box 16 perfmon counter 3.\r
@@ -6217,8 +5934,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C16_PMON_CTR3              0x00000E0B\r
-\r
+#define MSR_HASWELL_E_C16_PMON_CTR3  0x00000E0B\r
 \r
 /**\r
   Package. Uncore C-box 17 perfmon for box-wide control.\r
@@ -6236,8 +5952,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C17_PMON_BOX_CTL           0x00000F10\r
-\r
+#define MSR_HASWELL_E_C17_PMON_BOX_CTL  0x00000F10\r
 \r
 /**\r
   Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.\r
@@ -6255,8 +5970,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL0          0x00000F11\r
-\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL0  0x00000F11\r
 \r
 /**\r
   Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.\r
@@ -6274,8 +5988,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL1          0x00000F12\r
-\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL1  0x00000F12\r
 \r
 /**\r
   Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.\r
@@ -6293,8 +6006,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL2          0x00000F13\r
-\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL2  0x00000F13\r
 \r
 /**\r
   Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.\r
@@ -6312,8 +6024,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL3          0x00000F14\r
-\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL3  0x00000F14\r
 \r
 /**\r
   Package. Uncore C-box 17 perfmon box wide filter 0.\r
@@ -6331,8 +6042,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0       0x00000F15\r
-\r
+#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0  0x00000F15\r
 \r
 /**\r
   Package. Uncore C-box 17 perfmon box wide filter1.\r
@@ -6350,7 +6060,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1       0x00000F16\r
+#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1  0x00000F16\r
 \r
 /**\r
   Package. Uncore C-box 17 perfmon box wide status.\r
@@ -6368,8 +6078,7 @@ typedef union {
   @endcode\r
   @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_HASWELL_E_C17_PMON_BOX_STATUS        0x00000F17\r
-\r
+#define MSR_HASWELL_E_C17_PMON_BOX_STATUS  0x00000F17\r
 \r
 /**\r
   Package. Uncore C-box 17 perfmon counter n.\r
@@ -6391,10 +6100,10 @@ typedef union {
         MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.\r
   @{\r
 **/\r
-#define MSR_HASWELL_E_C17_PMON_CTR0              0x00000F18\r
-#define MSR_HASWELL_E_C17_PMON_CTR1              0x00000F19\r
-#define MSR_HASWELL_E_C17_PMON_CTR2              0x00000F1A\r
-#define MSR_HASWELL_E_C17_PMON_CTR3              0x00000F1B\r
+#define MSR_HASWELL_E_C17_PMON_CTR0  0x00000F18\r
+#define MSR_HASWELL_E_C17_PMON_CTR1  0x00000F19\r
+#define MSR_HASWELL_E_C17_PMON_CTR2  0x00000F1A\r
+#define MSR_HASWELL_E_C17_PMON_CTR3  0x00000F1B\r
 /// @}\r
 \r
 #endif\r