@endcode\r
@note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
-#define MSR_HASWELL_PLATFORM_INFO 0x000000CE\r
+#define MSR_HASWELL_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
/// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
/// MHz.\r
///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
+ UINT32 MaximumNonTurboRatio : 8;\r
+ UINT32 Reserved2 : 12;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
/// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
/// Turbo mode is disabled.\r
///\r
- UINT32 RatioLimit:1;\r
+ UINT32 RatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
/// and when set to 0, indicates TDP Limit for Turbo mode is not\r
/// programmable.\r
///\r
- UINT32 TDPLimit:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 TDPLimit : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,\r
/// indicates that LPM is supported, and when set to 0, indicates LPM is\r
/// not supported.\r
///\r
- UINT32 LowPowerModeSupport:1;\r
+ UINT32 LowPowerModeSupport : 1;\r
///\r
/// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base\r
/// TDP level available. 01: One additional TDP level available. 02: Two\r
/// additional TDP level available. 11: Reserved.\r
///\r
- UINT32 ConfigTDPLevels:2;\r
- UINT32 Reserved4:5;\r
+ UINT32 ConfigTDPLevels : 2;\r
+ UINT32 Reserved4 : 5;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
/// minimum ratio (maximum efficiency) that the processor can operates, in\r
/// units of 100MHz.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
///\r
/// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the\r
/// minimum supported operating ratio in units of 100 MHz.\r
///\r
- UINT32 MinimumOperatingRatio:8;\r
- UINT32 Reserved5:8;\r
+ UINT32 MinimumOperatingRatio : 8;\r
+ UINT32 Reserved5 : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_PLATFORM_INFO_REGISTER;\r
\r
-\r
/**\r
Thread. Performance Event Select for Counter n (R/W) Supports all fields\r
described inTable 2-2 and the fields below.\r
MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r
@{\r
**/\r
-#define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186\r
-#define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187\r
-#define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189\r
+#define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186\r
+#define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187\r
+#define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189\r
/// @}\r
\r
/**\r
///\r
/// [Bits 7:0] Event Select: Selects a performance event logic unit.\r
///\r
- UINT32 EventSelect:8;\r
+ UINT32 EventSelect : 8;\r
///\r
/// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r
/// detect on the selected event logic.\r
///\r
- UINT32 UMASK:8;\r
+ UINT32 UMASK : 8;\r
///\r
/// [Bit 16] USR: Counts while in privilege level is not ring 0.\r
///\r
- UINT32 USR:1;\r
+ UINT32 USR : 1;\r
///\r
/// [Bit 17] OS: Counts while in privilege level is ring 0.\r
///\r
- UINT32 OS:1;\r
+ UINT32 OS : 1;\r
///\r
/// [Bit 18] Edge: Enables edge detection if set.\r
///\r
- UINT32 E:1;\r
+ UINT32 E : 1;\r
///\r
/// [Bit 19] PC: enables pin control.\r
///\r
- UINT32 PC:1;\r
+ UINT32 PC : 1;\r
///\r
/// [Bit 20] INT: enables interrupt on counter overflow.\r
///\r
- UINT32 INT:1;\r
+ UINT32 INT : 1;\r
///\r
/// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r
/// event conditions occurring across all logical processors sharing a\r
/// associated event conditions occurring in the logical processor which\r
/// programmed the MSR.\r
///\r
- UINT32 ANY:1;\r
+ UINT32 ANY : 1;\r
///\r
/// [Bit 22] EN: enables the corresponding performance counter to commence\r
/// counting when this bit is set.\r
///\r
- UINT32 EN:1;\r
+ UINT32 EN : 1;\r
///\r
/// [Bit 23] INV: invert the CMASK.\r
///\r
- UINT32 INV:1;\r
+ UINT32 INV : 1;\r
///\r
/// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r
/// performance counter increments each cycle if the event count is\r
/// greater than or equal to the CMASK.\r
///\r
- UINT32 CMASK:8;\r
- UINT32 Reserved:32;\r
+ UINT32 CMASK : 8;\r
+ UINT32 Reserved : 32;\r
///\r
/// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,\r
/// AnyThread (bit 21) should be cleared to prevent incorrect results.\r
///\r
- UINT32 IN_TX:1;\r
- UINT32 Reserved2:31;\r
+ UINT32 IN_TX : 1;\r
+ UINT32 Reserved2 : 31;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_IA32_PERFEVTSEL_REGISTER;\r
\r
-\r
/**\r
Thread. Performance Event Select for Counter 2 (R/W) Supports all fields\r
described inTable 2-2 and the fields below.\r
@endcode\r
@note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188\r
+#define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2\r
///\r
/// [Bits 7:0] Event Select: Selects a performance event logic unit.\r
///\r
- UINT32 EventSelect:8;\r
+ UINT32 EventSelect : 8;\r
///\r
/// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r
/// detect on the selected event logic.\r
///\r
- UINT32 UMASK:8;\r
+ UINT32 UMASK : 8;\r
///\r
/// [Bit 16] USR: Counts while in privilege level is not ring 0.\r
///\r
- UINT32 USR:1;\r
+ UINT32 USR : 1;\r
///\r
/// [Bit 17] OS: Counts while in privilege level is ring 0.\r
///\r
- UINT32 OS:1;\r
+ UINT32 OS : 1;\r
///\r
/// [Bit 18] Edge: Enables edge detection if set.\r
///\r
- UINT32 E:1;\r
+ UINT32 E : 1;\r
///\r
/// [Bit 19] PC: enables pin control.\r
///\r
- UINT32 PC:1;\r
+ UINT32 PC : 1;\r
///\r
/// [Bit 20] INT: enables interrupt on counter overflow.\r
///\r
- UINT32 INT:1;\r
+ UINT32 INT : 1;\r
///\r
/// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r
/// event conditions occurring across all logical processors sharing a\r
/// associated event conditions occurring in the logical processor which\r
/// programmed the MSR.\r
///\r
- UINT32 ANY:1;\r
+ UINT32 ANY : 1;\r
///\r
/// [Bit 22] EN: enables the corresponding performance counter to commence\r
/// counting when this bit is set.\r
///\r
- UINT32 EN:1;\r
+ UINT32 EN : 1;\r
///\r
/// [Bit 23] INV: invert the CMASK.\r
///\r
- UINT32 INV:1;\r
+ UINT32 INV : 1;\r
///\r
/// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r
/// performance counter increments each cycle if the event count is\r
/// greater than or equal to the CMASK.\r
///\r
- UINT32 CMASK:8;\r
- UINT32 Reserved:32;\r
+ UINT32 CMASK : 8;\r
+ UINT32 Reserved : 32;\r
///\r
/// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,\r
/// AnyThread (bit 21) should be cleared to prevent incorrect results.\r
///\r
- UINT32 IN_TX:1;\r
+ UINT32 IN_TX : 1;\r
///\r
/// [Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and\r
/// in sampling, spurious PMI may occur and transactions may continuously\r
/// IN_TXCP and also always reset the counter even when no overflow\r
/// condition was reported.\r
///\r
- UINT32 IN_TXCP:1;\r
- UINT32 Reserved2:30;\r
+ UINT32 IN_TXCP : 1;\r
+ UINT32 Reserved2 : 30;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER;\r
\r
-\r
/**\r
Thread. Last Branch Record Filtering Select Register (R/W).\r
\r
@endcode\r
@note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
**/\r
-#define MSR_HASWELL_LBR_SELECT 0x000001C8\r
+#define MSR_HASWELL_LBR_SELECT 0x000001C8\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT\r
///\r
/// [Bit 0] CPL_EQ_0.\r
///\r
- UINT32 CPL_EQ_0:1;\r
+ UINT32 CPL_EQ_0 : 1;\r
///\r
/// [Bit 1] CPL_NEQ_0.\r
///\r
- UINT32 CPL_NEQ_0:1;\r
+ UINT32 CPL_NEQ_0 : 1;\r
///\r
/// [Bit 2] JCC.\r
///\r
- UINT32 JCC:1;\r
+ UINT32 JCC : 1;\r
///\r
/// [Bit 3] NEAR_REL_CALL.\r
///\r
- UINT32 NEAR_REL_CALL:1;\r
+ UINT32 NEAR_REL_CALL : 1;\r
///\r
/// [Bit 4] NEAR_IND_CALL.\r
///\r
- UINT32 NEAR_IND_CALL:1;\r
+ UINT32 NEAR_IND_CALL : 1;\r
///\r
/// [Bit 5] NEAR_RET.\r
///\r
- UINT32 NEAR_RET:1;\r
+ UINT32 NEAR_RET : 1;\r
///\r
/// [Bit 6] NEAR_IND_JMP.\r
///\r
- UINT32 NEAR_IND_JMP:1;\r
+ UINT32 NEAR_IND_JMP : 1;\r
///\r
/// [Bit 7] NEAR_REL_JMP.\r
///\r
- UINT32 NEAR_REL_JMP:1;\r
+ UINT32 NEAR_REL_JMP : 1;\r
///\r
/// [Bit 8] FAR_BRANCH.\r
///\r
- UINT32 FAR_BRANCH:1;\r
+ UINT32 FAR_BRANCH : 1;\r
///\r
/// [Bit 9] EN_CALL_STACK.\r
///\r
- UINT32 EN_CALL_STACK:1;\r
- UINT32 Reserved1:22;\r
- UINT32 Reserved2:32;\r
+ UINT32 EN_CALL_STACK : 1;\r
+ UINT32 Reserved1 : 22;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_LBR_SELECT_REGISTER;\r
\r
-\r
/**\r
Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines\r
the interrupt response time limit used by the processor to manage transition\r
@endcode\r
@note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.\r
**/\r
-#define MSR_HASWELL_PKGC_IRTL1 0x0000060B\r
+#define MSR_HASWELL_PKGC_IRTL1 0x0000060B\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1\r
/// that should be used to decide if the package should be put into a\r
/// package C6 or C7 state.\r
///\r
- UINT32 InterruptResponseTimeLimit:10;\r
+ UINT32 InterruptResponseTimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
/// of the interrupt response time limit. See Table 2-19 for supported\r
/// time unit encodings.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_PKGC_IRTL1_REGISTER;\r
\r
-\r
/**\r
Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines\r
the interrupt response time limit used by the processor to manage transition\r
@endcode\r
@note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.\r
**/\r
-#define MSR_HASWELL_PKGC_IRTL2 0x0000060C\r
+#define MSR_HASWELL_PKGC_IRTL2 0x0000060C\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2\r
/// that should be used to decide if the package should be put into a\r
/// package C6 or C7 state.\r
///\r
- UINT32 InterruptResponseTimeLimit:10;\r
+ UINT32 InterruptResponseTimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
/// of the interrupt response time limit. See Table 2-19 for supported\r
/// time unit encodings.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_PKGC_IRTL2_REGISTER;\r
\r
-\r
/**\r
Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
\r
@endcode\r
@note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_PKG_PERF_STATUS 0x00000613\r
-\r
+#define MSR_HASWELL_PKG_PERF_STATUS 0x00000613\r
\r
/**\r
Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619\r
-\r
+#define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619\r
\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
@endcode\r
@note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B\r
-\r
+#define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B\r
\r
/**\r
Package. Base TDP Ratio (R/O).\r
@endcode\r
@note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
**/\r
-#define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648\r
+#define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL\r
/// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this\r
/// specific processor (in units of 100 MHz).\r
///\r
- UINT32 Config_TDP_Base:8;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
+ UINT32 Config_TDP_Base : 8;\r
+ UINT32 Reserved1 : 24;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Level 1 ratio and power level (R/O).\r
\r
@endcode\r
@note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649\r
+#define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1\r
///\r
/// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.\r
///\r
- UINT32 PKG_TDP_LVL1:15;\r
- UINT32 Reserved1:1;\r
+ UINT32 PKG_TDP_LVL1 : 15;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used\r
/// for this specific processor.\r
///\r
- UINT32 Config_TDP_LVL1_Ratio:8;\r
- UINT32 Reserved2:8;\r
+ UINT32 Config_TDP_LVL1_Ratio : 8;\r
+ UINT32 Reserved2 : 8;\r
///\r
/// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP\r
/// Level 1.\r
///\r
- UINT32 PKG_MAX_PWR_LVL1:15;\r
+ UINT32 PKG_MAX_PWR_LVL1 : 15;\r
///\r
/// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP\r
/// Level 1.\r
///\r
- UINT32 PKG_MIN_PWR_LVL1:16;\r
- UINT32 Reserved3:1;\r
+ UINT32 PKG_MIN_PWR_LVL1 : 16;\r
+ UINT32 Reserved3 : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Level 2 ratio and power level (R/O).\r
\r
@endcode\r
@note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A\r
+#define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2\r
///\r
/// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.\r
///\r
- UINT32 PKG_TDP_LVL2:15;\r
- UINT32 Reserved1:1;\r
+ UINT32 PKG_TDP_LVL2 : 15;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used\r
/// for this specific processor.\r
///\r
- UINT32 Config_TDP_LVL2_Ratio:8;\r
- UINT32 Reserved2:8;\r
+ UINT32 Config_TDP_LVL2_Ratio : 8;\r
+ UINT32 Reserved2 : 8;\r
///\r
/// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP\r
/// Level 2.\r
///\r
- UINT32 PKG_MAX_PWR_LVL2:15;\r
+ UINT32 PKG_MAX_PWR_LVL2 : 15;\r
///\r
/// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP\r
/// Level 2.\r
///\r
- UINT32 PKG_MIN_PWR_LVL2:16;\r
- UINT32 Reserved3:1;\r
+ UINT32 PKG_MIN_PWR_LVL2 : 16;\r
+ UINT32 Reserved3 : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Control (R/W).\r
\r
@endcode\r
@note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
**/\r
-#define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B\r
+#define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL\r
///\r
/// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.\r
///\r
- UINT32 TDP_LEVEL:2;\r
- UINT32 Reserved1:29;\r
+ UINT32 TDP_LEVEL : 2;\r
+ UINT32 Reserved1 : 29;\r
///\r
/// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of\r
/// this register is locked until a reset.\r
///\r
- UINT32 Config_TDP_Lock:1;\r
- UINT32 Reserved2:32;\r
+ UINT32 Config_TDP_Lock : 1;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Control (R/W).\r
\r
@endcode\r
@note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
**/\r
-#define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C\r
+#define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO\r
/// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r
/// field.\r
///\r
- UINT32 MAX_NON_TURBO_RATIO:8;\r
- UINT32 Reserved1:23;\r
+ UINT32 MAX_NON_TURBO_RATIO : 8;\r
+ UINT32 Reserved1 : 23;\r
///\r
/// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r
/// content of this register is locked until a reset.\r
///\r
- UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r
- UINT32 Reserved2:32;\r
+ UINT32 TURBO_ACTIVATION_RATIO_Lock : 1;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER;\r
\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
specific C-state code names, unrelated to MWAIT extension C-state parameters\r
@endcode\r
@note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
-#define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL\r
/// 0100b: C7 0101b: C7s Package C states C7 are not available to\r
/// processor with signature 06_3CH.\r
///\r
- UINT32 Limit:4;\r
- UINT32 Reserved1:6;\r
+ UINT32 Limit : 4;\r
+ UINT32 Reserved1 : 6;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO).\r
///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:9;\r
+ UINT32 CFGLock : 1;\r
+ UINT32 Reserved3 : 9;\r
///\r
/// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C3AutoDemotion:1;\r
+ UINT32 C3AutoDemotion : 1;\r
///\r
/// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C1AutoDemotion:1;\r
+ UINT32 C1AutoDemotion : 1;\r
///\r
/// [Bit 27] Enable C3 Undemotion (R/W).\r
///\r
- UINT32 C3Undemotion:1;\r
+ UINT32 C3Undemotion : 1;\r
///\r
/// [Bit 28] Enable C1 Undemotion (R/W).\r
///\r
- UINT32 C1Undemotion:1;\r
- UINT32 Reserved4:3;\r
- UINT32 Reserved5:32;\r
+ UINT32 C1Undemotion : 1;\r
+ UINT32 Reserved4 : 3;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
Enhancement. Accessible only while in SMM.\r
@endcode\r
@note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
**/\r
-#define MSR_HASWELL_SMM_MCA_CAP 0x0000017D\r
+#define MSR_HASWELL_SMM_MCA_CAP 0x0000017D\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:26;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 26;\r
///\r
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
/// SMM code access restriction is supported and the\r
/// MSR_SMM_FEATURE_CONTROL is supported.\r
///\r
- UINT32 SMM_Code_Access_Chk:1;\r
+ UINT32 SMM_Code_Access_Chk : 1;\r
///\r
/// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
/// SMM long flow indicator is supported and the MSR_SMM_DELAYED is\r
/// supported.\r
///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 Long_Flow_Indication : 1;\r
+ UINT32 Reserved3 : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_SMM_MCA_CAP_REGISTER;\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
/// limit of 1 core active.\r
///\r
- UINT32 Maximum1C:8;\r
+ UINT32 Maximum1C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
/// limit of 2 core active.\r
///\r
- UINT32 Maximum2C:8;\r
+ UINT32 Maximum2C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
/// limit of 3 core active.\r
///\r
- UINT32 Maximum3C:8;\r
+ UINT32 Maximum3C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
/// limit of 4 core active.\r
///\r
- UINT32 Maximum4C:8;\r
- UINT32 Reserved:32;\r
+ UINT32 Maximum4C : 8;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. Uncore PMU global control.\r
\r
@endcode\r
@note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391\r
+#define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL\r
///\r
/// [Bit 0] Core 0 select.\r
///\r
- UINT32 PMI_Sel_Core0:1;\r
+ UINT32 PMI_Sel_Core0 : 1;\r
///\r
/// [Bit 1] Core 1 select.\r
///\r
- UINT32 PMI_Sel_Core1:1;\r
+ UINT32 PMI_Sel_Core1 : 1;\r
///\r
/// [Bit 2] Core 2 select.\r
///\r
- UINT32 PMI_Sel_Core2:1;\r
+ UINT32 PMI_Sel_Core2 : 1;\r
///\r
/// [Bit 3] Core 3 select.\r
///\r
- UINT32 PMI_Sel_Core3:1;\r
- UINT32 Reserved1:15;\r
- UINT32 Reserved2:10;\r
+ UINT32 PMI_Sel_Core3 : 1;\r
+ UINT32 Reserved1 : 15;\r
+ UINT32 Reserved2 : 10;\r
///\r
/// [Bit 29] Enable all uncore counters.\r
///\r
- UINT32 EN:1;\r
+ UINT32 EN : 1;\r
///\r
/// [Bit 30] Enable wake on PMI.\r
///\r
- UINT32 WakePMI:1;\r
+ UINT32 WakePMI : 1;\r
///\r
/// [Bit 31] Enable Freezing counter when overflow.\r
///\r
- UINT32 FREEZE:1;\r
- UINT32 Reserved3:32;\r
+ UINT32 FREEZE : 1;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
\r
-\r
/**\r
Package. Uncore PMU main status.\r
\r
@endcode\r
@note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392\r
+#define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS\r
///\r
/// [Bit 0] Fixed counter overflowed.\r
///\r
- UINT32 Fixed:1;\r
+ UINT32 Fixed : 1;\r
///\r
/// [Bit 1] An ARB counter overflowed.\r
///\r
- UINT32 ARB:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 ARB : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 3] A CBox counter overflowed (on any slice).\r
///\r
- UINT32 CBox:1;\r
- UINT32 Reserved2:28;\r
- UINT32 Reserved3:32;\r
+ UINT32 CBox : 1;\r
+ UINT32 Reserved2 : 28;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
\r
-\r
/**\r
Package. Uncore fixed counter control (R/W).\r
\r
@endcode\r
@note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394\r
+#define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:20;\r
+ UINT32 Reserved1 : 20;\r
///\r
/// [Bit 20] Enable overflow propagation.\r
///\r
- UINT32 EnableOverflow:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 EnableOverflow : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 22] Enable counting.\r
///\r
- UINT32 EnableCounting:1;\r
- UINT32 Reserved3:9;\r
- UINT32 Reserved4:32;\r
+ UINT32 EnableCounting : 1;\r
+ UINT32 Reserved3 : 9;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER;\r
\r
-\r
/**\r
Package. Uncore fixed counter.\r
\r
@endcode\r
@note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395\r
+#define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR\r
///\r
/// [Bits 31:0] Current count.\r
///\r
- UINT32 CurrentCount:32;\r
+ UINT32 CurrentCount : 32;\r
///\r
/// [Bits 47:32] Current count.\r
///\r
- UINT32 CurrentCountHi:16;\r
- UINT32 Reserved:16;\r
+ UINT32 CurrentCountHi : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER;\r
\r
-\r
/**\r
Package. Uncore C-Box configuration information (R/O).\r
\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396\r
+#define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG\r
///\r
/// [Bits 3:0] Encoded number of C-Box, derive value by "-1".\r
///\r
- UINT32 CBox:4;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
+ UINT32 CBox : 4;\r
+ UINT32 Reserved1 : 28;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_UNC_CBO_CONFIG_REGISTER;\r
\r
-\r
/**\r
Package. Uncore Arb unit, performance counter 0.\r
\r
@endcode\r
@note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0\r
-\r
+#define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0\r
\r
/**\r
Package. Uncore Arb unit, performance counter 1.\r
@endcode\r
@note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1\r
-\r
+#define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1\r
\r
/**\r
Package. Uncore Arb unit, counter 0 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2\r
-\r
+#define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2\r
\r
/**\r
Package. Uncore Arb unit, counter 1 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3\r
-\r
+#define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3\r
\r
/**\r
Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability\r
@endcode\r
@note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0\r
+#define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL\r
/// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from\r
/// further changes.\r
///\r
- UINT32 Lock:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 Lock : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if\r
/// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the\r
/// the package that attempts to execute SMM code not within the ranges\r
/// defined by the SMRR will assert an unrecoverable MCE.\r
///\r
- UINT32 SMM_Code_Chk_En:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
+ UINT32 SMM_Code_Chk_En : 1;\r
+ UINT32 Reserved2 : 29;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical\r
processors in the package. Available only while in SMM and\r
@endcode\r
@note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.\r
**/\r
-#define MSR_HASWELL_SMM_DELAYED 0x000004E2\r
-\r
+#define MSR_HASWELL_SMM_DELAYED 0x000004E2\r
\r
/**\r
Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical\r
@endcode\r
@note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.\r
**/\r
-#define MSR_HASWELL_SMM_BLOCKED 0x000004E3\r
-\r
+#define MSR_HASWELL_SMM_BLOCKED 0x000004E3\r
\r
/**\r
Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
@endcode\r
@note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
-#define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606\r
+#define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT\r
///\r
/// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
+ UINT32 PowerUnits : 4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 12:8] Package. Energy Status Units Energy related information\r
/// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
/// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
/// micro-joules).\r
///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
+ UINT32 EnergyStatusUnits : 5;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
/// Interfaces.".\r
///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
+ UINT32 TimeUnits : 4;\r
+ UINT32 Reserved3 : 12;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_RAPL_POWER_UNIT_REGISTER;\r
\r
-\r
/**\r
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
Domains.".\r
@endcode\r
@note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
@endcode\r
@note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640\r
-\r
+#define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640\r
\r
/**\r
Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641\r
-\r
+#define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641\r
\r
/**\r
Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.\r
**/\r
-#define MSR_HASWELL_PP1_POLICY 0x00000642\r
-\r
+#define MSR_HASWELL_PP1_POLICY 0x00000642\r
\r
/**\r
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
@endcode\r
@note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
**/\r
-#define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690\r
+#define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS\r
/// reduced below the operating system request due to assertion of\r
/// external PROCHOT.\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
/// operating system request due to a thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 ThermalStatus : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced\r
/// below the operating system request due to Processor Graphics driver\r
/// override.\r
///\r
- UINT32 GraphicsDriverStatus:1;\r
+ UINT32 GraphicsDriverStatus : 1;\r
///\r
/// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
/// When set, frequency is reduced below the operating system request\r
/// because the processor has detected that utilization is low.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlStatus : 1;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
/// below the operating system request due to a thermal alert from the\r
/// Voltage Regulator.\r
///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
/// reduced below the operating system request due to electrical design\r
/// point constraints (e.g. maximum electrical current consumption).\r
///\r
- UINT32 ElectricalDesignPointStatus:1;\r
+ UINT32 ElectricalDesignPointStatus : 1;\r
///\r
/// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced\r
/// below the operating system request due to domain-level power limiting.\r
///\r
- UINT32 PLStatus:1;\r
+ UINT32 PLStatus : 1;\r
///\r
/// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL1.\r
///\r
- UINT32 PL1Status:1;\r
+ UINT32 PL1Status : 1;\r
///\r
/// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL2.\r
///\r
- UINT32 PL2Status:1;\r
+ UINT32 PL2Status : 1;\r
///\r
/// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced\r
/// below the operating system request due to multi-core turbo limits.\r
///\r
- UINT32 MaxTurboLimitStatus:1;\r
+ UINT32 MaxTurboLimitStatus : 1;\r
///\r
/// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
/// is reduced below the operating system request due to Turbo transition\r
/// attenuation. This prevents performance degradation due to frequent\r
/// operating ratio changes.\r
///\r
- UINT32 TurboTransitionAttenuationStatus:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 TurboTransitionAttenuationStatus : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved4:2;\r
+ UINT32 ThermalLog : 1;\r
+ UINT32 Reserved4 : 2;\r
///\r
/// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r
/// Driver Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 GraphicsDriverLog:1;\r
+ UINT32 GraphicsDriverLog : 1;\r
///\r
/// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
/// indicates that the Autonomous Utilization-Based Frequency Control\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog : 1;\r
///\r
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 VRThermAlertLog : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 ElectricalDesignPointLog:1;\r
+ UINT32 ElectricalDesignPointLog : 1;\r
///\r
/// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
/// Power Limiting Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 PLLog:1;\r
+ UINT32 PLLog : 1;\r
///\r
/// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r
/// that the Package Level PL1 Power Limiting Status bit has asserted\r
/// since the log bit was last cleared. This log bit will remain set until\r
/// cleared by software writing 0.\r
///\r
- UINT32 PL1Log:1;\r
+ UINT32 PL1Log : 1;\r
///\r
/// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r
/// the Package Level PL2 Power Limiting Status bit has asserted since the\r
/// log bit was last cleared. This log bit will remain set until cleared\r
/// by software writing 0.\r
///\r
- UINT32 PL2Log:1;\r
+ UINT32 PL2Log : 1;\r
///\r
/// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
/// Limit Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 MaxTurboLimitLog:1;\r
+ UINT32 MaxTurboLimitLog : 1;\r
///\r
/// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
/// Turbo Transition Attenuation Status bit has asserted since the log bit\r
/// was last cleared. This log bit will remain set until cleared by\r
/// software writing 0.\r
///\r
- UINT32 TurboTransitionAttenuationLog:1;\r
- UINT32 Reserved6:2;\r
- UINT32 Reserved7:32;\r
+ UINT32 TurboTransitionAttenuationLog : 1;\r
+ UINT32 Reserved6 : 2;\r
+ UINT32 Reserved7 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)\r
(frequency refers to processor graphics frequency).\r
/// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
/// operating system request due to assertion of external PROCHOT.\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
/// operating system request due to a thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 ThermalStatus : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced\r
/// below the operating system request due to Processor Graphics driver\r
/// override.\r
///\r
- UINT32 GraphicsDriverStatus:1;\r
+ UINT32 GraphicsDriverStatus : 1;\r
///\r
/// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
/// When set, frequency is reduced below the operating system request\r
/// because the processor has detected that utilization is low.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlStatus : 1;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
/// below the operating system request due to a thermal alert from the\r
/// Voltage Regulator.\r
///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
/// reduced below the operating system request due to electrical design\r
/// point constraints (e.g. maximum electrical current consumption).\r
///\r
- UINT32 ElectricalDesignPointStatus:1;\r
+ UINT32 ElectricalDesignPointStatus : 1;\r
///\r
/// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is\r
/// reduced below the operating system request due to domain-level power\r
/// limiting.\r
///\r
- UINT32 GraphicsPowerLimitingStatus:1;\r
+ UINT32 GraphicsPowerLimitingStatus : 1;\r
///\r
/// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL1.\r
///\r
- UINT32 PL1STatus:1;\r
+ UINT32 PL1STatus : 1;\r
///\r
/// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL2.\r
///\r
- UINT32 PL2Status:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 PL2Status : 1;\r
+ UINT32 Reserved3 : 4;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved4:2;\r
+ UINT32 ThermalLog : 1;\r
+ UINT32 Reserved4 : 2;\r
///\r
/// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r
/// Driver Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 GraphicsDriverLog:1;\r
+ UINT32 GraphicsDriverLog : 1;\r
///\r
/// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
/// indicates that the Autonomous Utilization-Based Frequency Control\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog : 1;\r
///\r
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 VRThermAlertLog : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 ElectricalDesignPointLog:1;\r
+ UINT32 ElectricalDesignPointLog : 1;\r
///\r
/// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
/// Power Limiting Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 CorePowerLimitingLog:1;\r
+ UINT32 CorePowerLimitingLog : 1;\r
///\r
/// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r
/// that the Package Level PL1 Power Limiting Status bit has asserted\r
/// since the log bit was last cleared. This log bit will remain set until\r
/// cleared by software writing 0.\r
///\r
- UINT32 PL1Log:1;\r
+ UINT32 PL1Log : 1;\r
///\r
/// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r
/// the Package Level PL2 Power Limiting Status bit has asserted since the\r
/// log bit was last cleared. This log bit will remain set until cleared\r
/// by software writing 0.\r
///\r
- UINT32 PL2Log:1;\r
+ UINT32 PL2Log : 1;\r
///\r
/// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
/// Limit Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 MaxTurboLimitLog:1;\r
+ UINT32 MaxTurboLimitLog : 1;\r
///\r
/// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
/// Turbo Transition Attenuation Status bit has asserted since the log bit\r
/// was last cleared. This log bit will remain set until cleared by\r
/// software writing 0.\r
///\r
- UINT32 TurboTransitionAttenuationLog:1;\r
- UINT32 Reserved6:2;\r
- UINT32 Reserved7:32;\r
+ UINT32 TurboTransitionAttenuationLog : 1;\r
+ UINT32 Reserved6 : 2;\r
+ UINT32 Reserved7 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)\r
(frequency refers to ring interconnect in the uncore).\r
@endcode\r
@note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.\r
**/\r
-#define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1\r
+#define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS\r
/// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
/// operating system request due to assertion of external PROCHOT.\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
/// operating system request due to a thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 ThermalStatus : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
/// below the operating system request due to a thermal alert from the\r
/// Voltage Regulator.\r
///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
/// reduced below the operating system request due to electrical design\r
/// point constraints (e.g. maximum electrical current consumption).\r
///\r
- UINT32 ElectricalDesignPointStatus:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 ElectricalDesignPointStatus : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL1.\r
///\r
- UINT32 PL1STatus:1;\r
+ UINT32 PL1STatus : 1;\r
///\r
/// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL2.\r
///\r
- UINT32 PL2Status:1;\r
- UINT32 Reserved4:4;\r
+ UINT32 PL2Status : 1;\r
+ UINT32 Reserved4 : 4;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved5:2;\r
+ UINT32 ThermalLog : 1;\r
+ UINT32 Reserved5 : 2;\r
///\r
/// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r
/// Driver Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 GraphicsDriverLog:1;\r
+ UINT32 GraphicsDriverLog : 1;\r
///\r
/// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
/// indicates that the Autonomous Utilization-Based Frequency Control\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog : 1;\r
///\r
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 VRThermAlertLog : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 ElectricalDesignPointLog:1;\r
+ UINT32 ElectricalDesignPointLog : 1;\r
///\r
/// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
/// Power Limiting Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 CorePowerLimitingLog:1;\r
+ UINT32 CorePowerLimitingLog : 1;\r
///\r
/// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r
/// that the Package Level PL1 Power Limiting Status bit has asserted\r
/// since the log bit was last cleared. This log bit will remain set until\r
/// cleared by software writing 0.\r
///\r
- UINT32 PL1Log:1;\r
+ UINT32 PL1Log : 1;\r
///\r
/// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r
/// the Package Level PL2 Power Limiting Status bit has asserted since the\r
/// log bit was last cleared. This log bit will remain set until cleared\r
/// by software writing 0.\r
///\r
- UINT32 PL2Log:1;\r
+ UINT32 PL2Log : 1;\r
///\r
/// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
/// Limit Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 MaxTurboLimitLog:1;\r
+ UINT32 MaxTurboLimitLog : 1;\r
///\r
/// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
/// Turbo Transition Attenuation Status bit has asserted since the log bit\r
/// was last cleared. This log bit will remain set until cleared by\r
/// software writing 0.\r
///\r
- UINT32 TurboTransitionAttenuationLog:1;\r
- UINT32 Reserved7:2;\r
- UINT32 Reserved8:32;\r
+ UINT32 TurboTransitionAttenuationLog : 1;\r
+ UINT32 Reserved7 : 2;\r
+ UINT32 Reserved8 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
Package. Uncore C-Box 0, counter 0 event select MSR.\r
\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
-\r
+#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
\r
/**\r
Package. Uncore C-Box 0, counter 1 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
-\r
+#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
\r
/**\r
Package. Uncore C-Box 0, performance counter 0.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706\r
-\r
+#define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706\r
\r
/**\r
Package. Uncore C-Box 0, performance counter 1.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707\r
-\r
+#define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707\r
\r
/**\r
Package. Uncore C-Box 1, counter 0 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
-\r
+#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
\r
/**\r
Package. Uncore C-Box 1, counter 1 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
-\r
+#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
\r
/**\r
Package. Uncore C-Box 1, performance counter 0.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716\r
-\r
+#define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716\r
\r
/**\r
Package. Uncore C-Box 1, performance counter 1.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717\r
-\r
+#define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717\r
\r
/**\r
Package. Uncore C-Box 2, counter 0 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
-\r
+#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
\r
/**\r
Package. Uncore C-Box 2, counter 1 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
-\r
+#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
\r
/**\r
Package. Uncore C-Box 2, performance counter 0.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726\r
-\r
+#define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726\r
\r
/**\r
Package. Uncore C-Box 2, performance counter 1.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727\r
-\r
+#define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727\r
\r
/**\r
Package. Uncore C-Box 3, counter 0 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
-\r
+#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
\r
/**\r
Package. Uncore C-Box 3, counter 1 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
-\r
+#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
\r
/**\r
Package. Uncore C-Box 3, performance counter 0.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736\r
-\r
+#define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736\r
\r
/**\r
Package. Uncore C-Box 3, performance counter 1.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737\r
-\r
+#define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737\r
\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.\r
**/\r
-#define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630\r
+#define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY\r
/// that this package is in processor-specific C8 states. Count at the\r
/// same frequency as the TSC.\r
///\r
- UINT32 C8ResidencyCounter:32;\r
+ UINT32 C8ResidencyCounter : 32;\r
///\r
/// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last\r
/// reset that this package is in processor-specific C8 states. Count at\r
/// the same frequency as the TSC.\r
///\r
- UINT32 C8ResidencyCounterHi:28;\r
- UINT32 Reserved:4;\r
+ UINT32 C8ResidencyCounterHi : 28;\r
+ UINT32 Reserved : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
@endcode\r
@note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.\r
**/\r
-#define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631\r
+#define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY\r
/// that this package is in processor-specific C9 states. Count at the\r
/// same frequency as the TSC.\r
///\r
- UINT32 C9ResidencyCounter:32;\r
+ UINT32 C9ResidencyCounter : 32;\r
///\r
/// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last\r
/// reset that this package is in processor-specific C9 states. Count at\r
/// the same frequency as the TSC.\r
///\r
- UINT32 C9ResidencyCounterHi:28;\r
- UINT32 Reserved:4;\r
+ UINT32 C9ResidencyCounterHi : 28;\r
+ UINT32 Reserved : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
@endcode\r
@note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.\r
**/\r
-#define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632\r
+#define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY\r
/// reset that this package is in processor-specific C10 states. Count at\r
/// the same frequency as the TSC.\r
///\r
- UINT32 C10ResidencyCounter:32;\r
+ UINT32 C10ResidencyCounter : 32;\r
///\r
/// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last\r
/// reset that this package is in processor-specific C10 states. Count at\r
/// the same frequency as the TSC.\r
///\r
- UINT32 C10ResidencyCounterHi:28;\r
- UINT32 Reserved:4;\r
+ UINT32 C10ResidencyCounterHi : 28;\r
+ UINT32 Reserved : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER;\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff