@endcode\r
@note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE\r
+#define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
/// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
/// MHz.\r
///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
+ UINT32 MaximumNonTurboRatio : 8;\r
+ UINT32 Reserved2 : 12;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
/// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
/// Turbo mode is disabled.\r
///\r
- UINT32 RatioLimit:1;\r
+ UINT32 RatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
/// and when set to 0, indicates TDP Limit for Turbo mode is not\r
/// programmable.\r
///\r
- UINT32 TDPLimit:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 TDPLimit : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,\r
/// indicates that LPM is supported, and when set to 0, indicates LPM is\r
/// not supported.\r
///\r
- UINT32 LowPowerModeSupport:1;\r
+ UINT32 LowPowerModeSupport : 1;\r
///\r
/// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base\r
/// TDP level available. 01: One additional TDP level available. 02: Two\r
/// additional TDP level available. 11: Reserved.\r
///\r
- UINT32 ConfigTDPLevels:2;\r
- UINT32 Reserved4:5;\r
+ UINT32 ConfigTDPLevels : 2;\r
+ UINT32 Reserved4 : 5;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
/// minimum ratio (maximum efficiency) that the processor can operates, in\r
/// units of 100MHz.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
///\r
/// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the\r
/// minimum supported operating ratio in units of 100 MHz.\r
///\r
- UINT32 MinimumOperatingRatio:8;\r
- UINT32 Reserved5:8;\r
+ UINT32 MinimumOperatingRatio : 8;\r
+ UINT32 Reserved5 : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;\r
\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are\r
processor specific C-state code names, unrelated to MWAIT extension C-state\r
@endcode\r
@note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL\r
/// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:\r
/// This field cannot be used to limit package C-state to C3.\r
///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 Limit : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
/// IO_read instructions sent to IO register specified by\r
/// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
/// until next reset.\r
///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:9;\r
+ UINT32 CFGLock : 1;\r
+ UINT32 Reserved3 : 9;\r
///\r
/// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
/// will conditionally demote C6/C7 requests to C3 based on uncore\r
/// auto-demote information.\r
///\r
- UINT32 C3AutoDemotion:1;\r
+ UINT32 C3AutoDemotion : 1;\r
///\r
/// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
/// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
/// auto-demote information.\r
///\r
- UINT32 C1AutoDemotion:1;\r
+ UINT32 C1AutoDemotion : 1;\r
///\r
/// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from\r
/// demoted C3.\r
///\r
- UINT32 C3Undemotion:1;\r
+ UINT32 C3Undemotion : 1;\r
///\r
/// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from\r
/// demoted C1.\r
///\r
- UINT32 C1Undemotion:1;\r
- UINT32 Reserved4:3;\r
- UINT32 Reserved5:32;\r
+ UINT32 C1Undemotion : 1;\r
+ UINT32 Reserved4 : 3;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
Domains.".\r
@endcode\r
@note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Package. Base TDP Ratio (R/O).\r
@endcode\r
@note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL\r
/// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this\r
/// specific processor (in units of 100 MHz).\r
///\r
- UINT32 Config_TDP_Base:8;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
+ UINT32 Config_TDP_Base : 8;\r
+ UINT32 Reserved1 : 24;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Level 1 ratio and power level (R/O).\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1\r
///\r
/// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.\r
///\r
- UINT32 PKG_TDP_LVL1:15;\r
- UINT32 Reserved1:1;\r
+ UINT32 PKG_TDP_LVL1 : 15;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used\r
/// for this specific processor.\r
///\r
- UINT32 Config_TDP_LVL1_Ratio:8;\r
- UINT32 Reserved2:8;\r
+ UINT32 Config_TDP_LVL1_Ratio : 8;\r
+ UINT32 Reserved2 : 8;\r
///\r
/// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP\r
/// Level 1.\r
///\r
- UINT32 PKG_MAX_PWR_LVL1:15;\r
- UINT32 Reserved3:1;\r
+ UINT32 PKG_MAX_PWR_LVL1 : 15;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP\r
/// Level 1.\r
///\r
- UINT32 PKG_MIN_PWR_LVL1:15;\r
- UINT32 Reserved4:1;\r
+ UINT32 PKG_MIN_PWR_LVL1 : 15;\r
+ UINT32 Reserved4 : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Level 2 ratio and power level (R/O).\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2\r
///\r
/// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.\r
///\r
- UINT32 PKG_TDP_LVL2:15;\r
- UINT32 Reserved1:1;\r
+ UINT32 PKG_TDP_LVL2 : 15;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used\r
/// for this specific processor.\r
///\r
- UINT32 Config_TDP_LVL2_Ratio:8;\r
- UINT32 Reserved2:8;\r
+ UINT32 Config_TDP_LVL2_Ratio : 8;\r
+ UINT32 Reserved2 : 8;\r
///\r
/// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP\r
/// Level 2.\r
///\r
- UINT32 PKG_MAX_PWR_LVL2:15;\r
- UINT32 Reserved3:1;\r
+ UINT32 PKG_MAX_PWR_LVL2 : 15;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP\r
/// Level 2.\r
///\r
- UINT32 PKG_MIN_PWR_LVL2:15;\r
- UINT32 Reserved4:1;\r
+ UINT32 PKG_MIN_PWR_LVL2 : 15;\r
+ UINT32 Reserved4 : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Control (R/W).\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL\r
///\r
/// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.\r
///\r
- UINT32 TDP_LEVEL:2;\r
- UINT32 Reserved1:29;\r
+ UINT32 TDP_LEVEL : 2;\r
+ UINT32 Reserved1 : 29;\r
///\r
/// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of\r
/// this register is locked until a reset.\r
///\r
- UINT32 Config_TDP_Lock:1;\r
- UINT32 Reserved2:32;\r
+ UINT32 Config_TDP_Lock : 1;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Control (R/W).\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C\r
+#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO\r
/// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r
/// field.\r
///\r
- UINT32 MAX_NON_TURBO_RATIO:8;\r
- UINT32 Reserved1:23;\r
+ UINT32 MAX_NON_TURBO_RATIO : 8;\r
+ UINT32 Reserved1 : 23;\r
///\r
/// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r
/// content of this register is locked until a reset.\r
///\r
- UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r
- UINT32 Reserved2:32;\r
+ UINT32 TURBO_ACTIVATION_RATIO_Lock : 1;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER;\r
\r
-\r
/**\r
Package. Protected Processor Inventory Number Enable Control (R/W).\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E\r
+#define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL\r
/// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r
/// prevent unauthorized modification to MSR_PPIN_CTL.\r
///\r
- UINT32 LockOut:1;\r
+ UINT32 LockOut : 1;\r
///\r
/// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r
/// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will\r
/// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default\r
/// is 0.\r
///\r
- UINT32 Enable_PPIN:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 Enable_PPIN : 1;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_PPIN_CTL_REGISTER;\r
\r
-\r
/**\r
Package. Protected Processor Inventory Number (R/O). Protected Processor\r
Inventory Number (R/O) A unique value within a given CPUID\r
@endcode\r
@note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PPIN 0x0000004F\r
-\r
+#define MSR_IVY_BRIDGE_PPIN 0x0000004F\r
\r
/**\r
Package. See http://biosbits.org.\r
@endcode\r
@note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE\r
+#define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
/// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
/// MHz.\r
///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:7;\r
+ UINT32 MaximumNonTurboRatio : 8;\r
+ UINT32 Reserved2 : 7;\r
///\r
/// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that\r
/// Protected Processor Inventory Number (PPIN) capability can be enabled\r
/// set to 0, PPIN capability is not supported. An attempt to access\r
/// MSR_PPIN_CTL or MSR_PPIN will cause #GP.\r
///\r
- UINT32 PPIN_CAP:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 PPIN_CAP : 1;\r
+ UINT32 Reserved3 : 4;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
/// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
/// Turbo mode is disabled.\r
///\r
- UINT32 RatioLimit:1;\r
+ UINT32 RatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
/// and when set to 0, indicates TDP Limit for Turbo mode is not\r
/// programmable.\r
///\r
- UINT32 TDPLimit:1;\r
+ UINT32 TDPLimit : 1;\r
///\r
/// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,\r
/// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to\r
/// specify an temperature offset.\r
///\r
- UINT32 TJOFFSET:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:8;\r
+ UINT32 TJOFFSET : 1;\r
+ UINT32 Reserved4 : 1;\r
+ UINT32 Reserved5 : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
/// minimum ratio (maximum efficiency) that the processor can operates, in\r
/// units of 100MHz.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved6:16;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
+ UINT32 Reserved6 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER;\r
\r
-\r
/**\r
Package. MC Bank Error Configuration (R/W).\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F\r
+#define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
/// to log additional info in bits 36:32.\r
///\r
- UINT32 MemErrorLogEnable:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
+ UINT32 MemErrorLogEnable : 1;\r
+ UINT32 Reserved2 : 30;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package.\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
+#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bits 23:16] Temperature Target (RO) The minimum temperature at which\r
/// PROCHOT# will be asserted. The value is degree C.\r
///\r
- UINT32 TemperatureTarget:8;\r
+ UINT32 TemperatureTarget : 8;\r
///\r
/// [Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature\r
/// offset in degrees C from the temperature target (bits 23:16). PROCHOT#\r
/// will assert at the offset target temperature. Write is permitted only\r
/// MSR_PLATFORM_INFO.[30] is set.\r
///\r
- UINT32 TCCActivationOffset:4;\r
- UINT32 Reserved2:4;\r
- UINT32 Reserved3:32;\r
+ UINT32 TCCActivationOffset : 4;\r
+ UINT32 Reserved2 : 4;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER;\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE\r
+#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r
/// limit of 9 core active.\r
///\r
- UINT32 Maximum9C:8;\r
+ UINT32 Maximum9C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r
/// limit of 10core active.\r
///\r
- UINT32 Maximum10C:8;\r
+ UINT32 Maximum10C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r
/// limit of 11 core active.\r
///\r
- UINT32 Maximum11C:8;\r
+ UINT32 Maximum11C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r
/// limit of 12 core active.\r
///\r
- UINT32 Maximum12C:8;\r
+ UINT32 Maximum12C : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r
/// limit of 13 core active.\r
///\r
- UINT32 Maximum13C:8;\r
+ UINT32 Maximum13C : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r
/// limit of 14 core active.\r
///\r
- UINT32 Maximum14C:8;\r
+ UINT32 Maximum14C : 8;\r
///\r
/// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r
/// limit of 15 core active.\r
///\r
- UINT32 Maximum15C:8;\r
- UINT32 Reserved:7;\r
+ UINT32 Maximum15C : 8;\r
+ UINT32 Reserved : 7;\r
///\r
/// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
/// the processor uses override configuration specified in\r
/// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r
/// uses factory-set configuration (Default).\r
///\r
- UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
+ UINT32 TurboRatioLimitConfigurationSemaphore : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER;\r
\r
-\r
/**\r
Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B\r
+#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC\r
///\r
/// [Bits 5:0] Recoverable Address LSB.\r
///\r
- UINT32 RecoverableAddressLSB:6;\r
+ UINT32 RecoverableAddressLSB : 6;\r
///\r
/// [Bits 8:6] Address Mode.\r
///\r
- UINT32 AddressMode:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 AddressMode : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bits 31:16] PCI Express Requestor ID.\r
///\r
- UINT32 PCIExpressRequestorID:16;\r
+ UINT32 PCIExpressRequestorID : 16;\r
///\r
/// [Bits 39:32] PCI Express Segment Number.\r
///\r
- UINT32 PCIExpressSegmentNumber:8;\r
- UINT32 Reserved2:24;\r
+ UINT32 PCIExpressSegmentNumber : 8;\r
+ UINT32 Reserved2 : 24;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;\r
\r
-\r
/**\r
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
15.3.2.4, "IA32_MCi_MISC MSRs.".\r
MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.\r
@{\r
**/\r
-#define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474\r
-#define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478\r
-#define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C\r
+#define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474\r
+#define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478\r
+#define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C\r
/// @}\r
\r
-\r
/**\r
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
15.3.2.4, "IA32_MCi_MISC MSRs.".\r
MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.\r
@{\r
**/\r
-#define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475\r
-#define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479\r
-#define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D\r
+#define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475\r
+#define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479\r
+#define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D\r
/// @}\r
\r
-\r
/**\r
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
15.3.2.4, "IA32_MCi_MISC MSRs.".\r
MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.\r
@{\r
**/\r
-#define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476\r
-#define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A\r
-#define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E\r
+#define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476\r
+#define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A\r
+#define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E\r
/// @}\r
\r
-\r
/**\r
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
15.3.2.4, "IA32_MCi_MISC MSRs.".\r
MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.\r
@{\r
**/\r
-#define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477\r
-#define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B\r
-#define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F\r
+#define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477\r
+#define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B\r
+#define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F\r
/// @}\r
\r
-\r
/**\r
Package. Package RAPL Perf Status (R/O).\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
-\r
+#define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
\r
/**\r
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
@endcode\r
@note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
-\r
+#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
\r
/**\r
Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
-\r
+#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
@endcode\r
@note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
-\r
+#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
\r
/**\r
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
-\r
+#define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
\r
/**\r
Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r
@endcode\r
@note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1\r
+#define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE\r
///\r
/// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC0:1;\r
+ UINT32 PEBS_EN_PMC0 : 1;\r
///\r
/// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC1:1;\r
+ UINT32 PEBS_EN_PMC1 : 1;\r
///\r
/// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC2:1;\r
+ UINT32 PEBS_EN_PMC2 : 1;\r
///\r
/// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC3:1;\r
- UINT32 Reserved1:28;\r
+ UINT32 PEBS_EN_PMC3 : 1;\r
+ UINT32 Reserved1 : 28;\r
///\r
/// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
///\r
- UINT32 LL_EN_PMC0:1;\r
+ UINT32 LL_EN_PMC0 : 1;\r
///\r
/// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
///\r
- UINT32 LL_EN_PMC1:1;\r
+ UINT32 LL_EN_PMC1 : 1;\r
///\r
/// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
///\r
- UINT32 LL_EN_PMC2:1;\r
+ UINT32 LL_EN_PMC2 : 1;\r
///\r
/// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
///\r
- UINT32 LL_EN_PMC3:1;\r
- UINT32 Reserved2:28;\r
+ UINT32 LL_EN_PMC3 : 1;\r
+ UINT32 Reserved2 : 28;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
Package. Uncore perfmon per-socket global control.\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00\r
-\r
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00\r
\r
/**\r
Package. Uncore perfmon per-socket global status.\r
@endcode\r
@note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01\r
-\r
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01\r
\r
/**\r
Package. Uncore perfmon per-socket global configuration.\r
@endcode\r
@note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06\r
-\r
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06\r
\r
/**\r
Package. Uncore U-box perfmon U-box wide status.\r
@endcode\r
@note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15\r
-\r
+#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15\r
\r
/**\r
Package. Uncore PCU perfmon box wide status.\r
@endcode\r
@note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35\r
-\r
+#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35\r
\r
/**\r
Package. Uncore C-box 0 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A\r
-\r
+#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A\r
\r
/**\r
Package. Uncore C-box 1 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A\r
-\r
+#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A\r
\r
/**\r
Package. Uncore C-box 2 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A\r
-\r
+#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A\r
\r
/**\r
Package. Uncore C-box 3 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A\r
-\r
+#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A\r
\r
/**\r
Package. Uncore C-box 4 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A\r
-\r
+#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A\r
\r
/**\r
Package. Uncore C-box 5 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA\r
-\r
+#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA\r
\r
/**\r
Package. Uncore C-box 6 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA\r
-\r
+#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA\r
\r
/**\r
Package. Uncore C-box 7 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA\r
-\r
+#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA\r
\r
/**\r
Package. Uncore C-box 8 perfmon local box wide control.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04\r
\r
/**\r
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10\r
\r
/**\r
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11\r
\r
/**\r
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12\r
\r
/**\r
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13\r
\r
/**\r
Package. Uncore C-box 8 perfmon box wide filter.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14\r
\r
/**\r
Package. Uncore C-box 8 perfmon counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16\r
\r
/**\r
Package. Uncore C-box 8 perfmon counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17\r
\r
/**\r
Package. Uncore C-box 8 perfmon counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18\r
\r
/**\r
Package. Uncore C-box 8 perfmon counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19\r
\r
/**\r
Package. Uncore C-box 8 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A\r
\r
/**\r
Package. Uncore C-box 9 perfmon local box wide control.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24\r
\r
/**\r
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30\r
\r
/**\r
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31\r
\r
/**\r
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32\r
\r
/**\r
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33\r
\r
/**\r
Package. Uncore C-box 9 perfmon box wide filter.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34\r
\r
/**\r
Package. Uncore C-box 9 perfmon counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36\r
\r
/**\r
Package. Uncore C-box 9 perfmon counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37\r
\r
/**\r
Package. Uncore C-box 9 perfmon counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38\r
\r
/**\r
Package. Uncore C-box 9 perfmon counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39\r
\r
/**\r
Package. Uncore C-box 9 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A\r
\r
/**\r
Package. Uncore C-box 10 perfmon local box wide control.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44\r
\r
/**\r
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50\r
\r
/**\r
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51\r
\r
/**\r
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52\r
\r
/**\r
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53\r
\r
/**\r
Package. Uncore C-box 10 perfmon box wide filter.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54\r
\r
/**\r
Package. Uncore C-box 10 perfmon counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56\r
\r
/**\r
Package. Uncore C-box 10 perfmon counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57\r
\r
/**\r
Package. Uncore C-box 10 perfmon counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58\r
\r
/**\r
Package. Uncore C-box 10 perfmon counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59\r
\r
/**\r
Package. Uncore C-box 10 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A\r
\r
/**\r
Package. Uncore C-box 11 perfmon local box wide control.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64\r
\r
/**\r
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70\r
\r
/**\r
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71\r
\r
/**\r
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72\r
\r
/**\r
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73\r
\r
/**\r
Package. Uncore C-box 11 perfmon box wide filter.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74\r
\r
/**\r
Package. Uncore C-box 11 perfmon counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76\r
\r
/**\r
Package. Uncore C-box 11 perfmon counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77\r
\r
/**\r
Package. Uncore C-box 11 perfmon counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78\r
\r
/**\r
Package. Uncore C-box 11 perfmon counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79\r
\r
/**\r
Package. Uncore C-box 11 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A\r
\r
/**\r
Package. Uncore C-box 12 perfmon local box wide control.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84\r
\r
/**\r
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90\r
\r
/**\r
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91\r
\r
/**\r
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92\r
\r
/**\r
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93\r
\r
/**\r
Package. Uncore C-box 12 perfmon box wide filter.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94\r
\r
/**\r
Package. Uncore C-box 12 perfmon counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96\r
\r
/**\r
Package. Uncore C-box 12 perfmon counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97\r
\r
/**\r
Package. Uncore C-box 12 perfmon counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98\r
\r
/**\r
Package. Uncore C-box 12 perfmon counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99\r
\r
/**\r
Package. Uncore C-box 12 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A\r
\r
/**\r
Package. Uncore C-box 13 perfmon local box wide control.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4\r
\r
/**\r
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0\r
\r
/**\r
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1\r
\r
/**\r
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2\r
\r
/**\r
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3\r
\r
/**\r
Package. Uncore C-box 13 perfmon box wide filter.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4\r
\r
/**\r
Package. Uncore C-box 13 perfmon counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6\r
\r
/**\r
Package. Uncore C-box 13 perfmon counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7\r
\r
/**\r
Package. Uncore C-box 13 perfmon counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8\r
\r
/**\r
Package. Uncore C-box 13 perfmon counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9\r
\r
/**\r
Package. Uncore C-box 13 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA\r
\r
/**\r
Package. Uncore C-box 14 perfmon local box wide control.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4\r
\r
/**\r
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0\r
\r
/**\r
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1\r
\r
/**\r
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2\r
\r
/**\r
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3\r
\r
/**\r
Package. Uncore C-box 14 perfmon box wide filter.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4\r
\r
/**\r
Package. Uncore C-box 14 perfmon counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6\r
\r
/**\r
Package. Uncore C-box 14 perfmon counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7\r
\r
/**\r
Package. Uncore C-box 14 perfmon counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8\r
\r
/**\r
Package. Uncore C-box 14 perfmon counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9\r
\r
/**\r
Package. Uncore C-box 14 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA\r
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff