@endcode\r
@note MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE is defined as IA32_MONITOR_FILTER_LINE_SIZE in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006\r
-\r
+#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W)\r
@endcode\r
@note MSR_PENTIUM_4_EBC_HARD_POWERON is defined as MSR_EBC_HARD_POWERON in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A\r
+#define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON\r
/// The value in this bit is written on the deassertion of RESET#; the bit\r
/// is set to 1 when the address bus signal is asserted.\r
///\r
- UINT32 OutputTriStateEnabled:1;\r
+ UINT32 OutputTriStateEnabled : 1;\r
///\r
/// [Bit 1] Execute BIST (R) Indicates whether the execution of the BIST\r
/// is enabled (1) or disabled (0) as set by the strapping of INIT#. The\r
/// value in this bit is written on the deassertion of RESET#; the bit is\r
/// set to 1 when the address bus signal is asserted.\r
///\r
- UINT32 ExecuteBIST:1;\r
+ UINT32 ExecuteBIST : 1;\r
///\r
/// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue\r
/// depth for the system bus is 1 (1) or up to 12 (0) as set by the\r
/// strapping of A7#. The value in this bit is written on the deassertion\r
/// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
///\r
- UINT32 InOrderQueueDepth:1;\r
+ UINT32 InOrderQueueDepth : 1;\r
///\r
/// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR#\r
/// observation is enabled (0) or disabled (1) as determined by the\r
/// strapping of A9#. The value in this bit is written on the deassertion\r
/// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
///\r
- UINT32 MCERR_ObservationDisabled:1;\r
+ UINT32 MCERR_ObservationDisabled : 1;\r
///\r
/// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT#\r
/// observation is enabled (0) or disabled (1) as determined by the\r
/// strapping of A10#. The value in this bit is written on the deassertion\r
/// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
///\r
- UINT32 BINIT_ObservationEnabled:1;\r
+ UINT32 BINIT_ObservationEnabled : 1;\r
///\r
/// [Bits 6:5] APIC Cluster ID (R) Contains the logical APIC cluster ID\r
/// value as set by the strapping of A12# and A11#. The logical cluster ID\r
/// value is written into the field on the deassertion of RESET#; the\r
/// field is set to 1 when the address bus signal is asserted.\r
///\r
- UINT32 APICClusterID:2;\r
+ UINT32 APICClusterID : 2;\r
///\r
/// [Bit 7] Bus Park Disable (R) Indicates whether bus park is enabled\r
/// (0) or disabled (1) as set by the strapping of A15#. The value in this\r
/// bit is written on the deassertion of RESET#; the bit is set to 1 when\r
/// the address bus signal is asserted.\r
///\r
- UINT32 BusParkDisable:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 BusParkDisable : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 13:12] Agent ID (R) Contains the logical agent ID value as set\r
/// by the strapping of BR[3:0]. The logical ID value is written into the\r
/// field on the deassertion of RESET#; the field is set to 1 when the\r
/// address bus signal is asserted.\r
///\r
- UINT32 AgentID:2;\r
- UINT32 Reserved2:18;\r
- UINT32 Reserved3:32;\r
+ UINT32 AgentID : 2;\r
+ UINT32 Reserved2 : 18;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER;\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W)\r
Enables and disables processor features.\r
@endcode\r
@note MSR_PENTIUM_4_EBC_SOFT_POWERON is defined as MSR_EBC_SOFT_POWERON in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B\r
+#define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON\r
/// driving of RCNT/SCNT on the request encoding. Set to enable (1); clear\r
/// to disabled (0, default).\r
///\r
- UINT32 RCNT_SCNT:1;\r
+ UINT32 RCNT_SCNT : 1;\r
///\r
/// [Bit 1] Data Error Checking Disable (R/W) Set to disable system data\r
/// bus parity checking; clear to enable parity checking.\r
///\r
- UINT32 DataErrorCheckingDisable:1;\r
+ UINT32 DataErrorCheckingDisable : 1;\r
///\r
/// [Bit 2] Response Error Checking Disable (R/W) Set to disable\r
/// (default); clear to enable.\r
///\r
- UINT32 ResponseErrorCheckingDisable:1;\r
+ UINT32 ResponseErrorCheckingDisable : 1;\r
///\r
/// [Bit 3] Address/Request Error Checking Disable (R/W) Set to disable\r
/// (default); clear to enable.\r
///\r
- UINT32 AddressRequestErrorCheckingDisable:1;\r
+ UINT32 AddressRequestErrorCheckingDisable : 1;\r
///\r
/// [Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving\r
/// for initiator bus requests (default); clear to enable.\r
///\r
- UINT32 InitiatorMCERR_Disable:1;\r
+ UINT32 InitiatorMCERR_Disable : 1;\r
///\r
/// [Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving\r
/// for initiator internal errors (default); clear to enable.\r
///\r
- UINT32 InternalMCERR_Disable:1;\r
+ UINT32 InternalMCERR_Disable : 1;\r
///\r
/// [Bit 6] BINIT# Driver Disable (R/W) Set to disable BINIT# driver\r
/// (default); clear to enable driver.\r
///\r
- UINT32 BINIT_DriverDisable:1;\r
- UINT32 Reserved1:25;\r
- UINT32 Reserved2:32;\r
+ UINT32 BINIT_DriverDisable : 1;\r
+ UINT32 Reserved1 : 25;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER;\r
\r
-\r
/**\r
2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of\r
this MSR varies according to the MODEL value in the CPUID version\r
@endcode\r
@note MSR_PENTIUM_4_EBC_FREQUENCY_ID is defined as MSR_EBC_FREQUENCY_ID in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C\r
+#define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable\r
/// bus speed: *EncodingScalable Bus Speed*\r
/// Speed when encoding is 100B and model encoding = 6. All other values\r
/// are reserved.\r
///\r
- UINT32 ScalableBusSpeed:3;\r
- UINT32 Reserved2:5;\r
+ UINT32 ScalableBusSpeed : 3;\r
+ UINT32 Reserved2 : 5;\r
///\r
/// [Bits 31:24] Core Clock Frequency to System Bus Frequency Ratio (R)\r
/// The processor core clock frequency to system bus frequency ratio\r
/// observed at the de-assertion of the reset pin.\r
///\r
- UINT32 ClockRatio:8;\r
- UINT32 Reserved3:32;\r
+ UINT32 ClockRatio : 8;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER;\r
\r
-\r
/**\r
0, 1. Shared. Processor Frequency Configuration (R) The bit field layout of\r
this MSR varies according to the MODEL value of the CPUID version\r
@endcode\r
@note MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 is defined as MSR_EBC_FREQUENCY_ID_1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C\r
+#define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:21;\r
+ UINT32 Reserved1 : 21;\r
///\r
/// [Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable\r
/// bus speed: *Encoding* *Scalable Bus Speed*\r
///\r
/// 000B 100 MHz All others values reserved.\r
///\r
- UINT32 ScalableBusSpeed:3;\r
- UINT32 Reserved2:8;\r
- UINT32 Reserved3:32;\r
+ UINT32 ScalableBusSpeed : 3;\r
+ UINT32 Reserved2 : 8;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER;\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section\r
15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RAX is defined as MSR_MCG_RAX in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RAX 0x00000180\r
-\r
+#define MSR_PENTIUM_4_MCG_RAX 0x00000180\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RBX is defined as MSR_MCG_RBX in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RBX 0x00000181\r
-\r
+#define MSR_PENTIUM_4_MCG_RBX 0x00000181\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RCX is defined as MSR_MCG_RCX in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RCX 0x00000182\r
-\r
+#define MSR_PENTIUM_4_MCG_RCX 0x00000182\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RDX is defined as MSR_MCG_RDX in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RDX 0x00000183\r
-\r
+#define MSR_PENTIUM_4_MCG_RDX 0x00000183\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RSI is defined as MSR_MCG_RSI in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RSI 0x00000184\r
-\r
+#define MSR_PENTIUM_4_MCG_RSI 0x00000184\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RDI is defined as MSR_MCG_RDI in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RDI 0x00000185\r
-\r
+#define MSR_PENTIUM_4_MCG_RDI 0x00000185\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RBP is defined as MSR_MCG_RBP in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RBP 0x00000186\r
-\r
+#define MSR_PENTIUM_4_MCG_RBP 0x00000186\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RSP is defined as MSR_MCG_RSP in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RSP 0x00000187\r
-\r
+#define MSR_PENTIUM_4_MCG_RSP 0x00000187\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RFLAGS is defined as MSR_MCG_RFLAGS in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188\r
-\r
+#define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RIP is defined as MSR_MCG_RIP in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RIP 0x00000189\r
-\r
+#define MSR_PENTIUM_4_MCG_RIP 0x00000189\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6,\r
@endcode\r
@note MSR_PENTIUM_4_MCG_MISC is defined as MSR_MCG_MISC in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_MISC 0x0000018A\r
+#define MSR_PENTIUM_4_MCG_MISC 0x0000018A\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC\r
/// code. It is the responsibility of the user (BIOS or operating system)\r
/// to clear this bit for normal operation.\r
///\r
- UINT32 DS:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 DS : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_MCG_MISC_REGISTER;\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG\r
Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R8 is defined as MSR_MCG_R8 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R8 0x00000190\r
-\r
+#define MSR_PENTIUM_4_MCG_R8 0x00000190\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6,\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R9 is defined as MSR_MCG_R9 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R9 0x00000191\r
-\r
+#define MSR_PENTIUM_4_MCG_R9 0x00000191\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R10 is defined as MSR_MCG_R10 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R10 0x00000192\r
-\r
+#define MSR_PENTIUM_4_MCG_R10 0x00000192\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R11 is defined as MSR_MCG_R11 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R11 0x00000193\r
-\r
+#define MSR_PENTIUM_4_MCG_R11 0x00000193\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R12 is defined as MSR_MCG_R12 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R12 0x00000194\r
-\r
+#define MSR_PENTIUM_4_MCG_R12 0x00000194\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R13 is defined as MSR_MCG_R13 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R13 0x00000195\r
-\r
+#define MSR_PENTIUM_4_MCG_R13 0x00000195\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R14 is defined as MSR_MCG_R14 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R14 0x00000196\r
-\r
+#define MSR_PENTIUM_4_MCG_R14 0x00000196\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R15 is defined as MSR_MCG_R15 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R15 0x00000197\r
-\r
+#define MSR_PENTIUM_4_MCG_R15 0x00000197\r
\r
/**\r
Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors:\r
@endcode\r
@note MSR_PENTIUM_4_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
**/\r
-#define MSR_PENTIUM_4_THERM2_CTL 0x0000019D\r
-\r
+#define MSR_PENTIUM_4_THERM2_CTL 0x0000019D\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE\r
///\r
/// [Bit 0] Fast-Strings Enable. See Table 2-2.\r
///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 FastStrings : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 2] x87 FPU Fopcode Compatibility Mode Enable.\r
///\r
- UINT32 FPU:1;\r
+ UINT32 FPU : 1;\r
///\r
/// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal\r
/// Monitor," and see Table 2-2.\r
///\r
- UINT32 TM1:1;\r
+ UINT32 TM1 : 1;\r
///\r
/// [Bit 4] Split-Lock Disable When set, the bit causes an #AC exception\r
/// to be issued instead of a split-lock cycle. Operating systems that set\r
/// bus.\r
/// This debug feature is specific to the Pentium 4 processor.\r
///\r
- UINT32 SplitLockDisable:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 SplitLockDisable : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 6] Third-Level Cache Disable (R/W) When set, the third-level\r
/// cache is disabled; when clear (default) the third-level cache is\r
/// control register CR0, the page-level cache controls, and/or the MTRRs.\r
/// See Section 11.5.4, "Disabling and Enabling the L3 Cache.".\r
///\r
- UINT32 ThirdLevelCacheDisable:1;\r
+ UINT32 ThirdLevelCacheDisable : 1;\r
///\r
/// [Bit 7] Performance Monitoring Available (R) See Table 2-2.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
+ UINT32 PerformanceMonitoring : 1;\r
///\r
/// [Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is\r
/// suppressed during a Split Lock access. When clear (default), LOCK is\r
/// not suppressed.\r
///\r
- UINT32 SuppressLockEnable:1;\r
+ UINT32 SuppressLockEnable : 1;\r
///\r
/// [Bit 9] Prefetch Queue Disable When set, disables the prefetch queue.\r
/// When clear (default), enables the prefetch queue.\r
///\r
- UINT32 PrefetchQueueDisable:1;\r
+ UINT32 PrefetchQueueDisable : 1;\r
///\r
/// [Bit 10] FERR# Interrupt Reporting Enable (R/W) When set, interrupt\r
/// reporting through the FERR# pin is enabled; when clear, this interrupt\r
/// the normal operation of the FERR# pin (to indicate an unmasked\r
/// floatingpoint error) when the STPCLK# pin is not asserted.\r
///\r
- UINT32 FERR:1;\r
+ UINT32 FERR : 1;\r
///\r
/// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See\r
/// Table 2-2. When set, the processor does not support branch trace\r
/// storage (BTS); when clear, BTS is supported.\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable\r
/// (R) See Table 2-2. When set, the processor does not support processor\r
/// event-based sampling (PEBS); when clear, PEBS is supported.\r
///\r
- UINT32 PEBS:1;\r
+ UINT32 PEBS : 1;\r
///\r
/// [Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal\r
/// sensor indicates that the die temperature is at the predetermined\r
/// this bit location. The processor is operating out of spec if both this\r
/// bit and the TM1 bit are set to disabled states.\r
///\r
- UINT32 TM2:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 TM2 : 1;\r
+ UINT32 Reserved3 : 4;\r
///\r
/// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
- UINT32 MONITOR:1;\r
+ UINT32 MONITOR : 1;\r
///\r
/// [Bit 19] Adjacent Cache Line Prefetch Disable (R/W) When set to 1,\r
/// the processor fetches the cache line of the 128-byte sector containing\r
/// in validation and testing. BIOS may contain a setup option that\r
/// controls the setting of this bit.\r
///\r
- UINT32 AdjacentCacheLinePrefetchDisable:1;\r
- UINT32 Reserved4:2;\r
+ UINT32 AdjacentCacheLinePrefetchDisable : 1;\r
+ UINT32 Reserved4 : 2;\r
///\r
/// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this\r
/// can cause unexpected behavior to software that depends on the\r
/// availability of CPUID leaves greater than 3.\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
+ UINT32 LimitCpuidMaxval : 1;\r
///\r
/// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
+ UINT32 xTPR_Message_Disable : 1;\r
///\r
/// [Bit 24] L1 Data Cache Context Mode (R/W) When set, the L1 data cache\r
/// is placed in shared mode; when clear (default), the cache is placed in\r
/// the ability to switch modes is not supported. BIOS must not alter the\r
/// contents of IA32_MISC_ENABLE[24].\r
///\r
- UINT32 L1DataCacheContextMode:1;\r
- UINT32 Reserved5:7;\r
- UINT32 Reserved6:2;\r
+ UINT32 L1DataCacheContextMode : 1;\r
+ UINT32 Reserved5 : 7;\r
+ UINT32 Reserved6 : 2;\r
///\r
/// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved7:29;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved7 : 29;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
3, 4, 6. Shared. Platform Feature Requirements (R).\r
\r
@endcode\r
@note MSR_PENTIUM_4_PLATFORM_BRV is defined as MSR_PLATFORM_BRV in SDM.\r
**/\r
-#define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1\r
+#define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:18;\r
+ UINT32 Reserved1 : 18;\r
///\r
/// [Bit 18] PLATFORM Requirements When set to 1, indicates the processor\r
/// has specific platform requirements. The details of the platform\r
/// requirements are listed in the respective data sheets of the processor.\r
///\r
- UINT32 PLATFORM:1;\r
- UINT32 Reserved2:13;\r
- UINT32 Reserved3:32;\r
+ UINT32 PLATFORM : 1;\r
+ UINT32 Reserved2 : 13;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_PLATFORM_BRV_REGISTER;\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains\r
a pointer to the last branch instruction that the processor executed prior\r
@endcode\r
@note MSR_PENTIUM_4_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
-#define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7\r
-\r
+#define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area\r
@endcode\r
@note MSR_PENTIUM_4_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
-#define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8\r
-\r
+#define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug\r
@endcode\r
@note MSR_PENTIUM_4_DEBUGCTLA is defined as MSR_DEBUGCTLA in SDM.\r
**/\r
-#define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9\r
-\r
+#define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an\r
@endcode\r
@note MSR_PENTIUM_4_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA\r
-\r
+#define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA\r
\r
/**\r
0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record\r
MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB\r
-#define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC\r
-#define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD\r
-#define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE\r
+#define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB\r
+#define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC\r
+#define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD\r
+#define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
\r
MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300\r
-#define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301\r
-#define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302\r
-#define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303\r
+#define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300\r
+#define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301\r
+#define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302\r
+#define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
\r
MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_MS_COUNTER0 0x00000304\r
-#define MSR_PENTIUM_4_MS_COUNTER1 0x00000305\r
-#define MSR_PENTIUM_4_MS_COUNTER2 0x00000306\r
-#define MSR_PENTIUM_4_MS_COUNTER3 0x00000307\r
+#define MSR_PENTIUM_4_MS_COUNTER0 0x00000304\r
+#define MSR_PENTIUM_4_MS_COUNTER1 0x00000305\r
+#define MSR_PENTIUM_4_MS_COUNTER2 0x00000306\r
+#define MSR_PENTIUM_4_MS_COUNTER3 0x00000307\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
\r
MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308\r
-#define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309\r
-#define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A\r
-#define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B\r
+#define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308\r
+#define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309\r
+#define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A\r
+#define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
\r
MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C\r
-#define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D\r
-#define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E\r
-#define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F\r
-#define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310\r
-#define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311\r
+#define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C\r
+#define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D\r
+#define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E\r
+#define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F\r
+#define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310\r
+#define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
\r
MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_BPU_CCCR0 0x00000360\r
-#define MSR_PENTIUM_4_BPU_CCCR1 0x00000361\r
-#define MSR_PENTIUM_4_BPU_CCCR2 0x00000362\r
-#define MSR_PENTIUM_4_BPU_CCCR3 0x00000363\r
+#define MSR_PENTIUM_4_BPU_CCCR0 0x00000360\r
+#define MSR_PENTIUM_4_BPU_CCCR1 0x00000361\r
+#define MSR_PENTIUM_4_BPU_CCCR2 0x00000362\r
+#define MSR_PENTIUM_4_BPU_CCCR3 0x00000363\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
\r
MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_MS_CCCR0 0x00000364\r
-#define MSR_PENTIUM_4_MS_CCCR1 0x00000365\r
-#define MSR_PENTIUM_4_MS_CCCR2 0x00000366\r
-#define MSR_PENTIUM_4_MS_CCCR3 0x00000367\r
+#define MSR_PENTIUM_4_MS_CCCR0 0x00000364\r
+#define MSR_PENTIUM_4_MS_CCCR1 0x00000365\r
+#define MSR_PENTIUM_4_MS_CCCR2 0x00000366\r
+#define MSR_PENTIUM_4_MS_CCCR3 0x00000367\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
\r
MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368\r
-#define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369\r
-#define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A\r
-#define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B\r
+#define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368\r
+#define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369\r
+#define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A\r
+#define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
\r
MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C\r
-#define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D\r
-#define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E\r
-#define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F\r
-#define MSR_PENTIUM_4_IQ_CCCR4 0x00000370\r
-#define MSR_PENTIUM_4_IQ_CCCR5 0x00000371\r
+#define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C\r
+#define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D\r
+#define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E\r
+#define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F\r
+#define MSR_PENTIUM_4_IQ_CCCR4 0x00000370\r
+#define MSR_PENTIUM_4_IQ_CCCR5 0x00000371\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@endcode\r
@note MSR_PENTIUM_4_BSU_ESCR0 is defined as MSR_BSU_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0\r
-\r
+#define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_BSU_ESCR1 is defined as MSR_BSU_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1\r
-\r
+#define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_FSB_ESCR0 is defined as MSR_FSB_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2\r
-\r
+#define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_FSB_ESCR1 is defined as MSR_FSB_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3\r
-\r
+#define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_FIRM_ESCR0 is defined as MSR_FIRM_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4\r
-\r
+#define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_FIRM_ESCR1 is defined as MSR_FIRM_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5\r
-\r
+#define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_FLAME_ESCR0 is defined as MSR_FLAME_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6\r
-\r
+#define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_FLAME_ESCR1 is defined as MSR_FLAME_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7\r
-\r
+#define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_DAC_ESCR0 is defined as MSR_DAC_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8\r
-\r
+#define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_DAC_ESCR1 is defined as MSR_DAC_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9\r
-\r
+#define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_MOB_ESCR0 is defined as MSR_MOB_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA\r
-\r
+#define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_MOB_ESCR1 is defined as MSR_MOB_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB\r
-\r
+#define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_PMH_ESCR0 is defined as MSR_PMH_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC\r
-\r
+#define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_PMH_ESCR1 is defined as MSR_PMH_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD\r
-\r
+#define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_SAAT_ESCR0 is defined as MSR_SAAT_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE\r
-\r
+#define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_SAAT_ESCR1 is defined as MSR_SAAT_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF\r
-\r
+#define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_U2L_ESCR0 is defined as MSR_U2L_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0\r
-\r
+#define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_U2L_ESCR1 is defined as MSR_U2L_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1\r
-\r
+#define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_BPU_ESCR0 is defined as MSR_BPU_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2\r
-\r
+#define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_BPU_ESCR1 is defined as MSR_BPU_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3\r
-\r
+#define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_IS_ESCR0 is defined as MSR_IS_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IS_ESCR0 0x000003B4\r
-\r
+#define MSR_PENTIUM_4_IS_ESCR0 0x000003B4\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_IS_ESCR1 is defined as MSR_IS_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IS_ESCR1 0x000003B5\r
-\r
+#define MSR_PENTIUM_4_IS_ESCR1 0x000003B5\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_ITLB_ESCR0 is defined as MSR_ITLB_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6\r
-\r
+#define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_ITLB_ESCR1 is defined as MSR_ITLB_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7\r
-\r
+#define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_CRU_ESCR0 is defined as MSR_CRU_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8\r
-\r
+#define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_CRU_ESCR1 is defined as MSR_CRU_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9\r
-\r
+#define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9\r
\r
/**\r
0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not\r
@endcode\r
@note MSR_PENTIUM_4_IQ_ESCR0 is defined as MSR_IQ_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA\r
-\r
+#define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA\r
\r
/**\r
0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not\r
@endcode\r
@note MSR_PENTIUM_4_IQ_ESCR1 is defined as MSR_IQ_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB\r
-\r
+#define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_RAT_ESCR0 is defined as MSR_RAT_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC\r
-\r
+#define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_RAT_ESCR1 is defined as MSR_RAT_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD\r
-\r
+#define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_SSU_ESCR0 is defined as MSR_SSU_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE\r
-\r
+#define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_MS_ESCR0 is defined as MSR_MS_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MS_ESCR0 0x000003C0\r
-\r
+#define MSR_PENTIUM_4_MS_ESCR0 0x000003C0\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_MS_ESCR1 is defined as MSR_MS_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MS_ESCR1 0x000003C1\r
-\r
+#define MSR_PENTIUM_4_MS_ESCR1 0x000003C1\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_TBPU_ESCR0 is defined as MSR_TBPU_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2\r
-\r
+#define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_TBPU_ESCR1 is defined as MSR_TBPU_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3\r
-\r
+#define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_TC_ESCR0 is defined as MSR_TC_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_TC_ESCR0 0x000003C4\r
-\r
+#define MSR_PENTIUM_4_TC_ESCR0 0x000003C4\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_TC_ESCR1 is defined as MSR_TC_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_TC_ESCR1 0x000003C5\r
-\r
+#define MSR_PENTIUM_4_TC_ESCR1 0x000003C5\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_IX_ESCR0 is defined as MSR_IX_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IX_ESCR0 0x000003C8\r
-\r
+#define MSR_PENTIUM_4_IX_ESCR0 0x000003C8\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_IX_ESCR1 is defined as MSR_IX_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IX_ESCR1 0x000003C9\r
-\r
+#define MSR_PENTIUM_4_IX_ESCR1 0x000003C9\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA\r
-#define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB\r
-#define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC\r
-#define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD\r
-#define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0\r
-#define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1\r
+#define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA\r
+#define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB\r
+#define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC\r
+#define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD\r
+#define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0\r
+#define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@endcode\r
@note MSR_PENTIUM_4_TC_PRECISE_EVENT is defined as MSR_TC_PRECISE_EVENT in SDM.\r
**/\r
-#define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0\r
-\r
+#define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. Processor Event Based Sampling (PEBS) (R/W)\r
@endcode\r
@note MSR_PENTIUM_4_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1\r
+#define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE\r
///\r
/// [Bits 12:0] See Table 19-36.\r
///\r
- UINT32 EventNum:13;\r
- UINT32 Reserved1:11;\r
+ UINT32 EventNum : 13;\r
+ UINT32 Reserved1 : 11;\r
///\r
/// [Bit 24] UOP Tag Enables replay tagging when set.\r
///\r
- UINT32 UOP:1;\r
+ UINT32 UOP : 1;\r
///\r
/// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical\r
/// processor when set; disables PEBS when clear (default). See Section\r
/// logical processor. This bit is called ENABLE_PEBS in IA-32 processors\r
/// that do not support Intel HyperThreading Technology.\r
///\r
- UINT32 ENABLE_PEBS_MY_THR:1;\r
+ UINT32 ENABLE_PEBS_MY_THR : 1;\r
///\r
/// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical\r
/// processor when set; disables PEBS when clear (default). See Section\r
/// logical processor. This bit is reserved for IA-32 processors that do\r
/// not support Intel Hyper-Threading Technology.\r
///\r
- UINT32 ENABLE_PEBS_OTH_THR:1;\r
- UINT32 Reserved2:5;\r
- UINT32 Reserved3:32;\r
+ UINT32 ENABLE_PEBS_OTH_THR : 1;\r
+ UINT32 Reserved2 : 5;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Table 19-36.\r
\r
@endcode\r
@note MSR_PENTIUM_4_PEBS_MATRIX_VERT is defined as MSR_PEBS_MATRIX_VERT in SDM.\r
**/\r
-#define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2\r
-\r
+#define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2\r
\r
/**\r
3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch\r
MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680\r
-#define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681\r
-#define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682\r
-#define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683\r
-#define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684\r
-#define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685\r
-#define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686\r
-#define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687\r
-#define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688\r
-#define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689\r
-#define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A\r
-#define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B\r
-#define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C\r
-#define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D\r
-#define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E\r
-#define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F\r
+#define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680\r
+#define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681\r
+#define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682\r
+#define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683\r
+#define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684\r
+#define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685\r
+#define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686\r
+#define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687\r
+#define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688\r
+#define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689\r
+#define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A\r
+#define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B\r
+#define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C\r
+#define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D\r
+#define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E\r
+#define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F\r
/// @}\r
\r
-\r
/**\r
3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch\r
record registers on the last branch record stack (6C0H-6CFH). This part of\r
MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0\r
-#define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1\r
-#define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2\r
-#define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3\r
-#define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4\r
-#define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5\r
-#define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6\r
-#define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7\r
-#define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8\r
-#define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9\r
-#define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA\r
-#define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB\r
-#define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC\r
-#define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD\r
-#define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE\r
-#define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF\r
+#define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0\r
+#define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1\r
+#define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2\r
+#define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3\r
+#define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4\r
+#define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5\r
+#define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6\r
+#define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7\r
+#define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8\r
+#define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9\r
+#define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA\r
+#define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB\r
+#define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC\r
+#define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD\r
+#define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE\r
+#define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF\r
/// @}\r
\r
-\r
/**\r
3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See Section\r
18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to\r
@endcode\r
@note MSR_PENTIUM_4_IFSB_BUSQ0 is defined as MSR_IFSB_BUSQ0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC\r
-\r
+#define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC\r
\r
/**\r
3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_IFSB_BUSQ1 is defined as MSR_IFSB_BUSQ1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD\r
-\r
+#define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD\r
\r
/**\r
3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See Section\r
@endcode\r
@note MSR_PENTIUM_4_IFSB_SNPQ0 is defined as MSR_IFSB_SNPQ0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE\r
-\r
+#define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE\r
\r
/**\r
3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_IFSB_SNPQ1 is defined as MSR_IFSB_SNPQ1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF\r
-\r
+#define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF\r
\r
/**\r
3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See Section\r
@endcode\r
@note MSR_PENTIUM_4_EFSB_DRDY0 is defined as MSR_EFSB_DRDY0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0\r
-\r
+#define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0\r
\r
/**\r
3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_EFSB_DRDY1 is defined as MSR_EFSB_DRDY1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1\r
-\r
+#define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1\r
\r
/**\r
3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.6.6,\r
@endcode\r
@note MSR_PENTIUM_4_IFSB_CTL6 is defined as MSR_IFSB_CTL6 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2\r
-\r
+#define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2\r
\r
/**\r
3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.6.6,\r
@endcode\r
@note MSR_PENTIUM_4_IFSB_CNTR7 is defined as MSR_IFSB_CNTR7 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3\r
-\r
+#define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3\r
\r
/**\r
6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC\r
-\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC\r
\r
/**\r
6. Shared. GBUSQ Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD\r
-\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD\r
\r
/**\r
6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE\r
-\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE\r
\r
/**\r
6. Shared. GSNPQ Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF\r
-\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF\r
\r
/**\r
6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.6.6,\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0\r
-\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0\r
\r
/**\r
6. Shared. FSB Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1\r
-\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1\r
\r
/**\r
6. Shared. FSB Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2\r
-\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2\r
\r
/**\r
6. Shared. FSB Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff