@endcode\r
@note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034\r
+#define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT\r
///\r
/// [Bits 31:0] SMI Count (R/O) Count SMIs.\r
///\r
- UINT32 SMICount:32;\r
- UINT32 Reserved:32;\r
+ UINT32 SMICount : 32;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER;\r
\r
-\r
/**\r
Package. Platform Information Contains power management and other model\r
specific features enumeration. See http://biosbits.org.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE\r
+#define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
/// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
/// MHz.\r
///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
+ UINT32 MaximumNonTurboRatio : 8;\r
+ UINT32 Reserved2 : 12;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
/// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
/// Turbo mode is disabled.\r
///\r
- UINT32 RatioLimit:1;\r
+ UINT32 RatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
/// and when set to 0, indicates TDP Limit for Turbo mode is not\r
/// programmable.\r
///\r
- UINT32 TDPLimit:1;\r
- UINT32 Reserved3:2;\r
- UINT32 Reserved4:8;\r
+ UINT32 TDPLimit : 1;\r
+ UINT32 Reserved3 : 2;\r
+ UINT32 Reserved4 : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
/// minimum ratio (maximum efficiency) that the processor can operates, in\r
/// units of 100MHz.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved5:16;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
+ UINT32 Reserved5 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER;\r
\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are\r
processor specific C-state code names, unrelated to MWAIT extension C-state\r
/// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:\r
/// This field cannot be used to limit package C-state to C3.\r
///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 Limit : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
/// IO_read instructions sent to IO register specified by\r
/// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
/// until next reset.\r
///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:9;\r
+ UINT32 CFGLock : 1;\r
+ UINT32 Reserved3 : 9;\r
///\r
/// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
/// will conditionally demote C6/C7 requests to C3 based on uncore\r
/// auto-demote information.\r
///\r
- UINT32 C3AutoDemotion:1;\r
+ UINT32 C3AutoDemotion : 1;\r
///\r
/// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
/// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
/// auto-demote information.\r
///\r
- UINT32 C1AutoDemotion:1;\r
+ UINT32 C1AutoDemotion : 1;\r
///\r
/// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from\r
/// demoted C3.\r
///\r
- UINT32 C3Undemotion:1;\r
+ UINT32 C3Undemotion : 1;\r
///\r
/// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from\r
/// demoted C1.\r
///\r
- UINT32 C1Undemotion:1;\r
- UINT32 Reserved4:3;\r
- UINT32 Reserved5:32;\r
+ UINT32 C1Undemotion : 1;\r
+ UINT32 Reserved4 : 3;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Core. Power Management IO Redirection in C-state (R/W) See\r
http://biosbits.org.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4\r
+#define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE\r
/// address redirection is enabled, this is the IO port address reported\r
/// to the OS/software.\r
///\r
- UINT32 Lvl2Base:16;\r
+ UINT32 Lvl2Base : 16;\r
///\r
/// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
/// maximum C-State code name to be included when IO read to MWAIT\r
/// is the max C-State to include 001b - C6 is the max C-State to include\r
/// 010b - C7 is the max C-State to include.\r
///\r
- UINT32 CStateRange:3;\r
- UINT32 Reserved1:13;\r
- UINT32 Reserved2:32;\r
+ UINT32 CStateRange : 3;\r
+ UINT32 Reserved1 : 13;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER;\r
\r
-\r
/**\r
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
handler to handle unsuccessful read of this MSR.\r
@endcode\r
@note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C\r
+#define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG\r
/// 01b, AES instruction can be mis-configured if a privileged agent\r
/// unintentionally writes 11b.\r
///\r
- UINT32 AESConfiguration:2;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 AESConfiguration : 2;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER;\r
\r
-\r
/**\r
Core. See Table 2-2. If CPUID.0AH:EAX[15:8] = 8.\r
\r
MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A\r
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B\r
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C\r
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D\r
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A\r
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B\r
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C\r
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D\r
/// @}\r
\r
-\r
/**\r
Package.\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198\r
+#define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
+ UINT32 Reserved1 : 32;\r
///\r
/// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed\r
/// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).\r
///\r
- UINT32 CoreVoltage:16;\r
- UINT32 Reserved2:16;\r
+ UINT32 CoreVoltage : 16;\r
+ UINT32 Reserved2 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER;\r
\r
-\r
/**\r
Thread. Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was\r
originally named IA32_THERM_CONTROL MSR.\r
@endcode\r
@note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A\r
+#define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A\r
\r
/**\r
MSR information returned for MSR index\r
/// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25%\r
/// increment.\r
///\r
- UINT32 OnDemandClockModulationDutyCycle:4;\r
+ UINT32 OnDemandClockModulationDutyCycle : 4;\r
///\r
/// [Bit 4] On demand Clock Modulation Enable (R/W).\r
///\r
- UINT32 OnDemandClockModulationEnable:1;\r
- UINT32 Reserved1:27;\r
- UINT32 Reserved2:32;\r
+ UINT32 OnDemandClockModulationEnable : 1;\r
+ UINT32 Reserved1 : 27;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER;\r
\r
-\r
/**\r
Enable Misc. Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE\r
///\r
/// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.\r
///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:6;\r
+ UINT32 FastStrings : 1;\r
+ UINT32 Reserved1 : 6;\r
///\r
/// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 2-2.\r
///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved3:3;\r
+ UINT32 PEBS : 1;\r
+ UINT32 Reserved3 : 3;\r
///\r
/// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
/// Table 2-2.\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved5:3;\r
+ UINT32 MONITOR : 1;\r
+ UINT32 Reserved5 : 3;\r
///\r
/// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
+ UINT32 LimitCpuidMaxval : 1;\r
///\r
/// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved6:8;\r
- UINT32 Reserved7:2;\r
+ UINT32 xTPR_Message_Disable : 1;\r
+ UINT32 Reserved6 : 8;\r
+ UINT32 Reserved7 : 2;\r
///\r
/// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved8:3;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved8 : 3;\r
///\r
/// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
/// that support Intel Turbo Boost Technology, the turbo mode feature is\r
/// in the processor. If power-on default value is 0, turbo mode is not\r
/// available.\r
///\r
- UINT32 TurboModeDisable:1;\r
- UINT32 Reserved9:25;\r
+ UINT32 TurboModeDisable : 1;\r
+ UINT32 Reserved9 : 25;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Unique.\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
+#define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bits 23:16] Temperature Target (R) The minimum temperature at which\r
/// PROCHOT# will be asserted. The value is degree C.\r
///\r
- UINT32 TemperatureTarget:8;\r
- UINT32 Reserved2:8;\r
- UINT32 Reserved3:32;\r
+ UINT32 TemperatureTarget : 8;\r
+ UINT32 Reserved2 : 8;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER;\r
\r
-\r
/**\r
Miscellaneous Feature Control (R/W).\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4\r
+#define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL\r
/// L2 hardware prefetcher, which fetches additional lines of code or data\r
/// into the L2 cache.\r
///\r
- UINT32 L2HardwarePrefetcherDisable:1;\r
+ UINT32 L2HardwarePrefetcherDisable : 1;\r
///\r
/// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,\r
/// disables the adjacent cache line prefetcher, which fetches the cache\r
/// line that comprises a cache line pair (128 bytes).\r
///\r
- UINT32 L2AdjacentCacheLinePrefetcherDisable:1;\r
+ UINT32 L2AdjacentCacheLinePrefetcherDisable : 1;\r
///\r
/// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
/// the L1 data cache prefetcher, which fetches the next cache line into\r
/// L1 data cache.\r
///\r
- UINT32 DCUHardwarePrefetcherDisable:1;\r
+ UINT32 DCUHardwarePrefetcherDisable : 1;\r
///\r
/// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1\r
/// data cache IP prefetcher, which uses sequential load history (based on\r
/// instruction Pointer of previous loads) to determine whether to\r
/// prefetch additional lines.\r
///\r
- UINT32 DCUIPPrefetcherDisable:1;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
+ UINT32 DCUIPPrefetcherDisable : 1;\r
+ UINT32 Reserved1 : 28;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Thread. Offcore Response Event Select Register (R/W).\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6\r
-\r
+#define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6\r
\r
/**\r
Thread. Offcore Response Event Select Register (R/W).\r
@endcode\r
@note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7\r
-\r
+#define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7\r
\r
/**\r
See http://biosbits.org.\r
@endcode\r
@note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA\r
-\r
+#define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA\r
\r
/**\r
Thread. Last Branch Record Filtering Select Register (R/W) See Section\r
@endcode\r
@note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8\r
+#define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT\r
///\r
/// [Bit 0] CPL_EQ_0.\r
///\r
- UINT32 CPL_EQ_0:1;\r
+ UINT32 CPL_EQ_0 : 1;\r
///\r
/// [Bit 1] CPL_NEQ_0.\r
///\r
- UINT32 CPL_NEQ_0:1;\r
+ UINT32 CPL_NEQ_0 : 1;\r
///\r
/// [Bit 2] JCC.\r
///\r
- UINT32 JCC:1;\r
+ UINT32 JCC : 1;\r
///\r
/// [Bit 3] NEAR_REL_CALL.\r
///\r
- UINT32 NEAR_REL_CALL:1;\r
+ UINT32 NEAR_REL_CALL : 1;\r
///\r
/// [Bit 4] NEAR_IND_CALL.\r
///\r
- UINT32 NEAR_IND_CALL:1;\r
+ UINT32 NEAR_IND_CALL : 1;\r
///\r
/// [Bit 5] NEAR_RET.\r
///\r
- UINT32 NEAR_RET:1;\r
+ UINT32 NEAR_RET : 1;\r
///\r
/// [Bit 6] NEAR_IND_JMP.\r
///\r
- UINT32 NEAR_IND_JMP:1;\r
+ UINT32 NEAR_IND_JMP : 1;\r
///\r
/// [Bit 7] NEAR_REL_JMP.\r
///\r
- UINT32 NEAR_REL_JMP:1;\r
+ UINT32 NEAR_REL_JMP : 1;\r
///\r
/// [Bit 8] FAR_BRANCH.\r
///\r
- UINT32 FAR_BRANCH:1;\r
- UINT32 Reserved1:23;\r
- UINT32 Reserved2:32;\r
+ UINT32 FAR_BRANCH : 1;\r
+ UINT32 Reserved1 : 23;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER;\r
\r
-\r
/**\r
Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
that points to the MSR containing the most recent branch record. See\r
@endcode\r
@note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Thread. Last Exception Record From Linear IP (R) Contains a pointer to the\r
@endcode\r
@note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD\r
-\r
+#define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD\r
\r
/**\r
Thread. Last Exception Record To Linear IP (R) This area contains a pointer\r
@endcode\r
@note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE\r
-\r
+#define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE\r
\r
/**\r
Core. See http://biosbits.org.\r
@endcode\r
@note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC\r
-\r
+#define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC\r
\r
/**\r
Package. Always 0 (CMCI not supported).\r
@endcode\r
@note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284\r
-\r
+#define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284\r
\r
/**\r
See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
+#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
\r
/**\r
MSR information returned for MSR index\r
///\r
/// [Bit 0] Thread. Ovf_PMC0.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Thread. Ovf_PMC1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Thread. Ovf_PMC2.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Thread. Ovf_PMC3.\r
///\r
- UINT32 Ovf_PMC3:1;\r
+ UINT32 Ovf_PMC3 : 1;\r
///\r
/// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
///\r
- UINT32 Ovf_PMC4:1;\r
+ UINT32 Ovf_PMC4 : 1;\r
///\r
/// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
///\r
- UINT32 Ovf_PMC5:1;\r
+ UINT32 Ovf_PMC5 : 1;\r
///\r
/// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
///\r
- UINT32 Ovf_PMC6:1;\r
+ UINT32 Ovf_PMC6 : 1;\r
///\r
/// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
///\r
- UINT32 Ovf_PMC7:1;\r
- UINT32 Reserved1:24;\r
+ UINT32 Ovf_PMC7 : 1;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bit 32] Thread. Ovf_FixedCtr0.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Thread. Ovf_FixedCtr1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Thread. Ovf_FixedCtr2.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:26;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 26;\r
///\r
/// [Bit 61] Thread. Ovf_Uncore.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Thread. Ovf_BufDSSAVE.\r
///\r
- UINT32 Ovf_BufDSSAVE:1;\r
+ UINT32 Ovf_BufDSSAVE : 1;\r
///\r
/// [Bit 63] Thread. CondChgd.\r
///\r
- UINT32 CondChgd:1;\r
+ UINT32 CondChgd : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
\r
-\r
/**\r
Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control\r
Facilities.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F\r
+#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F\r
\r
/**\r
MSR information returned for MSR index\r
///\r
/// [Bit 0] Thread. Set 1 to enable PMC0 to count.\r
///\r
- UINT32 PCM0_EN:1;\r
+ UINT32 PCM0_EN : 1;\r
///\r
/// [Bit 1] Thread. Set 1 to enable PMC1 to count.\r
///\r
- UINT32 PCM1_EN:1;\r
+ UINT32 PCM1_EN : 1;\r
///\r
/// [Bit 2] Thread. Set 1 to enable PMC2 to count.\r
///\r
- UINT32 PCM2_EN:1;\r
+ UINT32 PCM2_EN : 1;\r
///\r
/// [Bit 3] Thread. Set 1 to enable PMC3 to count.\r
///\r
- UINT32 PCM3_EN:1;\r
+ UINT32 PCM3_EN : 1;\r
///\r
/// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] >\r
/// 4).\r
///\r
- UINT32 PCM4_EN:1;\r
+ UINT32 PCM4_EN : 1;\r
///\r
/// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] >\r
/// 5).\r
///\r
- UINT32 PCM5_EN:1;\r
+ UINT32 PCM5_EN : 1;\r
///\r
/// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] >\r
/// 6).\r
///\r
- UINT32 PCM6_EN:1;\r
+ UINT32 PCM6_EN : 1;\r
///\r
/// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] >\r
/// 7).\r
///\r
- UINT32 PCM7_EN:1;\r
- UINT32 Reserved1:24;\r
+ UINT32 PCM7_EN : 1;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count.\r
///\r
- UINT32 FIXED_CTR0:1;\r
+ UINT32 FIXED_CTR0 : 1;\r
///\r
/// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count.\r
///\r
- UINT32 FIXED_CTR1:1;\r
+ UINT32 FIXED_CTR1 : 1;\r
///\r
/// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count.\r
///\r
- UINT32 FIXED_CTR2:1;\r
- UINT32 Reserved2:29;\r
+ UINT32 FIXED_CTR2 : 1;\r
+ UINT32 Reserved2 : 29;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER;\r
\r
-\r
/**\r
See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r
+#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r
\r
/**\r
MSR information returned for MSR index\r
///\r
/// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.\r
///\r
- UINT32 Ovf_PMC3:1;\r
+ UINT32 Ovf_PMC3 : 1;\r
///\r
/// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
///\r
- UINT32 Ovf_PMC4:1;\r
+ UINT32 Ovf_PMC4 : 1;\r
///\r
/// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
///\r
- UINT32 Ovf_PMC5:1;\r
+ UINT32 Ovf_PMC5 : 1;\r
///\r
/// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
///\r
- UINT32 Ovf_PMC6:1;\r
+ UINT32 Ovf_PMC6 : 1;\r
///\r
/// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
///\r
- UINT32 Ovf_PMC7:1;\r
- UINT32 Reserved1:24;\r
+ UINT32 Ovf_PMC7 : 1;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:26;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 26;\r
///\r
/// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.\r
///\r
- UINT32 Ovf_BufDSSAVE:1;\r
+ UINT32 Ovf_BufDSSAVE : 1;\r
///\r
/// [Bit 63] Thread. Set 1 to clear CondChgd.\r
///\r
- UINT32 CondChgd:1;\r
+ UINT32 CondChgd : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
\r
-\r
/**\r
Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1\r
+#define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE\r
///\r
/// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC0:1;\r
+ UINT32 PEBS_EN_PMC0 : 1;\r
///\r
/// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC1:1;\r
+ UINT32 PEBS_EN_PMC1 : 1;\r
///\r
/// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC2:1;\r
+ UINT32 PEBS_EN_PMC2 : 1;\r
///\r
/// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC3:1;\r
- UINT32 Reserved1:28;\r
+ UINT32 PEBS_EN_PMC3 : 1;\r
+ UINT32 Reserved1 : 28;\r
///\r
/// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
///\r
- UINT32 LL_EN_PMC0:1;\r
+ UINT32 LL_EN_PMC0 : 1;\r
///\r
/// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
///\r
- UINT32 LL_EN_PMC1:1;\r
+ UINT32 LL_EN_PMC1 : 1;\r
///\r
/// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
///\r
- UINT32 LL_EN_PMC2:1;\r
+ UINT32 LL_EN_PMC2 : 1;\r
///\r
/// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
///\r
- UINT32 LL_EN_PMC3:1;\r
- UINT32 Reserved2:27;\r
+ UINT32 LL_EN_PMC3 : 1;\r
+ UINT32 Reserved2 : 27;\r
///\r
/// [Bit 63] Enable Precise Store. (R/W).\r
///\r
- UINT32 PS_EN:1;\r
+ UINT32 PS_EN : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring\r
Facility.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6\r
+#define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT\r
/// [Bits 15:0] Minimum threshold latency value of tagged load operation\r
/// that will be counted. (R/W).\r
///\r
- UINT32 MinimumThreshold:16;\r
- UINT32 Reserved1:16;\r
- UINT32 Reserved2:32;\r
+ UINT32 MinimumThreshold : 16;\r
+ UINT32 Reserved1 : 16;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8\r
\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9\r
\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC\r
-\r
+#define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD\r
-\r
+#define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE\r
-\r
+#define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE\r
\r
/**\r
Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410\r
+#define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL\r
/// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU\r
/// hardware detected errors.\r
///\r
- UINT32 PCUHardwareError:1;\r
+ UINT32 PCUHardwareError : 1;\r
///\r
/// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU\r
/// controller detected errors.\r
///\r
- UINT32 PCUControllerError:1;\r
+ UINT32 PCUControllerError : 1;\r
///\r
/// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU\r
/// firmware detected errors.\r
///\r
- UINT32 PCUFirmwareError:1;\r
- UINT32 Reserved1:29;\r
- UINT32 Reserved2:32;\r
+ UINT32 PCUFirmwareError : 1;\r
+ UINT32 Reserved1 : 29;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER;\r
\r
-\r
/**\r
Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r
\r
**/\r
#define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
\r
-\r
/**\r
Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r
"RAPL Interfaces.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606\r
-\r
+#define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606\r
\r
/**\r
Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A\r
+#define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL\r
/// that should be used to decide if the package should be put into a\r
/// package C3 state.\r
///\r
- UINT32 TimeLimit:10;\r
+ UINT32 TimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
/// unit of the interrupt response time limit. The following time unit\r
/// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
/// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER;\r
\r
-\r
/**\r
Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the\r
budget allocated for the package to exit from C6 to a C0 state, where\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B\r
+#define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL\r
/// that should be used to decide if the package should be put into a\r
/// package C6 state.\r
///\r
- UINT32 TimeLimit:10;\r
+ UINT32 TimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
/// unit of the interrupt response time limit. The following time unit\r
/// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
/// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D\r
\r
/**\r
Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610\r
\r
/**\r
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611\r
\r
/**\r
Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614\r
\r
/**\r
Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
@endcode\r
@note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638\r
-\r
+#define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638\r
\r
/**\r
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r
MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F\r
/// @}\r
\r
-\r
/**\r
Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r
record registers on the last branch record stack. This part of the stack\r
MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF\r
/// @}\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
/// limit of 1 core active.\r
///\r
- UINT32 Maximum1C:8;\r
+ UINT32 Maximum1C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
/// limit of 2 core active.\r
///\r
- UINT32 Maximum2C:8;\r
+ UINT32 Maximum2C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
/// limit of 3 core active.\r
///\r
- UINT32 Maximum3C:8;\r
+ UINT32 Maximum3C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
/// limit of 4 core active.\r
///\r
- UINT32 Maximum4C:8;\r
+ UINT32 Maximum4C : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
/// limit of 5 core active.\r
///\r
- UINT32 Maximum5C:8;\r
+ UINT32 Maximum5C : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
/// limit of 6 core active.\r
///\r
- UINT32 Maximum6C:8;\r
+ UINT32 Maximum6C : 8;\r
///\r
/// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
/// limit of 7 core active.\r
///\r
- UINT32 Maximum7C:8;\r
+ UINT32 Maximum7C : 8;\r
///\r
/// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
/// limit of 8 core active.\r
///\r
- UINT32 Maximum8C:8;\r
+ UINT32 Maximum8C : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. Uncore PMU global control.\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391\r
+#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL\r
///\r
/// [Bit 0] Slice 0 select.\r
///\r
- UINT32 PMI_Sel_Slice0:1;\r
+ UINT32 PMI_Sel_Slice0 : 1;\r
///\r
/// [Bit 1] Slice 1 select.\r
///\r
- UINT32 PMI_Sel_Slice1:1;\r
+ UINT32 PMI_Sel_Slice1 : 1;\r
///\r
/// [Bit 2] Slice 2 select.\r
///\r
- UINT32 PMI_Sel_Slice2:1;\r
+ UINT32 PMI_Sel_Slice2 : 1;\r
///\r
/// [Bit 3] Slice 3 select.\r
///\r
- UINT32 PMI_Sel_Slice3:1;\r
+ UINT32 PMI_Sel_Slice3 : 1;\r
///\r
/// [Bit 4] Slice 4 select.\r
///\r
- UINT32 PMI_Sel_Slice4:1;\r
- UINT32 Reserved1:14;\r
- UINT32 Reserved2:10;\r
+ UINT32 PMI_Sel_Slice4 : 1;\r
+ UINT32 Reserved1 : 14;\r
+ UINT32 Reserved2 : 10;\r
///\r
/// [Bit 29] Enable all uncore counters.\r
///\r
- UINT32 EN:1;\r
+ UINT32 EN : 1;\r
///\r
/// [Bit 30] Enable wake on PMI.\r
///\r
- UINT32 WakePMI:1;\r
+ UINT32 WakePMI : 1;\r
///\r
/// [Bit 31] Enable Freezing counter when overflow.\r
///\r
- UINT32 FREEZE:1;\r
- UINT32 Reserved3:32;\r
+ UINT32 FREEZE : 1;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
\r
-\r
/**\r
Package. Uncore PMU main status.\r
\r
///\r
/// [Bit 0] Fixed counter overflowed.\r
///\r
- UINT32 Fixed:1;\r
+ UINT32 Fixed : 1;\r
///\r
/// [Bit 1] An ARB counter overflowed.\r
///\r
- UINT32 ARB:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 ARB : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 3] A CBox counter overflowed (on any slice).\r
///\r
- UINT32 CBox:1;\r
- UINT32 Reserved2:28;\r
- UINT32 Reserved3:32;\r
+ UINT32 CBox : 1;\r
+ UINT32 Reserved2 : 28;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
\r
-\r
/**\r
Package. Uncore fixed counter control (R/W).\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394\r
+#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:20;\r
+ UINT32 Reserved1 : 20;\r
///\r
/// [Bit 20] Enable overflow propagation.\r
///\r
- UINT32 EnableOverflow:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 EnableOverflow : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 22] Enable counting.\r
///\r
- UINT32 EnableCounting:1;\r
- UINT32 Reserved3:9;\r
- UINT32 Reserved4:32;\r
+ UINT32 EnableCounting : 1;\r
+ UINT32 Reserved3 : 9;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER;\r
\r
-\r
/**\r
Package. Uncore fixed counter.\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395\r
+#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR\r
///\r
/// [Bits 31:0] Current count.\r
///\r
- UINT32 CurrentCount:32;\r
+ UINT32 CurrentCount : 32;\r
///\r
/// [Bits 47:32] Current count.\r
///\r
- UINT32 CurrentCountHi:16;\r
- UINT32 Reserved:16;\r
+ UINT32 CurrentCountHi : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER;\r
\r
-\r
/**\r
Package. Uncore C-Box configuration information (R/O).\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG\r
/// [Bits 3:0] Report the number of C-Box units with performance counters,\r
/// including processor cores and processor graphics".\r
///\r
- UINT32 CBox:4;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
+ UINT32 CBox : 4;\r
+ UINT32 Reserved1 : 28;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER;\r
\r
-\r
/**\r
Package. Uncore Arb unit, performance counter 0.\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0\r
-\r
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0\r
\r
/**\r
Package. Uncore Arb unit, performance counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1\r
-\r
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1\r
\r
/**\r
Package. Uncore Arb unit, counter 0 event select MSR.\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
-\r
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
\r
/**\r
Package. Uncore Arb unit, counter 1 event select MSR.\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
-\r
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
\r
/**\r
Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C\r
+#define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL\r
/// that should be used to decide if the package should be put into a\r
/// package C7 state.\r
///\r
- UINT32 TimeLimit:10;\r
+ UINT32 TimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
/// unit of the interrupt response time limit. The following time unit\r
/// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
/// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER;\r
\r
-\r
/**\r
Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
Domains.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A\r
-\r
+#define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A\r
\r
/**\r
Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
@endcode\r
@note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640\r
-\r
+#define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640\r
\r
/**\r
Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641\r
-\r
+#define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641\r
\r
/**\r
Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642\r
-\r
+#define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642\r
\r
/**\r
Package. Uncore C-Box 0, counter n event select MSR.\r
MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box n, unit status for counter 0-3.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 0, performance counter n.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 1, counter n event select MSR.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 1, performance counter n.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 2, counter n event select MSR.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 2, performance counter n.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 3, counter n event select MSR.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 3, performance counter n.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 4, counter n event select MSR.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 4, performance counter n.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749\r
/// @}\r
\r
-\r
/**\r
Package. MC Bank Error Configuration (R/W).\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F\r
+#define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
/// to log additional info in bits 36:32.\r
///\r
- UINT32 MemErrorLogEnable:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
+ UINT32 MemErrorLogEnable : 1;\r
+ UINT32 Reserved2 : 30;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package.\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C\r
+#define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT\r
/// counting logic for specific events requiring additional configuration,\r
/// see Table 19-17.\r
///\r
- UINT32 ENABLE_PEBS_NUM_ALT:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 ENABLE_PEBS_NUM_ALT : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER;\r
\r
-\r
/**\r
Package. Package RAPL Perf Status (R/O).\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
\r
/**\r
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
@endcode\r
@note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
-\r
+#define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
\r
/**\r
Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
-\r
+#define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
@endcode\r
@note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
-\r
+#define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
\r
/**\r
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
-\r
+#define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
\r
/**\r
Package. Uncore U-box UCLK fixed counter control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08\r
-\r
+#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08\r
\r
/**\r
Package. Uncore U-box UCLK fixed counter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09\r
-\r
+#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09\r
\r
/**\r
Package. Uncore U-box perfmon event select for U-box counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10\r
-\r
+#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10\r
\r
/**\r
Package. Uncore U-box perfmon event select for U-box counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11\r
-\r
+#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11\r
\r
/**\r
Package. Uncore U-box perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16\r
-\r
+#define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16\r
\r
/**\r
Package. Uncore U-box perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17\r
-\r
+#define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17\r
\r
/**\r
Package. Uncore PCU perfmon for PCU-box-wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24\r
\r
/**\r
Package. Uncore PCU perfmon event select for PCU counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30\r
\r
/**\r
Package. Uncore PCU perfmon event select for PCU counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31\r
\r
/**\r
Package. Uncore PCU perfmon event select for PCU counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32\r
\r
/**\r
Package. Uncore PCU perfmon event select for PCU counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33\r
\r
/**\r
Package. Uncore PCU perfmon box-wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34\r
\r
/**\r
Package. Uncore PCU perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36\r
\r
/**\r
Package. Uncore PCU perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37\r
\r
/**\r
Package. Uncore PCU perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38\r
\r
/**\r
Package. Uncore PCU perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39\r
\r
/**\r
Package. Uncore C-box 0 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13\r
\r
/**\r
Package. Uncore C-box 0 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19\r
\r
/**\r
Package. Uncore C-box 1 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33\r
\r
/**\r
Package. Uncore C-box 1 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39\r
\r
/**\r
Package. Uncore C-box 2 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53\r
\r
/**\r
Package. Uncore C-box 2 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59\r
\r
/**\r
Package. Uncore C-box 3 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73\r
\r
/**\r
Package. Uncore C-box 3 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79\r
\r
/**\r
Package. Uncore C-box 4 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93\r
\r
/**\r
Package. Uncore C-box 4 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99\r
\r
/**\r
Package. Uncore C-box 5 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3\r
\r
/**\r
Package. Uncore C-box 5 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9\r
\r
/**\r
Package. Uncore C-box 6 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3\r
\r
/**\r
Package. Uncore C-box 6 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9\r
\r
/**\r
Package. Uncore C-box 7 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3\r
\r
/**\r
Package. Uncore C-box 7 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9\r
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff