@endcode\r
@note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
**/\r
-#define MSR_SILVERMONT_PLATFORM_ID 0x00000017\r
+#define MSR_SILVERMONT_PLATFORM_ID 0x00000017\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r
///\r
- UINT32 MaximumQualifiedRatio:5;\r
- UINT32 Reserved2:19;\r
- UINT32 Reserved3:18;\r
+ UINT32 MaximumQualifiedRatio : 5;\r
+ UINT32 Reserved2 : 19;\r
+ UINT32 Reserved3 : 18;\r
///\r
/// [Bits 52:50] See Table 2-2.\r
///\r
- UINT32 PlatformId:3;\r
- UINT32 Reserved4:11;\r
+ UINT32 PlatformId : 3;\r
+ UINT32 Reserved4 : 11;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PLATFORM_ID_REGISTER;\r
\r
-\r
/**\r
Module. Processor Hard Power-On Configuration (R/W) Writes ignored.\r
\r
@endcode\r
@note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
**/\r
-#define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A\r
+#define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:32;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_EBL_CR_POWERON_REGISTER;\r
\r
-\r
/**\r
Core. SMI Counter (R/O).\r
\r
@endcode\r
@note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
**/\r
-#define MSR_SILVERMONT_SMI_COUNT 0x00000034\r
+#define MSR_SILVERMONT_SMI_COUNT 0x00000034\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT\r
/// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last\r
/// RESET.\r
///\r
- UINT32 SMICount:32;\r
- UINT32 Reserved:32;\r
+ UINT32 SMICount : 32;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_SMI_COUNT_REGISTER;\r
\r
-\r
/**\r
Core. Control Features in Intel 64 Processor (R/W). See Table 2-2.\r
\r
@endcode\r
@note MSR_SILVERMONT_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_SILVERMONT_IA32_FEATURE_CONTROL 0x0000003A\r
+#define MSR_SILVERMONT_IA32_FEATURE_CONTROL 0x0000003A\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_IA32_FEATURE_CONTROL\r
///\r
/// [Bit 0] Lock (R/WL).\r
///\r
- UINT32 Lock:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 Lock : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 2] Enable VMX outside SMX operation (R/WL).\r
///\r
- UINT32 EnableVmxOutsideSmx:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
+ UINT32 EnableVmxOutsideSmx : 1;\r
+ UINT32 Reserved2 : 29;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r
record registers on the last branch record stack. The From_IP part of the\r
MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
@{\r
**/\r
-#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040\r
-#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041\r
-#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042\r
-#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043\r
-#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044\r
-#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045\r
-#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046\r
-#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047\r
+#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040\r
+#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041\r
+#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042\r
+#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043\r
+#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044\r
+#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045\r
+#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046\r
+#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047\r
/// @}\r
\r
-\r
/**\r
Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r
record registers on the last branch record stack. The To_IP part of the\r
MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
@{\r
**/\r
-#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060\r
-#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061\r
-#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062\r
-#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063\r
-#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064\r
-#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065\r
-#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066\r
-#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067\r
+#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060\r
+#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061\r
+#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062\r
+#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063\r
+#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064\r
+#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065\r
+#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066\r
+#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067\r
/// @}\r
\r
-\r
/**\r
Module. Scalable Bus Speed(RO) This field indicates the intended scalable\r
bus clock speed for processors based on Silvermont microarchitecture:.\r
@endcode\r
@note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
**/\r
-#define MSR_SILVERMONT_FSB_FREQ 0x000000CD\r
+#define MSR_SILVERMONT_FSB_FREQ 0x000000CD\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ\r
/// 0111B: 088.9 MHz\r
/// 1000B: 087.5 MHz\r
///\r
- UINT32 ScalableBusSpeed:4;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
+ UINT32 ScalableBusSpeed : 4;\r
+ UINT32 Reserved1 : 28;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_FSB_FREQ_REGISTER;\r
\r
-\r
/**\r
Package. Platform Information: Contains power management and other model\r
specific features enumeration. See http://biosbits.org.\r
AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SILVERMONT_PLATFORM_INFO 0x000000CE\r
+#define MSR_SILVERMONT_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio\r
/// of the maximum frequency that does not require turbo. Frequency =\r
/// ratio * Scalable Bus Frequency.\r
///\r
- UINT32 MaximumNon_TurboRatio:8;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 MaximumNon_TurboRatio : 8;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PLATFORM_INFO_REGISTER;\r
\r
/**\r
@endcode\r
@note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
-#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL\r
/// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)\r
/// 100b: C4 110b: C6 111b: C7 (Silvermont only).\r
///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 Limit : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
/// IO_read instructions sent to IO register specified by\r
/// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
/// until next reset.\r
///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:16;\r
- UINT32 Reserved4:32;\r
+ UINT32 CFGLock : 1;\r
+ UINT32 Reserved3 : 16;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Module. Power Management IO Redirection in C-state (R/W) See\r
http://biosbits.org.\r
@endcode\r
@note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
**/\r
-#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4\r
+#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE\r
/// address redirection is enabled, this is the IO port address reported\r
/// to the OS/software.\r
///\r
- UINT32 Lvl2Base:16;\r
+ UINT32 Lvl2Base : 16;\r
///\r
/// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
/// maximum C-State code name to be included when IO read to MWAIT\r
/// is the max C-State to include 110b - C6 is the max C-State to include\r
/// 111b - C7 is the max C-State to include.\r
///\r
- UINT32 CStateRange:3;\r
- UINT32 Reserved1:13;\r
- UINT32 Reserved2:32;\r
+ UINT32 CStateRange : 3;\r
+ UINT32 Reserved1 : 13;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER;\r
\r
-\r
/**\r
Module.\r
\r
@endcode\r
@note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
**/\r
-#define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E\r
+#define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3\r
/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
/// Indicates if the L2 is hardware-disabled.\r
///\r
- UINT32 L2HardwareEnabled:1;\r
- UINT32 Reserved1:7;\r
+ UINT32 L2HardwareEnabled : 1;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =\r
/// Disabled (default) Until this bit is set the processor will not\r
/// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
///\r
- UINT32 L2Enabled:1;\r
- UINT32 Reserved2:14;\r
+ UINT32 L2Enabled : 1;\r
+ UINT32 Reserved2 : 14;\r
///\r
/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
///\r
- UINT32 L2NotPresent:1;\r
- UINT32 Reserved3:8;\r
- UINT32 Reserved4:32;\r
+ UINT32 L2NotPresent : 1;\r
+ UINT32 Reserved3 : 8;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_BBL_CR_CTL3_REGISTER;\r
\r
-\r
/**\r
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
handler to handle unsuccessful read of this MSR.\r
@endcode\r
@note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
**/\r
-#define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C\r
+#define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG\r
/// 01b, AES instruction can be mis-configured if a privileged agent\r
/// unintentionally writes 11b.\r
///\r
- UINT32 AESConfiguration:2;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 AESConfiguration : 2;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_FEATURE_CONFIG_REGISTER;\r
\r
-\r
/**\r
Enable Misc. Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE\r
///\r
/// [Bit 0] Core. Fast-Strings Enable See Table 2-2.\r
///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 FastStrings : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See\r
/// Table 2-2. Default value is 0.\r
///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 AutomaticThermalControlCircuit : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:3;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved3 : 3;\r
///\r
/// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 2-2.\r
///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved4:3;\r
+ UINT32 PEBS : 1;\r
+ UINT32 Reserved4 : 3;\r
///\r
/// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
/// Table 2-2.\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved6:3;\r
+ UINT32 MONITOR : 1;\r
+ UINT32 Reserved6 : 3;\r
///\r
/// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
+ UINT32 LimitCpuidMaxval : 1;\r
///\r
/// [Bit 23] Module. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
+ UINT32 xTPR_Message_Disable : 1;\r
+ UINT32 Reserved7 : 8;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:3;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved9 : 3;\r
///\r
/// [Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors\r
/// that support Intel Turbo Boost Technology, the turbo mode feature is\r
/// in the processor. If power-on default value is 0, turbo mode is not\r
/// available.\r
///\r
- UINT32 TurboModeDisable:1;\r
- UINT32 Reserved10:25;\r
+ UINT32 TurboModeDisable : 1;\r
+ UINT32 Reserved10 : 25;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Package.\r
\r
@endcode\r
@note MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
**/\r
-#define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2\r
+#define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bits 23:16] Temperature Target (R) The default thermal throttling or\r
/// PROCHOT# activation temperature in degree C, The effective temperature\r
/// for thermal throttling or PROCHOT# activation is "Temperature Target"\r
/// + "Target Offset".\r
///\r
- UINT32 TemperatureTarget:8;\r
+ UINT32 TemperatureTarget : 8;\r
///\r
/// [Bits 29:24] Target Offset (R/W) Specifies an offset in degrees C to\r
/// adjust the throttling and PROCHOT# activation temperature from the\r
/// default target specified in TEMPERATURE_TARGET (bits 23:16).\r
///\r
- UINT32 TargetOffset:6;\r
- UINT32 Reserved2:2;\r
- UINT32 Reserved3:32;\r
+ UINT32 TargetOffset : 6;\r
+ UINT32 Reserved2 : 2;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER;\r
\r
-\r
/**\r
Miscellaneous Feature Control (R/W).\r
\r
@endcode\r
@note MSR_SILVERMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_SILVERMONT_MISC_FEATURE_CONTROL 0x000001A4\r
+#define MSR_SILVERMONT_MISC_FEATURE_CONTROL 0x000001A4\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_MISC_FEATURE_CONTROL\r
/// L2 hardware prefetcher, which fetches additional lines of code or data\r
/// into the L2 cache.\r
///\r
- UINT32 L2HardwarePrefetcherDisable:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 L2HardwarePrefetcherDisable : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
/// the L1 data cache prefetcher, which fetches the next cache line into\r
/// L1 data cache.\r
///\r
- UINT32 DCUHardwarePrefetcherDisable:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
+ UINT32 DCUHardwarePrefetcherDisable : 1;\r
+ UINT32 Reserved2 : 29;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Module. Offcore Response Event Select Register (R/W).\r
\r
@endcode\r
@note MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
**/\r
-#define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6\r
-\r
+#define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6\r
\r
/**\r
Module. Offcore Response Event Select Register (R/W).\r
@endcode\r
@note MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
**/\r
-#define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7\r
-\r
+#define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7\r
\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode (RW).\r
@endcode\r
@note MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
/// limit of 1 core active.\r
///\r
- UINT32 Maximum1C:8;\r
+ UINT32 Maximum1C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
/// limit of 2 core active.\r
///\r
- UINT32 Maximum2C:8;\r
+ UINT32 Maximum2C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
/// limit of 3 core active.\r
///\r
- UINT32 Maximum3C:8;\r
+ UINT32 Maximum3C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
/// limit of 4 core active.\r
///\r
- UINT32 Maximum4C:8;\r
+ UINT32 Maximum4C : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
/// limit of 5 core active.\r
///\r
- UINT32 Maximum5C:8;\r
+ UINT32 Maximum5C : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
/// limit of 6 core active.\r
///\r
- UINT32 Maximum6C:8;\r
+ UINT32 Maximum6C : 8;\r
///\r
/// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
/// limit of 7 core active.\r
///\r
- UINT32 Maximum7C:8;\r
+ UINT32 Maximum7C : 8;\r
///\r
/// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
/// limit of 8 core active.\r
///\r
- UINT32 Maximum8C:8;\r
+ UINT32 Maximum8C : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r
"Filtering of Last Branch Records.".\r
@endcode\r
@note MSR_SILVERMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
**/\r
-#define MSR_SILVERMONT_LBR_SELECT 0x000001C8\r
+#define MSR_SILVERMONT_LBR_SELECT 0x000001C8\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_LBR_SELECT\r
///\r
/// [Bit 0] CPL_EQ_0.\r
///\r
- UINT32 CPL_EQ_0:1;\r
+ UINT32 CPL_EQ_0 : 1;\r
///\r
/// [Bit 1] CPL_NEQ_0.\r
///\r
- UINT32 CPL_NEQ_0:1;\r
+ UINT32 CPL_NEQ_0 : 1;\r
///\r
/// [Bit 2] JCC.\r
///\r
- UINT32 JCC:1;\r
+ UINT32 JCC : 1;\r
///\r
/// [Bit 3] NEAR_REL_CALL.\r
///\r
- UINT32 NEAR_REL_CALL:1;\r
+ UINT32 NEAR_REL_CALL : 1;\r
///\r
/// [Bit 4] NEAR_IND_CALL.\r
///\r
- UINT32 NEAR_IND_CALL:1;\r
+ UINT32 NEAR_IND_CALL : 1;\r
///\r
/// [Bit 5] NEAR_RET.\r
///\r
- UINT32 NEAR_RET:1;\r
+ UINT32 NEAR_RET : 1;\r
///\r
/// [Bit 6] NEAR_IND_JMP.\r
///\r
- UINT32 NEAR_IND_JMP:1;\r
+ UINT32 NEAR_IND_JMP : 1;\r
///\r
/// [Bit 7] NEAR_REL_JMP.\r
///\r
- UINT32 NEAR_REL_JMP:1;\r
+ UINT32 NEAR_REL_JMP : 1;\r
///\r
/// [Bit 8] FAR_BRANCH.\r
///\r
- UINT32 FAR_BRANCH:1;\r
- UINT32 Reserved1:23;\r
- UINT32 Reserved2:32;\r
+ UINT32 FAR_BRANCH : 1;\r
+ UINT32 Reserved1 : 23;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_LBR_SELECT_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that\r
points to the MSR containing the most recent branch record. See\r
@endcode\r
@note MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Core. Last Exception Record From Linear IP (R) Contains a pointer to the\r
@endcode\r
@note MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
-#define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD\r
-\r
+#define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD\r
\r
/**\r
Core. Last Exception Record To Linear IP (R) This area contains a pointer\r
@endcode\r
@note MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
-#define MSR_SILVERMONT_LER_TO_LIP 0x000001DE\r
-\r
+#define MSR_SILVERMONT_LER_TO_LIP 0x000001DE\r
\r
/**\r
Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
@endcode\r
@note MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1\r
+#define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE\r
///\r
/// [Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W).\r
///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 PEBS : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
@endcode\r
@note MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA\r
-\r
+#define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD\r
-\r
+#define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD\r
\r
/**\r
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r
@endcode\r
@note MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r
**/\r
-#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
-\r
+#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
\r
/**\r
Core. Capability Reporting Register of VM-Function Controls (R/O) See Table\r
@endcode\r
@note MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.\r
**/\r
-#define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491\r
-\r
+#define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM.\r
**/\r
-#define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660\r
-\r
+#define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660\r
\r
/**\r
Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r
@endcode\r
@note MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
-#define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606\r
+#define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT\r
/// represented by bits 3:0. Default value is 0101b, indicating power unit\r
/// is in 32 milliWatts increment.\r
///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
+ UINT32 PowerUnits : 4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 12:8] Energy Status Units. Energy related information (in\r
/// microJoules) is based on the multiplier, 2^ESU; where ESU is an\r
/// unsigned integer represented by bits 12:8. Default value is 00101b,\r
/// indicating energy unit is in 32 microJoules increment.\r
///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
+ UINT32 EnergyStatusUnits : 5;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in\r
/// one second.\r
///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
+ UINT32 TimeUnits : 4;\r
+ UINT32 Reserved3 : 12;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER;\r
\r
-\r
/**\r
Package. PKG RAPL Power Limit Control (R/W).\r
\r
@endcode\r
@note MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610\r
+#define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT\r
/// [Bits 14:0] Package Power Limit #1 (R/W) See Section 14.9.3, "Package\r
/// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8.\r
///\r
- UINT32 Limit:15;\r
+ UINT32 Limit : 15;\r
///\r
/// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package\r
/// RAPL Domain.".\r
///\r
- UINT32 Enable:1;\r
+ UINT32 Enable : 1;\r
///\r
/// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3,\r
/// "Package RAPL Domain.".\r
///\r
- UINT32 ClampingLimit:1;\r
+ UINT32 ClampingLimit : 1;\r
///\r
/// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second.\r
/// If 0 is specified in bits [23:17], defaults to 1 second window.\r
///\r
- UINT32 Time:7;\r
- UINT32 Reserved1:8;\r
- UINT32 Reserved2:32;\r
+ UINT32 Time : 7;\r
+ UINT32 Reserved1 : 8;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."\r
and MSR_RAPL_POWER_UNIT in Table 2-8.\r
@endcode\r
@note MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611\r
-\r
+#define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611\r
\r
/**\r
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains."\r
@endcode\r
@note MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion\r
@endcode\r
@note MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM.\r
**/\r
-#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668\r
-\r
+#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668\r
\r
/**\r
Package. Module C6 demotion policy config MSR. Controls module (i.e. two\r
@endcode\r
@note MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM.\r
**/\r
-#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669\r
-\r
+#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669\r
\r
/**\r
Module. Module C6 Residency Counter (R/0) Note: C-state values are processor\r
@endcode\r
@note MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM.\r
**/\r
-#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664\r
-\r
+#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664\r
\r
/**\r
Package. PKG RAPL Parameter (R/0).\r
@endcode\r
@note MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
**/\r
-#define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E\r
+#define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO\r
/// The unit of this field is specified by the "Power Units" field of\r
/// MSR_RAPL_POWER_UNIT.\r
///\r
- UINT32 ThermalSpecPower:15;\r
- UINT32 Reserved1:17;\r
- UINT32 Reserved2:32;\r
+ UINT32 ThermalSpecPower : 15;\r
+ UINT32 Reserved1 : 17;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PKG_POWER_INFO_REGISTER;\r
\r
-\r
/**\r
Package. PP0 RAPL Power Limit Control (R/W).\r
\r
@endcode\r
@note MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638\r
+#define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT\r
/// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1\r
/// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.\r
///\r
- UINT32 Limit:15;\r
+ UINT32 Limit : 15;\r
///\r
/// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1\r
/// RAPL Domains.".\r
///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 Enable : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time\r
/// duration over which the average power must remain below\r
/// second time duration. 0x8: 40 second time duration. 0x9: 45 second\r
/// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.\r
///\r
- UINT32 Time:7;\r
- UINT32 Reserved2:8;\r
- UINT32 Reserved3:32;\r
+ UINT32 Time : 7;\r
+ UINT32 Reserved2 : 8;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER;\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff