@endcode\r
@note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
/// limit of 1 core active.\r
///\r
- UINT32 Maximum1C:8;\r
+ UINT32 Maximum1C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
/// limit of 2 core active.\r
///\r
- UINT32 Maximum2C:8;\r
+ UINT32 Maximum2C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
/// limit of 3 core active.\r
///\r
- UINT32 Maximum3C:8;\r
+ UINT32 Maximum3C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
/// limit of 4 core active.\r
///\r
- UINT32 Maximum4C:8;\r
- UINT32 Reserved:32;\r
+ UINT32 Maximum4C : 8;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4)\r
that points to the MSR containing the most recent branch record.\r
@endcode\r
@note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Core. Power Control Register See http://biosbits.org.\r
AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_POWER_CTL 0x000001FC\r
+#define MSR_SKYLAKE_POWER_CTL 0x000001FC\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU\r
/// to switch to the Minimum Enhanced Intel SpeedStep Technology operating\r
/// point when all execution cores enter MWAIT (C1).\r
///\r
- UINT32 C1EEnable:1;\r
- UINT32 Reserved2:17;\r
+ UINT32 C1EEnable : 1;\r
+ UINT32 Reserved2 : 17;\r
///\r
/// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit\r
/// disables the Race to Halt optimization and avoids this optimization\r
/// optimization. Default value is 1 for processors that do not support\r
/// Race to Halt optimization.\r
///\r
- UINT32 Fix_Me_1:1;\r
+ UINT32 Fix_Me_1 : 1;\r
///\r
/// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit\r
/// disables the P-States energy efficiency optimization. Default value is\r
/// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS\r
/// desired or OS maximize to the OS minimize performance setting.\r
///\r
- UINT32 DisableEnergyEfficiencyOptimization:1;\r
- UINT32 Reserved3:11;\r
- UINT32 Reserved4:32;\r
+ UINT32 DisableEnergyEfficiencyOptimization : 1;\r
+ UINT32 Reserved3 : 11;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_POWER_CTL_REGISTER;\r
\r
-\r
/**\r
Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r
CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r
@endcode\r
@note MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300\r
+#define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300\r
\r
//\r
// Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the SDM.\r
//\r
-#define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0\r
+#define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0\r
+\r
/**\r
Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r
CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r
@endcode\r
@note MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301\r
+#define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301\r
\r
//\r
// Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the SDM.\r
//\r
-#define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1\r
-\r
+#define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1\r
\r
/**\r
See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r
@endcode\r
@note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
+#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS\r
///\r
/// [Bit 0] Thread. Ovf_PMC0.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Thread. Ovf_PMC1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Thread. Ovf_PMC2.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Thread. Ovf_PMC3.\r
///\r
- UINT32 Ovf_PMC3:1;\r
+ UINT32 Ovf_PMC3 : 1;\r
///\r
/// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
///\r
- UINT32 Ovf_PMC4:1;\r
+ UINT32 Ovf_PMC4 : 1;\r
///\r
/// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
///\r
- UINT32 Ovf_PMC5:1;\r
+ UINT32 Ovf_PMC5 : 1;\r
///\r
/// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
///\r
- UINT32 Ovf_PMC6:1;\r
+ UINT32 Ovf_PMC6 : 1;\r
///\r
/// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
///\r
- UINT32 Ovf_PMC7:1;\r
- UINT32 Reserved1:24;\r
+ UINT32 Ovf_PMC7 : 1;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bit 32] Thread. Ovf_FixedCtr0.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Thread. Ovf_FixedCtr1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Thread. Ovf_FixedCtr2.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 20;\r
///\r
/// [Bit 55] Thread. Trace_ToPA_PMI.\r
///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 Trace_ToPA_PMI : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 58] Thread. LBR_Frz.\r
///\r
- UINT32 LBR_Frz:1;\r
+ UINT32 LBR_Frz : 1;\r
///\r
/// [Bit 59] Thread. CTR_Frz.\r
///\r
- UINT32 CTR_Frz:1;\r
+ UINT32 CTR_Frz : 1;\r
///\r
/// [Bit 60] Thread. ASCI.\r
///\r
- UINT32 ASCI:1;\r
+ UINT32 ASCI : 1;\r
///\r
/// [Bit 61] Thread. Ovf_Uncore.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Thread. Ovf_BufDSSAVE.\r
///\r
- UINT32 Ovf_BufDSSAVE:1;\r
+ UINT32 Ovf_BufDSSAVE : 1;\r
///\r
/// [Bit 63] Thread. CondChgd.\r
///\r
- UINT32 CondChgd:1;\r
+ UINT32 CondChgd : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
\r
-\r
/**\r
See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r
Version 4.".\r
@endcode\r
@note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
**/\r
-#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
+#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
\r
/**\r
MSR information returned for MSR index\r
///\r
/// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.\r
///\r
- UINT32 Ovf_PMC3:1;\r
+ UINT32 Ovf_PMC3 : 1;\r
///\r
/// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
///\r
- UINT32 Ovf_PMC4:1;\r
+ UINT32 Ovf_PMC4 : 1;\r
///\r
/// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
///\r
- UINT32 Ovf_PMC5:1;\r
+ UINT32 Ovf_PMC5 : 1;\r
///\r
/// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
///\r
- UINT32 Ovf_PMC6:1;\r
+ UINT32 Ovf_PMC6 : 1;\r
///\r
/// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
///\r
- UINT32 Ovf_PMC7:1;\r
- UINT32 Reserved1:24;\r
+ UINT32 Ovf_PMC7 : 1;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 20;\r
///\r
/// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.\r
///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 Trace_ToPA_PMI : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 58] Thread. Set 1 to clear LBR_Frz.\r
///\r
- UINT32 LBR_Frz:1;\r
+ UINT32 LBR_Frz : 1;\r
///\r
/// [Bit 59] Thread. Set 1 to clear CTR_Frz.\r
///\r
- UINT32 CTR_Frz:1;\r
+ UINT32 CTR_Frz : 1;\r
///\r
/// [Bit 60] Thread. Set 1 to clear ASCI.\r
///\r
- UINT32 ASCI:1;\r
+ UINT32 ASCI : 1;\r
///\r
/// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.\r
///\r
- UINT32 Ovf_BufDSSAVE:1;\r
+ UINT32 Ovf_BufDSSAVE : 1;\r
///\r
/// [Bit 63] Thread. Set 1 to clear CondChgd.\r
///\r
- UINT32 CondChgd:1;\r
+ UINT32 CondChgd : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
\r
-\r
/**\r
See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r
Version 4.".\r
///\r
/// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.\r
///\r
- UINT32 Ovf_PMC3:1;\r
+ UINT32 Ovf_PMC3 : 1;\r
///\r
/// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).\r
///\r
- UINT32 Ovf_PMC4:1;\r
+ UINT32 Ovf_PMC4 : 1;\r
///\r
/// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).\r
///\r
- UINT32 Ovf_PMC5:1;\r
+ UINT32 Ovf_PMC5 : 1;\r
///\r
/// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).\r
///\r
- UINT32 Ovf_PMC6:1;\r
+ UINT32 Ovf_PMC6 : 1;\r
///\r
/// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).\r
///\r
- UINT32 Ovf_PMC7:1;\r
- UINT32 Reserved1:24;\r
+ UINT32 Ovf_PMC7 : 1;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 20;\r
///\r
/// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.\r
///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 Trace_ToPA_PMI : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1.\r
///\r
- UINT32 LBR_Frz:1;\r
+ UINT32 LBR_Frz : 1;\r
///\r
/// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1.\r
///\r
- UINT32 CTR_Frz:1;\r
+ UINT32 CTR_Frz : 1;\r
///\r
/// [Bit 60] Thread. Set 1 to cause ASCI = 1.\r
///\r
- UINT32 ASCI:1;\r
+ UINT32 ASCI : 1;\r
///\r
/// [Bit 61] Thread. Set 1 to cause Ovf_Uncore.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.\r
///\r
- UINT32 Ovf_BufDSSAVE:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 Ovf_BufDSSAVE : 1;\r
+ UINT32 Reserved4 : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
\r
-\r
/**\r
Thread. FrontEnd Precise Event Condition Select (R/W).\r
\r
@endcode\r
@note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.\r
**/\r
-#define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7\r
+#define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND\r
///\r
/// [Bits 2:0] Event Code Select.\r
///\r
- UINT32 EventCodeSelect:3;\r
- UINT32 Reserved1:1;\r
+ UINT32 EventCodeSelect : 3;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 4] Event Code Select High.\r
///\r
- UINT32 EventCodeSelectHigh:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 EventCodeSelectHigh : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 19:8] IDQ_Bubble_Length Specifier.\r
///\r
- UINT32 IDQ_Bubble_Length:12;\r
+ UINT32 IDQ_Bubble_Length : 12;\r
///\r
/// [Bits 22:20] IDQ_Bubble_Width Specifier.\r
///\r
- UINT32 IDQ_Bubble_Width:3;\r
- UINT32 Reserved3:9;\r
- UINT32 Reserved4:32;\r
+ UINT32 IDQ_Bubble_Width : 3;\r
+ UINT32 Reserved3 : 9;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PEBS_FRONTEND_REGISTER;\r
\r
-\r
/**\r
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
Domains.".\r
@endcode\r
@note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both\r
@endcode\r
@note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.\r
**/\r
-#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D\r
+#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER\r
/// delivery means. The energy units are specified in the\r
/// MSR_RAPL_POWER_UNIT.Enery_Status_Unit.\r
///\r
- UINT32 TotalEnergy:32;\r
- UINT32 Reserved:32;\r
+ UINT32 TotalEnergy : 32;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER;\r
\r
-\r
/**\r
Thread. Productive Performance Count. (R/O). Hardware's view of workload\r
scalability. See Section 14.4.5.1.\r
@endcode\r
@note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.\r
**/\r
-#define MSR_SKYLAKE_PPERF 0x0000064E\r
-\r
+#define MSR_SKYLAKE_PPERF 0x0000064E\r
\r
/**\r
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
@endcode\r
@note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
**/\r
-#define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F\r
+#define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS\r
/// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
/// operating system request due to assertion of external PROCHOT.\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
/// operating system request due to a thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 ThermalStatus : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 4] Residency State Regulation Status (R0) When set, frequency is\r
/// reduced below the operating system request due to residency state\r
/// regulation limit.\r
///\r
- UINT32 ResidencyStateRegulationStatus:1;\r
+ UINT32 ResidencyStateRegulationStatus : 1;\r
///\r
/// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
/// is reduced below the operating system request due to Running Average\r
/// Thermal Limit (RATL).\r
///\r
- UINT32 RunningAverageThermalLimitStatus:1;\r
+ UINT32 RunningAverageThermalLimitStatus : 1;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
/// below the operating system request due to a thermal alert from a\r
/// processor Voltage Regulator (VR).\r
///\r
- UINT32 VRThermAlertStatus:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
///\r
/// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is\r
/// reduced below the operating system request due to VR thermal design\r
/// current limit.\r
///\r
- UINT32 VRThermDesignCurrentStatus:1;\r
+ UINT32 VRThermDesignCurrentStatus : 1;\r
///\r
/// [Bit 8] Other Status (R0) When set, frequency is reduced below the\r
/// operating system request due to electrical or other constraints.\r
///\r
- UINT32 OtherStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 OtherStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
/// set, frequency is reduced below the operating system request due to\r
/// package/platform-level power limiting PL1.\r
///\r
- UINT32 PL1Status:1;\r
+ UINT32 PL1Status : 1;\r
///\r
/// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
/// set, frequency is reduced below the operating system request due to\r
/// package/platform-level power limiting PL2/PL3.\r
///\r
- UINT32 PL2Status:1;\r
+ UINT32 PL2Status : 1;\r
///\r
/// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced\r
/// below the operating system request due to multi-core turbo limits.\r
///\r
- UINT32 MaxTurboLimitStatus:1;\r
+ UINT32 MaxTurboLimitStatus : 1;\r
///\r
/// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
/// is reduced below the operating system request due to Turbo transition\r
/// attenuation. This prevents performance degradation due to frequent\r
/// operating ratio changes.\r
///\r
- UINT32 TurboTransitionAttenuationStatus:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 TurboTransitionAttenuationStatus : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved4:2;\r
+ UINT32 ThermalLog : 1;\r
+ UINT32 Reserved4 : 2;\r
///\r
/// [Bit 20] Residency State Regulation Log When set, indicates that the\r
/// Residency State Regulation Status bit has asserted since the log bit\r
/// was last cleared. This log bit will remain set until cleared by\r
/// software writing 0.\r
///\r
- UINT32 ResidencyStateRegulationLog:1;\r
+ UINT32 ResidencyStateRegulationLog : 1;\r
///\r
/// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
/// the RATL Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 RunningAverageThermalLimitLog:1;\r
+ UINT32 RunningAverageThermalLimitLog : 1;\r
///\r
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
+ UINT32 VRThermAlertLog : 1;\r
///\r
/// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
/// VR TDC Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermalDesignCurrentLog:1;\r
+ UINT32 VRThermalDesignCurrentLog : 1;\r
///\r
/// [Bit 24] Other Log When set, indicates that the Other Status bit has\r
/// asserted since the log bit was last cleared. This log bit will remain\r
/// set until cleared by software writing 0.\r
///\r
- UINT32 OtherLog:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 OtherLog : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
/// indicates that the Package or Platform Level PL1 Power Limiting Status\r
/// bit has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PL1Log:1;\r
+ UINT32 PL1Log : 1;\r
///\r
/// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
/// indicates that the Package or Platform Level PL2/PL3 Power Limiting\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 PL2Log:1;\r
+ UINT32 PL2Log : 1;\r
///\r
/// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
/// Limit Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 MaxTurboLimitLog:1;\r
+ UINT32 MaxTurboLimitLog : 1;\r
///\r
/// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
/// Turbo Transition Attenuation Status bit has asserted since the log bit\r
/// was last cleared. This log bit will remain set until cleared by\r
/// software writing 0.\r
///\r
- UINT32 TurboTransitionAttenuationLog:1;\r
- UINT32 Reserved6:2;\r
- UINT32 Reserved7:32;\r
+ UINT32 TurboTransitionAttenuationLog : 1;\r
+ UINT32 Reserved6 : 2;\r
+ UINT32 Reserved7 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
Package. HDC Configuration (R/W)..\r
\r
@endcode\r
@note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.\r
**/\r
-#define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652\r
+#define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG\r
/// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for\r
/// MSR_PKG_HDC_DEEP_RESIDENCY.\r
///\r
- UINT32 PKG_Cx_Monitor:3;\r
- UINT32 Reserved1:29;\r
- UINT32 Reserved2:32;\r
+ UINT32 PKG_Cx_Monitor : 3;\r
+ UINT32 Reserved1 : 29;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER;\r
\r
-\r
/**\r
Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.\r
\r
@endcode\r
@note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.\r
**/\r
-#define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653\r
-\r
+#define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653\r
\r
/**\r
Package. Accumulate the cycles the package was in C2 state and at least one\r
@endcode\r
@note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.\r
**/\r
-#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655\r
-\r
+#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655\r
\r
/**\r
Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.\r
@endcode\r
@note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.\r
**/\r
-#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656\r
-\r
+#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656\r
\r
/**\r
Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate\r
@endcode\r
@note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658\r
-\r
+#define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658\r
\r
/**\r
Package. Any Core C0 Residency. (R/O). Increment at the same rate as the\r
@endcode\r
@note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_ANY_CORE_C0 0x00000659\r
-\r
+#define MSR_SKYLAKE_ANY_CORE_C0 0x00000659\r
\r
/**\r
Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate\r
@endcode\r
@note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A\r
-\r
+#define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A\r
\r
/**\r
Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment\r
@endcode\r
@note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B\r
-\r
+#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B\r
\r
/**\r
Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to\r
@endcode\r
@note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C\r
+#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT\r
/// Power (TDP) and varies with product skus. The unit is specified in\r
/// MSR_RAPLPOWER_UNIT.\r
///\r
- UINT32 PlatformPowerLimit1:15;\r
+ UINT32 PlatformPowerLimit1 : 15;\r
///\r
/// [Bit 15] Enable Platform Power Limit #1. When set, enables the\r
/// processor to apply control policy such that the platform power does\r
/// not exceed Platform Power limit #1 over the time window specified by\r
/// Power Limit #1 Time Window.\r
///\r
- UINT32 EnablePlatformPowerLimit1:1;\r
+ UINT32 EnablePlatformPowerLimit1 : 1;\r
///\r
/// [Bit 16] Platform Clamping Limitation #1. When set, allows the\r
/// processor to go below the OS requested P states in order to maintain\r
/// the power below specified Platform Power Limit #1 value. This bit is\r
/// writeable only when CPUID (EAX=6):EAX[4] is set.\r
///\r
- UINT32 PlatformClampingLimitation1:1;\r
+ UINT32 PlatformClampingLimitation1 : 1;\r
///\r
/// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the\r
/// duration of the time window over which Platform Power Limit 1 value\r
/// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH,\r
/// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].\r
///\r
- UINT32 Time:7;\r
- UINT32 Reserved1:8;\r
+ UINT32 Time : 7;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 46:32] Platform Power Limit #2. Average Power limit value which\r
/// the platform must not exceed over the Short Duration time window\r
/// chosen by the processor. The recommended default value is 1.25 times\r
/// the Long Duration Power Limit (i.e. Platform Power Limit # 1).\r
///\r
- UINT32 PlatformPowerLimit2:15;\r
+ UINT32 PlatformPowerLimit2 : 15;\r
///\r
/// [Bit 47] Enable Platform Power Limit #2. When set, enables the\r
/// processor to apply control policy such that the platform power does\r
/// not exceed Platform Power limit #2 over the Short Duration time window.\r
///\r
- UINT32 EnablePlatformPowerLimit2:1;\r
+ UINT32 EnablePlatformPowerLimit2 : 1;\r
///\r
/// [Bit 48] Platform Clamping Limitation #2. When set, allows the\r
/// processor to go below the OS requested P states in order to maintain\r
/// the power below specified Platform Power Limit #2 value.\r
///\r
- UINT32 PlatformClampingLimitation2:1;\r
- UINT32 Reserved2:14;\r
+ UINT32 PlatformClampingLimitation2 : 1;\r
+ UINT32 Reserved2 : 14;\r
///\r
/// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR\r
/// until system RESET.\r
///\r
- UINT32 Lock:1;\r
+ UINT32 Lock : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER;\r
\r
-\r
/**\r
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last\r
branch record registers on the last branch record stack. This part of the\r
MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.\r
@{\r
**/\r
-#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690\r
-#define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691\r
-#define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692\r
-#define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693\r
-#define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694\r
-#define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695\r
-#define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696\r
-#define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697\r
-#define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698\r
-#define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699\r
-#define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A\r
-#define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B\r
-#define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C\r
-#define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D\r
-#define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E\r
-#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F\r
+#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690\r
+#define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691\r
+#define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692\r
+#define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693\r
+#define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694\r
+#define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695\r
+#define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696\r
+#define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697\r
+#define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698\r
+#define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699\r
+#define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A\r
+#define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B\r
+#define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C\r
+#define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D\r
+#define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E\r
+#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F\r
/// @}\r
\r
-\r
/**\r
Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)\r
(frequency refers to processor graphics frequency).\r
/// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r
/// assertion of external PROCHOT.\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r
/// thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:3;\r
+ UINT32 ThermalStatus : 1;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
/// is reduced due to running average thermal limit.\r
///\r
- UINT32 RunningAverageThermalLimitStatus:1;\r
+ UINT32 RunningAverageThermalLimitStatus : 1;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r
/// to a thermal alert from a processor Voltage Regulator.\r
///\r
- UINT32 VRThermAlertStatus:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
///\r
/// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r
/// reduced due to VR TDC limit.\r
///\r
- UINT32 VRThermalDesignCurrentStatus:1;\r
+ UINT32 VRThermalDesignCurrentStatus : 1;\r
///\r
/// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r
/// electrical or other constraints.\r
///\r
- UINT32 OtherStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 OtherStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
/// set, frequency is reduced due to package/platform-level power limiting\r
/// PL1.\r
///\r
- UINT32 PL1Status:1;\r
+ UINT32 PL1Status : 1;\r
///\r
/// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
/// set, frequency is reduced due to package/platform-level power limiting\r
/// PL2/PL3.\r
///\r
- UINT32 PL2Status:1;\r
+ UINT32 PL2Status : 1;\r
///\r
/// [Bit 12] Inefficient Operation Status (R0) When set, processor\r
/// graphics frequency is operating below target frequency.\r
///\r
- UINT32 InefficientOperationStatus:1;\r
- UINT32 Reserved3:3;\r
+ UINT32 InefficientOperationStatus : 1;\r
+ UINT32 Reserved3 : 3;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved4:3;\r
+ UINT32 ThermalLog : 1;\r
+ UINT32 Reserved4 : 3;\r
///\r
/// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
/// the RATL Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 RunningAverageThermalLimitLog:1;\r
+ UINT32 RunningAverageThermalLimitLog : 1;\r
///\r
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
+ UINT32 VRThermAlertLog : 1;\r
///\r
/// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
/// VR Therm Alert Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 VRThermalDesignCurrentLog:1;\r
+ UINT32 VRThermalDesignCurrentLog : 1;\r
///\r
/// [Bit 24] Other Log When set, indicates that the OTHER Status bit has\r
/// asserted since the log bit was last cleared. This log bit will remain\r
/// set until cleared by software writing 0.\r
///\r
- UINT32 OtherLog:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 OtherLog : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
/// indicates that the Package/Platform Level PL1 Power Limiting Status\r
/// bit has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PL1Log:1;\r
+ UINT32 PL1Log : 1;\r
///\r
/// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
/// indicates that the Package/Platform Level PL2 Power Limiting Status\r
/// bit has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PL2Log:1;\r
+ UINT32 PL2Log : 1;\r
///\r
/// [Bit 28] Inefficient Operation Log When set, indicates that the\r
/// Inefficient Operation Status bit has asserted since the log bit was\r
/// last cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 InefficientOperationLog:1;\r
- UINT32 Reserved6:3;\r
- UINT32 Reserved7:32;\r
+ UINT32 InefficientOperationLog : 1;\r
+ UINT32 Reserved6 : 3;\r
+ UINT32 Reserved7 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)\r
(frequency refers to ring interconnect in the uncore).\r
@endcode\r
@note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.\r
**/\r
-#define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1\r
+#define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS\r
/// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r
/// assertion of external PROCHOT.\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r
/// thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:3;\r
+ UINT32 ThermalStatus : 1;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
/// is reduced due to running average thermal limit.\r
///\r
- UINT32 RunningAverageThermalLimitStatus:1;\r
+ UINT32 RunningAverageThermalLimitStatus : 1;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r
/// to a thermal alert from a processor Voltage Regulator.\r
///\r
- UINT32 VRThermAlertStatus:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
///\r
/// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r
/// reduced due to VR TDC limit.\r
///\r
- UINT32 VRThermalDesignCurrentStatus:1;\r
+ UINT32 VRThermalDesignCurrentStatus : 1;\r
///\r
/// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r
/// electrical or other constraints.\r
///\r
- UINT32 OtherStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 OtherStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
/// set, frequency is reduced due to package/Platform-level power limiting\r
/// PL1.\r
///\r
- UINT32 PL1Status:1;\r
+ UINT32 PL1Status : 1;\r
///\r
/// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
/// set, frequency is reduced due to package/Platform-level power limiting\r
/// PL2/PL3.\r
///\r
- UINT32 PL2Status:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 PL2Status : 1;\r
+ UINT32 Reserved3 : 4;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved4:3;\r
+ UINT32 ThermalLog : 1;\r
+ UINT32 Reserved4 : 3;\r
///\r
/// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
/// the RATL Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 RunningAverageThermalLimitLog:1;\r
+ UINT32 RunningAverageThermalLimitLog : 1;\r
///\r
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
+ UINT32 VRThermAlertLog : 1;\r
///\r
/// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
/// VR Therm Alert Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 VRThermalDesignCurrentLog:1;\r
+ UINT32 VRThermalDesignCurrentLog : 1;\r
///\r
/// [Bit 24] Other Log When set, indicates that the OTHER Status bit has\r
/// asserted since the log bit was last cleared. This log bit will remain\r
/// set until cleared by software writing 0.\r
///\r
- UINT32 OtherLog:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 OtherLog : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
/// indicates that the Package/Platform Level PL1 Power Limiting Status\r
/// bit has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PL1Log:1;\r
+ UINT32 PL1Log : 1;\r
///\r
/// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
/// indicates that the Package/Platform Level PL2 Power Limiting Status\r
/// bit has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PL2Log:1;\r
- UINT32 Reserved6:4;\r
- UINT32 Reserved7:32;\r
+ UINT32 PL2Log : 1;\r
+ UINT32 Reserved6 : 4;\r
+ UINT32 Reserved7 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch\r
record registers on the last branch record stack. This part of the stack\r
MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.\r
@{\r
**/\r
-#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0\r
-#define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1\r
-#define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2\r
-#define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3\r
-#define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4\r
-#define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5\r
-#define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6\r
-#define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7\r
-#define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8\r
-#define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9\r
-#define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA\r
-#define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB\r
-#define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC\r
-#define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD\r
-#define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE\r
-#define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF\r
+#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0\r
+#define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1\r
+#define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2\r
+#define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3\r
+#define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4\r
+#define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5\r
+#define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6\r
+#define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7\r
+#define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8\r
+#define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9\r
+#define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA\r
+#define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB\r
+#define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC\r
+#define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD\r
+#define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE\r
+#define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF\r
/// @}\r
\r
-\r
/**\r
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet\r
of last branch record registers on the last branch record stack. This part\r
MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.\r
@{\r
**/\r
-#define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0\r
-#define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1\r
-#define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2\r
-#define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3\r
-#define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4\r
-#define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5\r
-#define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6\r
-#define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7\r
-#define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8\r
-#define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9\r
-#define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA\r
-#define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB\r
-#define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC\r
-#define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD\r
-#define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE\r
-#define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF\r
-#define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0\r
-#define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1\r
-#define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2\r
-#define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3\r
-#define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4\r
-#define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5\r
-#define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6\r
-#define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7\r
-#define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8\r
-#define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9\r
-#define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA\r
-#define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB\r
-#define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC\r
-#define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD\r
-#define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE\r
-#define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF\r
+#define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0\r
+#define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1\r
+#define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2\r
+#define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3\r
+#define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4\r
+#define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5\r
+#define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6\r
+#define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7\r
+#define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8\r
+#define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9\r
+#define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA\r
+#define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB\r
+#define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC\r
+#define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD\r
+#define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE\r
+#define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF\r
+#define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0\r
+#define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1\r
+#define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2\r
+#define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3\r
+#define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4\r
+#define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5\r
+#define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6\r
+#define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7\r
+#define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8\r
+#define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9\r
+#define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA\r
+#define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB\r
+#define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC\r
+#define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD\r
+#define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE\r
+#define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF\r
/// @}\r
\r
-\r
/**\r
Package. Uncore fixed counter control (R/W).\r
\r
@endcode\r
@note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394\r
+#define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:20;\r
+ UINT32 Reserved1 : 20;\r
///\r
/// [Bit 20] Enable overflow propagation.\r
///\r
- UINT32 EnableOverflow:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 EnableOverflow : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 22] Enable counting.\r
///\r
- UINT32 EnableCounting:1;\r
- UINT32 Reserved3:9;\r
- UINT32 Reserved4:32;\r
+ UINT32 EnableCounting : 1;\r
+ UINT32 Reserved3 : 9;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER;\r
\r
-\r
/**\r
Package. Uncore fixed counter.\r
\r
@endcode\r
@note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395\r
+#define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR\r
///\r
/// [Bits 31:0] Current count.\r
///\r
- UINT32 CurrentCount:32;\r
+ UINT32 CurrentCount : 32;\r
///\r
/// [Bits 43:32] Current count.\r
///\r
- UINT32 CurrentCountHi:12;\r
- UINT32 Reserved:20;\r
+ UINT32 CurrentCountHi : 12;\r
+ UINT32 Reserved : 20;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER;\r
\r
-\r
/**\r
Package. Uncore C-Box configuration information (R/O).\r
\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396\r
+#define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG\r
/// [Bits 3:0] Specifies the number of C-Box units with programmable\r
/// counters (including processor cores and processor graphics),.\r
///\r
- UINT32 CBox:4;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
+ UINT32 CBox : 4;\r
+ UINT32 Reserved1 : 28;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER;\r
\r
-\r
/**\r
Package. Uncore Arb unit, performance counter 0.\r
\r
@endcode\r
@note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0\r
-\r
+#define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0\r
\r
/**\r
Package. Uncore Arb unit, performance counter 1.\r
@endcode\r
@note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1\r
-\r
+#define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1\r
\r
/**\r
Package. Uncore Arb unit, counter 0 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
-\r
+#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
\r
/**\r
Package. Uncore Arb unit, counter 1 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
-\r
+#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
\r
/**\r
Package. Uncore C-Box 0, counter 0 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
\r
/**\r
Package. Uncore C-Box 0, counter 1 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
\r
/**\r
Package. Uncore C-Box 0, performance counter 0.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706\r
\r
/**\r
Package. Uncore C-Box 0, performance counter 1.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707\r
\r
/**\r
Package. Uncore C-Box 1, counter 0 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
\r
/**\r
Package. Uncore C-Box 1, counter 1 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
\r
/**\r
Package. Uncore C-Box 1, performance counter 0.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716\r
\r
/**\r
Package. Uncore C-Box 1, performance counter 1.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717\r
\r
/**\r
Package. Uncore C-Box 2, counter 0 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
\r
/**\r
Package. Uncore C-Box 2, counter 1 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
\r
/**\r
Package. Uncore C-Box 2, performance counter 0.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726\r
\r
/**\r
Package. Uncore C-Box 2, performance counter 1.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727\r
\r
/**\r
Package. Uncore C-Box 3, counter 0 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
\r
/**\r
Package. Uncore C-Box 3, counter 1 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
\r
/**\r
Package. Uncore C-Box 3, performance counter 0.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736\r
\r
/**\r
Package. Uncore C-Box 3, performance counter 1.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737\r
\r
/**\r
Package. Uncore PMU global control.\r
@endcode\r
@note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01\r
+#define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL\r
///\r
/// [Bit 0] Slice 0 select.\r
///\r
- UINT32 PMI_Sel_Slice0:1;\r
+ UINT32 PMI_Sel_Slice0 : 1;\r
///\r
/// [Bit 1] Slice 1 select.\r
///\r
- UINT32 PMI_Sel_Slice1:1;\r
+ UINT32 PMI_Sel_Slice1 : 1;\r
///\r
/// [Bit 2] Slice 2 select.\r
///\r
- UINT32 PMI_Sel_Slice2:1;\r
+ UINT32 PMI_Sel_Slice2 : 1;\r
///\r
/// [Bit 3] Slice 3 select.\r
///\r
- UINT32 PMI_Sel_Slice3:1;\r
+ UINT32 PMI_Sel_Slice3 : 1;\r
///\r
/// [Bit 4] Slice 4select.\r
///\r
- UINT32 PMI_Sel_Slice4:1;\r
- UINT32 Reserved1:14;\r
- UINT32 Reserved2:10;\r
+ UINT32 PMI_Sel_Slice4 : 1;\r
+ UINT32 Reserved1 : 14;\r
+ UINT32 Reserved2 : 10;\r
///\r
/// [Bit 29] Enable all uncore counters.\r
///\r
- UINT32 EN:1;\r
+ UINT32 EN : 1;\r
///\r
/// [Bit 30] Enable wake on PMI.\r
///\r
- UINT32 WakePMI:1;\r
+ UINT32 WakePMI : 1;\r
///\r
/// [Bit 31] Enable Freezing counter when overflow.\r
///\r
- UINT32 FREEZE:1;\r
- UINT32 Reserved3:32;\r
+ UINT32 FREEZE : 1;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
\r
-\r
/**\r
Package. Uncore PMU main status.\r
\r
@endcode\r
@note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02\r
+#define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS\r
///\r
/// [Bit 0] Fixed counter overflowed.\r
///\r
- UINT32 Fixed:1;\r
+ UINT32 Fixed : 1;\r
///\r
/// [Bit 1] An ARB counter overflowed.\r
///\r
- UINT32 ARB:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 ARB : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 3] A CBox counter overflowed (on any slice).\r
///\r
- UINT32 CBox:1;\r
- UINT32 Reserved2:28;\r
- UINT32 Reserved3:32;\r
+ UINT32 CBox : 1;\r
+ UINT32 Reserved2 : 28;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
\r
-\r
/**\r
Package. NPK Address Used by AET Messages (R/W).\r
\r
AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080\r
+#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080\r
\r
/**\r
MSR information returned for MSR index\r
/// bit has to be set in order for the AET packets to be directed to NPK\r
/// MMIO.\r
///\r
- UINT32 Fix_Me_1:1;\r
- UINT32 Reserved:17;\r
+ UINT32 Fix_Me_1 : 1;\r
+ UINT32 Reserved : 17;\r
///\r
/// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.\r
///\r
- UINT32 ACPIBAR_BASE_ADDRESS:14;\r
+ UINT32 ACPIBAR_BASE_ADDRESS : 14;\r
///\r
/// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.\r
///\r
- UINT32 Fix_Me_2:32;\r
+ UINT32 Fix_Me_2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER;\r
\r
-\r
/**\r
Core. Processor Reserved Memory Range Register - Physical Base Control\r
Register (R/W).\r
AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4\r
+#define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_BASE\r
///\r
/// [Bits 2:0] MemType PRMRR BASE MemType.\r
///\r
- UINT32 MemTypePRMRRBASEMemType:3;\r
- UINT32 Reserved1:9;\r
+ UINT32 MemTypePRMRRBASEMemType : 3;\r
+ UINT32 Reserved1 : 9;\r
///\r
/// [Bits 31:12] Base PRMRR Base Address.\r
///\r
- UINT32 BasePRMRRBaseAddress:20;\r
+ UINT32 BasePRMRRBaseAddress : 20;\r
///\r
/// [Bits 45:32] Base PRMRR Base Address.\r
///\r
- UINT32 Fix_Me_1:14;\r
- UINT32 Reserved2:18;\r
+ UINT32 Fix_Me_1 : 14;\r
+ UINT32 Reserved2 : 18;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER;\r
\r
-\r
/**\r
Core. Processor Reserved Memory Range Register - Physical Mask Control\r
Register (R/W).\r
AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5\r
+#define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_MASK\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:10;\r
+ UINT32 Reserved1 : 10;\r
///\r
/// [Bit 10] Lock Lock bit for the PRMRR.\r
///\r
- UINT32 Fix_Me_1:1;\r
+ UINT32 Fix_Me_1 : 1;\r
///\r
/// [Bit 11] VLD Enable bit for the PRMRR.\r
///\r
- UINT32 VLD:1;\r
+ UINT32 VLD : 1;\r
///\r
/// [Bits 31:12] Mask PRMRR MASK bits.\r
///\r
- UINT32 Fix_Me_2:20;\r
+ UINT32 Fix_Me_2 : 20;\r
///\r
/// [Bits 45:32] Mask PRMRR MASK bits.\r
///\r
- UINT32 Fix_Me_3:14;\r
- UINT32 Reserved2:18;\r
+ UINT32 Fix_Me_3 : 14;\r
+ UINT32 Reserved2 : 18;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER;\r
\r
-\r
/**\r
Core. Valid PRMRR Configurations (R/W).\r
\r
AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB\r
+#define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_VALID_CONFIG\r
///\r
/// [Bit 0] 1M supported MEE size.\r
///\r
- UINT32 Fix_Me_1:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 Fix_Me_1 : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bit 5] 32M supported MEE size.\r
///\r
- UINT32 Fix_Me_2:1;\r
+ UINT32 Fix_Me_2 : 1;\r
///\r
/// [Bit 6] 64M supported MEE size.\r
///\r
- UINT32 Fix_Me_3:1;\r
+ UINT32 Fix_Me_3 : 1;\r
///\r
/// [Bit 7] 128M supported MEE size.\r
///\r
- UINT32 Fix_Me_4:1;\r
- UINT32 Reserved2:24;\r
- UINT32 Reserved3:32;\r
+ UINT32 Fix_Me_4 : 1;\r
+ UINT32 Reserved2 : 24;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER;\r
\r
-\r
/**\r
Package. (R/W) The PRMRR range is used to protect Xucode memory from\r
unauthorized reads and writes. Any IO access to this range is aborted. This\r
AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4\r
+#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:12;\r
+ UINT32 Reserved1 : 12;\r
///\r
/// [Bits 31:12] Range Base This field corresponds to bits 38:12 of the\r
/// base address memory range which is allocated to PRMRR memory.\r
///\r
- UINT32 Fix_Me_1:20;\r
+ UINT32 Fix_Me_1 : 20;\r
///\r
/// [Bits 38:32] Range Base This field corresponds to bits 38:12 of the\r
/// base address memory range which is allocated to PRMRR memory.\r
///\r
- UINT32 Fix_Me_2:7;\r
- UINT32 Reserved2:25;\r
+ UINT32 Fix_Me_2 : 7;\r
+ UINT32 Reserved2 : 25;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER;\r
\r
-\r
/**\r
Package. (R/W) This register controls the size of the PRMRR range by\r
indicating which address bits must match the PRMRR base register value.\r
AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5\r
+#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:10;\r
+ UINT32 Reserved1 : 10;\r
///\r
/// [Bit 10] Lock Setting this bit locks all writeable settings in this\r
/// register, including itself.\r
///\r
- UINT32 Fix_Me_1:1;\r
+ UINT32 Fix_Me_1 : 1;\r
///\r
/// [Bit 11] Range_En Indicates whether the PRMRR range is enabled and\r
/// valid.\r
///\r
- UINT32 Fix_Me_2:1;\r
- UINT32 Reserved2:20;\r
- UINT32 Reserved3:32;\r
+ UINT32 Fix_Me_2 : 1;\r
+ UINT32 Reserved2 : 20;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER;\r
\r
/**\r
AsmWriteMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620\r
+#define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_RING_RATIO_LIMIT\r
/// [Bits 6:0] MAX_Ratio This field is used to limit the max ratio of the\r
/// LLC/Ring.\r
///\r
- UINT32 Fix_Me_1:7;\r
- UINT32 Reserved1:1;\r
+ UINT32 Fix_Me_1 : 7;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 14:8] MIN_Ratio Writing to this field controls the minimum\r
/// possible ratio of the LLC/Ring.\r
///\r
- UINT32 Fix_Me_2:7;\r
- UINT32 Reserved2:17;\r
- UINT32 Reserved3:32;\r
+ UINT32 Fix_Me_2 : 7;\r
+ UINT32 Reserved2 : 17;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Branch Monitoring Global Control (R/W).\r
\r
AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350\r
+#define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_CTRL\r
///\r
/// [Bit 0] EnMonitoring Global enable for branch monitoring.\r
///\r
- UINT32 EnMonitoring:1;\r
+ UINT32 EnMonitoring : 1;\r
///\r
/// [Bit 1] EnExcept Enable branch monitoring event signaling on threshold\r
/// trip. The branch monitoring event handler is signaled via the existing\r
/// PMI signaling mechanism as programmed from the corresponding local\r
/// APIC LVT entry.\r
///\r
- UINT32 EnExcept:1;\r
+ UINT32 EnExcept : 1;\r
///\r
/// [Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause\r
/// the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a\r
/// triggering condition occurs and this bit is enabled.\r
///\r
- UINT32 EnLBRFrz:1;\r
+ UINT32 EnLBRFrz : 1;\r
///\r
/// [Bit 3] DisableInGuest When set to '1', branch monitoring, event\r
/// triggering and LBR freeze actions are disabled when operating at VMX\r
/// non-root operation.\r
///\r
- UINT32 DisableInGuest:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 DisableInGuest : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 -\r
/// 1023 are supported. Once the Window counter reaches the WindowSize\r
/// count both the Window Counter and all Branch Monitoring Counters are\r
/// cleared.\r
///\r
- UINT32 WindowSize:10;\r
- UINT32 Reserved2:6;\r
+ UINT32 WindowSize : 10;\r
+ UINT32 Reserved2 : 6;\r
///\r
/// [Bits 25:24] WindowCntSel Window event count select: '00 =\r
/// Instructions retired. '01 = Branch instructions retired '10 = Return\r
/// instructions retired. '11 = Indirect branch instructions retired.\r
///\r
- UINT32 WindowCntSel:2;\r
+ UINT32 WindowCntSel : 2;\r
///\r
/// [Bit 26] CntAndMode When set to '1', the overall branch monitoring\r
/// event triggering condition is true only if all enabled counters'\r
/// threshold conditions are true. When '0', the threshold tripping\r
/// condition is true if any enabled counters' threshold is true.\r
///\r
- UINT32 CntAndMode:1;\r
- UINT32 Reserved3:5;\r
- UINT32 Reserved4:32;\r
+ UINT32 CntAndMode : 1;\r
+ UINT32 Reserved3 : 5;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER;\r
\r
/**\r
AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351\r
+#define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_STATUS\r
/// Monitoring event signaling is blocked until this bit is cleared by\r
/// software.\r
///\r
- UINT32 BranchMonitoringEventSignaled:1;\r
+ UINT32 BranchMonitoringEventSignaled : 1;\r
///\r
/// [Bit 1] LBRsValid This status bit is set to '1' if the LBR state is\r
/// considered valid for sampling by branch monitoring software.\r
///\r
- UINT32 LBRsValid:1;\r
- UINT32 Reserved1:6;\r
+ UINT32 LBRsValid : 1;\r
+ UINT32 Reserved1 : 6;\r
///\r
/// [Bit 8] CntrHit0 Branch monitoring counter #0 threshold hit. This\r
/// status bit is sticky and once set requires clearing by software.\r
/// Counter operation continues independent of the state of the bit.\r
///\r
- UINT32 CntrHit0:1;\r
+ UINT32 CntrHit0 : 1;\r
///\r
/// [Bit 9] CntrHit1 Branch monitoring counter #1 threshold hit. This\r
/// status bit is sticky and once set requires clearing by software.\r
/// Counter operation continues independent of the state of the bit.\r
///\r
- UINT32 CntrHit1:1;\r
- UINT32 Reserved2:6;\r
+ UINT32 CntrHit1 : 1;\r
+ UINT32 Reserved2 : 6;\r
///\r
/// [Bits 25:16] CountWindow The current value of the window counter. The\r
/// count value is frozen on a valid branch monitoring triggering\r
/// condition. This is a 10-bit unsigned value.\r
///\r
- UINT32 CountWindow:10;\r
- UINT32 Reserved3:6;\r
+ UINT32 CountWindow : 10;\r
+ UINT32 Reserved3 : 6;\r
///\r
/// [Bits 39:32] Count0 The current value of counter 0 updated after each\r
/// occurrence of the event being counted. The count value is frozen on a\r
/// maximum value 0xFF (256). RET-CALL event counter saturate at maximum\r
/// value 0x7F (+127) and minimum value 0x80 (-128).\r
///\r
- UINT32 Count0:8;\r
+ UINT32 Count0 : 8;\r
///\r
/// [Bits 47:40] Count1 The current value of counter 1 updated after each\r
/// occurrence of the event being counted. The count value is frozen on a\r
/// maximum value 0xFF (256). RET-CALL event counter saturate at maximum\r
/// value 0x7F (+127) and minimum value 0x80 (-128).\r
///\r
- UINT32 Count1:8;\r
- UINT32 Reserved4:16;\r
+ UINT32 Count1 : 8;\r
+ UINT32 Reserved4 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER;\r
\r
-\r
/**\r
Package. Package C3 Residency Counter (R/O). Note: C-state values are\r
processor specific C-state code names, unrelated to MWAIT extension C-state\r
Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_C3_RESIDENCY);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8\r
-\r
+#define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8\r
\r
/**\r
Core. Core C1 Residency Counter (R/O). Value since last reset for the Core\r
Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C1_RESIDENCY);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660\r
-\r
+#define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660\r
\r
/**\r
Core. Core C3 Residency Counter (R/O). Will always return 0.\r
Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C3_RESIDENCY);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662\r
-\r
+#define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662\r
\r
/**\r
Package. Protected Processor Inventory Number Enable Control (R/W).\r
AsmWriteMsr64 (MSR_SKYLAKE_PPIN_CTL, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PPIN_CTL 0x0000004E\r
+#define MSR_SKYLAKE_PPIN_CTL 0x0000004E\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PPIN_CTL\r
///\r
/// [Bit 0] LockOut (R/WO) See Table 2-25.\r
///\r
- UINT32 LockOut:1;\r
+ UINT32 LockOut : 1;\r
///\r
/// [Bit 1] Enable_PPIN (R/W) See Table 2-25.\r
///\r
- UINT32 Enable_PPIN:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 Enable_PPIN : 1;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PPIN_CTL_REGISTER;\r
\r
-\r
/**\r
Package. Protected Processor Inventory Number (R/O). Protected Processor\r
Inventory Number (R/O) See Table 2-25.\r
Msr = AsmReadMsr64 (MSR_SKYLAKE_PPIN);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PPIN 0x0000004F\r
-\r
+#define MSR_SKYLAKE_PPIN 0x0000004F\r
\r
/**\r
Package. Platform Information Contains power management and other model\r
AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_INFO, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE\r
+#define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.\r
///\r
- UINT32 MaximumNon_TurboRatio:8;\r
- UINT32 Reserved2:7;\r
+ UINT32 MaximumNon_TurboRatio : 8;\r
+ UINT32 Reserved2 : 7;\r
///\r
/// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.\r
///\r
- UINT32 PPIN_CAP:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 PPIN_CAP : 1;\r
+ UINT32 Reserved3 : 4;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
/// Table 2-25.\r
///\r
- UINT32 ProgrammableRatioLimit:1;\r
+ UINT32 ProgrammableRatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
/// Table 2-25.\r
///\r
- UINT32 ProgrammableTDPLimit:1;\r
+ UINT32 ProgrammableTDPLimit : 1;\r
///\r
/// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.\r
///\r
- UINT32 ProgrammableTJOFFSET:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:8;\r
+ UINT32 ProgrammableTJOFFSET : 1;\r
+ UINT32 Reserved4 : 1;\r
+ UINT32 Reserved5 : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved6:16;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
+ UINT32 Reserved6 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PLATFORM_INFO_REGISTER;\r
\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
specific C-state code names, unrelated to MWAIT extension C-state parameters\r
AsmWriteMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL\r
/// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
/// supported by the processor are available.\r
///\r
- UINT32 C_StateLimit:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 C_StateLimit : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
///\r
- UINT32 MWAITRedirectionEnable:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 MWAITRedirectionEnable : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO).\r
///\r
- UINT32 CFGLock:1;\r
+ UINT32 CFGLock : 1;\r
///\r
/// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r
/// will convert HALT or MWAT(C1) to MWAIT(C6).\r
///\r
- UINT32 AutomaticC_StateConversionEnable:1;\r
- UINT32 Reserved3:8;\r
+ UINT32 AutomaticC_StateConversionEnable : 1;\r
+ UINT32 Reserved3 : 8;\r
///\r
/// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C3StateAutoDemotionEnable:1;\r
+ UINT32 C3StateAutoDemotionEnable : 1;\r
///\r
/// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C1StateAutoDemotionEnable:1;\r
+ UINT32 C1StateAutoDemotionEnable : 1;\r
///\r
/// [Bit 27] Enable C3 Undemotion (R/W).\r
///\r
- UINT32 EnableC3Undemotion:1;\r
+ UINT32 EnableC3Undemotion : 1;\r
///\r
/// [Bit 28] Enable C1 Undemotion (R/W).\r
///\r
- UINT32 EnableC1Undemotion:1;\r
+ UINT32 EnableC1Undemotion : 1;\r
///\r
/// [Bit 29] Package C State Demotion Enable (R/W).\r
///\r
- UINT32 CStateDemotionEnable:1;\r
+ UINT32 CStateDemotionEnable : 1;\r
///\r
/// [Bit 30] Package C State UnDemotion Enable (R/W).\r
///\r
- UINT32 CStateUnDemotionEnable:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:32;\r
+ UINT32 CStateUnDemotionEnable : 1;\r
+ UINT32 Reserved4 : 1;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Thread. Global Machine Check Capability (R/O).\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_MCG_CAP);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179\r
+#define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_IA32_MCG_CAP\r
///\r
/// [Bits 7:0] Count.\r
///\r
- UINT32 Count:8;\r
+ UINT32 Count : 8;\r
///\r
/// [Bit 8] MCG_CTL_P.\r
///\r
- UINT32 MCG_CTL_P:1;\r
+ UINT32 MCG_CTL_P : 1;\r
///\r
/// [Bit 9] MCG_EXT_P.\r
///\r
- UINT32 MCG_EXT_P:1;\r
+ UINT32 MCG_EXT_P : 1;\r
///\r
/// [Bit 10] MCP_CMCI_P.\r
///\r
- UINT32 MCP_CMCI_P:1;\r
+ UINT32 MCP_CMCI_P : 1;\r
///\r
/// [Bit 11] MCG_TES_P.\r
///\r
- UINT32 MCG_TES_P:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 MCG_TES_P : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 23:16] MCG_EXT_CNT.\r
///\r
- UINT32 MCG_EXT_CNT:8;\r
+ UINT32 MCG_EXT_CNT : 8;\r
///\r
/// [Bit 24] MCG_SER_P.\r
///\r
- UINT32 MCG_SER_P:1;\r
+ UINT32 MCG_SER_P : 1;\r
///\r
/// [Bit 25] MCG_EM_P.\r
///\r
- UINT32 MCG_EM_P:1;\r
+ UINT32 MCG_EM_P : 1;\r
///\r
/// [Bit 26] MCG_ELOG_P.\r
///\r
- UINT32 MCG_ELOG_P:1;\r
- UINT32 Reserved2:5;\r
- UINT32 Reserved3:32;\r
+ UINT32 MCG_ELOG_P : 1;\r
+ UINT32 Reserved2 : 5;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_IA32_MCG_CAP_REGISTER;\r
\r
-\r
/**\r
THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
Enhancement. Accessible only while in SMM.\r
AsmWriteMsr64 (MSR_SKYLAKE_SMM_MCA_CAP, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D\r
+#define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_SMM_MCA_CAP\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:26;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 26;\r
///\r
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
/// SMM code access restriction is supported and a host-space interface is\r
/// available to SMM handler.\r
///\r
- UINT32 SMM_Code_Access_Chk:1;\r
+ UINT32 SMM_Code_Access_Chk : 1;\r
///\r
/// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
/// SMM long flow indicator is supported and a host-space interface is\r
/// available to SMM handler.\r
///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 Long_Flow_Indication : 1;\r
+ UINT32 Reserved3 : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_SMM_MCA_CAP_REGISTER;\r
\r
-\r
/**\r
Package. Temperature Target.\r
\r
AsmWriteMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2\r
+#define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_TEMPERATURE_TARGET\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bits 23:16] Temperature Target (RO) See Table 2-25.\r
///\r
- UINT32 TemperatureTarget:8;\r
+ UINT32 TemperatureTarget : 8;\r
///\r
/// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.\r
///\r
- UINT32 TCCActivationOffset:4;\r
- UINT32 Reserved2:4;\r
- UINT32 Reserved3:32;\r
+ UINT32 TCCActivationOffset : 4;\r
+ UINT32 Reserved2 : 4;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER;\r
\r
/**\r
AsmWriteMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE\r
+#define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES\r
/// [Bits 7:0] NUMCORE_0 Defines the active core ranges for each frequency\r
/// point.\r
///\r
- UINT32 NUMCORE_0:8;\r
+ UINT32 NUMCORE_0 : 8;\r
///\r
/// [Bits 15:8] NUMCORE_1 Defines the active core ranges for each\r
/// frequency point.\r
///\r
- UINT32 NUMCORE_1:8;\r
+ UINT32 NUMCORE_1 : 8;\r
///\r
/// [Bits 23:16] NUMCORE_2 Defines the active core ranges for each\r
/// frequency point.\r
///\r
- UINT32 NUMCORE_2:8;\r
+ UINT32 NUMCORE_2 : 8;\r
///\r
/// [Bits 31:24] NUMCORE_3 Defines the active core ranges for each\r
/// frequency point.\r
///\r
- UINT32 NUMCORE_3:8;\r
+ UINT32 NUMCORE_3 : 8;\r
///\r
/// [Bits 39:32] NUMCORE_4 Defines the active core ranges for each\r
/// frequency point.\r
///\r
- UINT32 NUMCORE_4:8;\r
+ UINT32 NUMCORE_4 : 8;\r
///\r
/// [Bits 47:40] NUMCORE_5 Defines the active core ranges for each\r
/// frequency point.\r
///\r
- UINT32 NUMCORE_5:8;\r
+ UINT32 NUMCORE_5 : 8;\r
///\r
/// [Bits 55:48] NUMCORE_6 Defines the active core ranges for each\r
/// frequency point.\r
///\r
- UINT32 NUMCORE_6:8;\r
+ UINT32 NUMCORE_6 : 8;\r
///\r
/// [Bits 63:56] NUMCORE_7 Defines the active core ranges for each\r
/// frequency point.\r
///\r
- UINT32 NUMCORE_7:8;\r
+ UINT32 NUMCORE_7 : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER;\r
\r
-\r
/**\r
Package. Unit Multipliers Used in RAPL Interfaces (R/O).\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RAPL_POWER_UNIT);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606\r
+#define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_RAPL_POWER_UNIT\r
///\r
/// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
+ UINT32 PowerUnits : 4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 12:8] Package. Energy Status Units Energy related information\r
/// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
/// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
/// micro-joules).\r
///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
+ UINT32 EnergyStatusUnits : 5;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
/// Interfaces.".\r
///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
+ UINT32 TimeUnits : 4;\r
+ UINT32 Reserved3 : 12;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER;\r
\r
-\r
/**\r
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
Domain.".\r
AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT, Msr);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618\r
-\r
+#define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618\r
\r
/**\r
Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_DRAM_ENERGY_STATUS);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619\r
+#define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_DRAM_ENERGY_STATUS\r
/// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
/// to enable DRAM RAPL mode 0 (Direct VR).\r
///\r
- UINT32 Energy:32;\r
- UINT32 Reserved:32;\r
+ UINT32 Energy : 32;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER;\r
\r
-\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
RAPL Domain.".\r
Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_PERF_STATUS);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B\r
-\r
+#define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B\r
\r
/**\r
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO, Msr);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C\r
-\r
+#define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C\r
\r
/**\r
Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
AsmWriteMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+#define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT\r
/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
/// LLC/Ring.\r
///\r
- UINT32 MAX_RATIO:7;\r
- UINT32 Reserved1:1;\r
+ UINT32 MAX_RATIO : 7;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
/// possible ratio of the LLC/Ring.\r
///\r
- UINT32 MIN_RATIO:7;\r
- UINT32 Reserved2:17;\r
- UINT32 Reserved3:32;\r
+ UINT32 MIN_RATIO : 7;\r
+ UINT32 Reserved2 : 17;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. Reserved (R/O) Reads return 0.\r
\r
Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H,\r
AsmWriteMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D\r
+#define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_IA32_QM_EVTSEL\r
/// occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03:\r
/// Local memory bandwidth monitoring. All other encoding reserved.\r
///\r
- UINT32 EventID:8;\r
- UINT32 Reserved1:24;\r
+ UINT32 EventID : 8;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bits 41:32] RMID (RW).\r
///\r
- UINT32 RMID:10;\r
- UINT32 Reserved2:22;\r
+ UINT32 RMID : 10;\r
+ UINT32 Reserved2 : 22;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER;\r
\r
-\r
/**\r
THREAD. Resource Association Register (R/W).\r
\r
AsmWriteMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F\r
+#define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_IA32_PQR_ASSOC\r
///\r
/// [Bits 9:0] RMID.\r
///\r
- UINT32 RMID:10;\r
- UINT32 Reserved1:22;\r
+ UINT32 RMID : 10;\r
+ UINT32 Reserved1 : 22;\r
///\r
/// [Bits 51:32] COS (R/W).\r
///\r
- UINT32 COS:20;\r
- UINT32 Reserved2:12;\r
+ UINT32 COS : 20;\r
+ UINT32 Reserved2 : 12;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER;\r
\r
-\r
/**\r
Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H,\r
ECX=1):EDX.COS_MAX[15:0] >=0.\r
AsmWriteMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N\r
///\r
/// [Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement.\r
///\r
- UINT32 CBM:20;\r
- UINT32 Reserved2:12;\r
- UINT32 Reserved3:32;\r
+ UINT32 CBM : 20;\r
+ UINT32 Reserved2 : 12;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER;\r
\r
-\r
#endif\r
projects / mirror_edk2.git / blobdiff