MdePkg: Apply uncrustify changes

[mirror_edk2.git] / MdePkg / Include / Register / Intel / Msr / Xeon5600Msr.h

diff --git a/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h b/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h
index 01293ff2936e12dffb926e9b0aeb788981994590..383e3eaf5706c37f5fdfd725d9ea74ed84eb3328 100644 (file)
--- a/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h
+++ b/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h
@@ -56,7 +56,7 @@
   @endcode\r
   @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
 **/\r
-#define MSR_XEON_5600_FEATURE_CONFIG             0x0000013C\r
+#define MSR_XEON_5600_FEATURE_CONFIG  0x0000013C\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG\r
@@ -75,21 +75,20 @@ typedef union {
     /// 01b, AES instruction can be mis-configured if a privileged agent\r
     /// unintentionally writes 11b.\r
     ///\r
-    UINT32  AESConfiguration:2;\r
-    UINT32  Reserved1:30;\r
-    UINT32  Reserved2:32;\r
+    UINT32    AESConfiguration : 2;\r
+    UINT32    Reserved1        : 30;\r
+    UINT32    Reserved2        : 32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
-  UINT32  Uint32;\r
+  UINT32    Uint32;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_XEON_5600_FEATURE_CONFIG_REGISTER;\r
 \r
-\r
 /**\r
   Thread. Offcore Response Event Select Register (R/W).\r
 \r
@@ -106,8 +105,7 @@ typedef union {
   @endcode\r
   @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
 **/\r
-#define MSR_XEON_5600_OFFCORE_RSP_1              0x000001A7\r
-\r
+#define MSR_XEON_5600_OFFCORE_RSP_1  0x000001A7\r
 \r
 /**\r
   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
@@ -127,7 +125,7 @@ typedef union {
   @endcode\r
   @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
 **/\r
-#define MSR_XEON_5600_TURBO_RATIO_LIMIT          0x000001AD\r
+#define MSR_XEON_5600_TURBO_RATIO_LIMIT  0x000001AD\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER\r
@@ -141,41 +139,40 @@ typedef union {
     /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
     /// limit of 1 core active.\r
     ///\r
-    UINT32  Maximum1C:8;\r
+    UINT32    Maximum1C : 8;\r
     ///\r
     /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
     /// limit of 2 core active.\r
     ///\r
-    UINT32  Maximum2C:8;\r
+    UINT32    Maximum2C : 8;\r
     ///\r
     /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
     /// limit of 3 core active.\r
     ///\r
-    UINT32  Maximum3C:8;\r
+    UINT32    Maximum3C : 8;\r
     ///\r
     /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
     /// limit of 4 core active.\r
     ///\r
-    UINT32  Maximum4C:8;\r
+    UINT32    Maximum4C : 8;\r
     ///\r
     /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
     /// limit of 5 core active.\r
     ///\r
-    UINT32  Maximum5C:8;\r
+    UINT32    Maximum5C : 8;\r
     ///\r
     /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
     /// limit of 6 core active.\r
     ///\r
-    UINT32  Maximum6C:8;\r
-    UINT32  Reserved:16;\r
+    UINT32    Maximum6C : 8;\r
+    UINT32    Reserved  : 16;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;\r
 \r
-\r
 /**\r
   Package. See Table 2-2.\r
 \r
@@ -192,6 +189,6 @@ typedef union {
   @endcode\r
   @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r
 **/\r
-#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS      0x000001B0\r
+#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS  0x000001B0\r
 \r
 #endif\r