MdePkg: Apply uncrustify changes

[mirror_edk2.git] / MdePkg / Include / Register / Intel / Msr / XeonE7Msr.h

diff --git a/MdePkg/Include/Register/Intel/Msr/XeonE7Msr.h b/MdePkg/Include/Register/Intel/Msr/XeonE7Msr.h
index 6e8c61e19b25f0bb4f5cd2038f86e820c887250d..3a6b6b7b9d92a1b02850cce1044458d008fa7f1f 100644 (file)
--- a/MdePkg/Include/Register/Intel/Msr/XeonE7Msr.h
+++ b/MdePkg/Include/Register/Intel/Msr/XeonE7Msr.h
@@ -55,7 +55,7 @@
   @endcode\r
   @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
 **/\r
-#define MSR_XEON_E7_FEATURE_CONFIG               0x0000013C\r
+#define MSR_XEON_E7_FEATURE_CONFIG  0x0000013C\r
 \r
 /**\r
   MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG\r
@@ -74,21 +74,20 @@ typedef union {
     /// 01b, AES instruction can be mis-configured if a privileged agent\r
     /// unintentionally writes 11b.\r
     ///\r
-    UINT32  AESConfiguration:2;\r
-    UINT32  Reserved1:30;\r
-    UINT32  Reserved2:32;\r
+    UINT32    AESConfiguration : 2;\r
+    UINT32    Reserved1        : 30;\r
+    UINT32    Reserved2        : 32;\r
   } Bits;\r
   ///\r
   /// All bit fields as a 32-bit value\r
   ///\r
-  UINT32  Uint32;\r
+  UINT32    Uint32;\r
   ///\r
   /// All bit fields as a 64-bit value\r
   ///\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } MSR_XEON_E7_FEATURE_CONFIG_REGISTER;\r
 \r
-\r
 /**\r
   Thread. Offcore Response Event Select Register (R/W).\r
 \r
@@ -105,8 +104,7 @@ typedef union {
   @endcode\r
   @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
 **/\r
-#define MSR_XEON_E7_OFFCORE_RSP_1                0x000001A7\r
-\r
+#define MSR_XEON_E7_OFFCORE_RSP_1  0x000001A7\r
 \r
 /**\r
   Package. Reserved Attempt to read/write will cause #UD.\r
@@ -124,8 +122,7 @@ typedef union {
   @endcode\r
   @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
 **/\r
-#define MSR_XEON_E7_TURBO_RATIO_LIMIT            0x000001AD\r
-\r
+#define MSR_XEON_E7_TURBO_RATIO_LIMIT  0x000001AD\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon local box control MSR.\r
@@ -143,8 +140,7 @@ typedef union {
   @endcode\r
   @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.\r
 **/\r
-#define MSR_XEON_E7_C8_PMON_BOX_CTRL             0x00000F40\r
-\r
+#define MSR_XEON_E7_C8_PMON_BOX_CTRL  0x00000F40\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon local box status MSR.\r
@@ -162,8 +158,7 @@ typedef union {
   @endcode\r
   @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_XEON_E7_C8_PMON_BOX_STATUS           0x00000F41\r
-\r
+#define MSR_XEON_E7_C8_PMON_BOX_STATUS  0x00000F41\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon local box overflow control MSR.\r
@@ -181,8 +176,7 @@ typedef union {
   @endcode\r
   @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.\r
 **/\r
-#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL         0x00000F42\r
-\r
+#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL  0x00000F42\r
 \r
 /**\r
   Package. Uncore C-box 8 perfmon event select MSR.\r
@@ -206,15 +200,14 @@ typedef union {
         MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.\r
   @{\r
 **/\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL0            0x00000F50\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL1            0x00000F52\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL2            0x00000F54\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL3            0x00000F56\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL4            0x00000F58\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL5            0x00000F5A\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL0  0x00000F50\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL1  0x00000F52\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL2  0x00000F54\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL3  0x00000F56\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL4  0x00000F58\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL5  0x00000F5A\r
 /// @}\r
 \r
-\r
 /**\r
   Package. Uncore C-box 8 perfmon counter MSR.\r
 \r
@@ -237,15 +230,14 @@ typedef union {
         MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.\r
   @{\r
 **/\r
-#define MSR_XEON_E7_C8_PMON_CTR0                 0x00000F51\r
-#define MSR_XEON_E7_C8_PMON_CTR1                 0x00000F53\r
-#define MSR_XEON_E7_C8_PMON_CTR2                 0x00000F55\r
-#define MSR_XEON_E7_C8_PMON_CTR3                 0x00000F57\r
-#define MSR_XEON_E7_C8_PMON_CTR4                 0x00000F59\r
-#define MSR_XEON_E7_C8_PMON_CTR5                 0x00000F5B\r
+#define MSR_XEON_E7_C8_PMON_CTR0  0x00000F51\r
+#define MSR_XEON_E7_C8_PMON_CTR1  0x00000F53\r
+#define MSR_XEON_E7_C8_PMON_CTR2  0x00000F55\r
+#define MSR_XEON_E7_C8_PMON_CTR3  0x00000F57\r
+#define MSR_XEON_E7_C8_PMON_CTR4  0x00000F59\r
+#define MSR_XEON_E7_C8_PMON_CTR5  0x00000F5B\r
 /// @}\r
 \r
-\r
 /**\r
   Package. Uncore C-box 9 perfmon local box control MSR.\r
 \r
@@ -262,8 +254,7 @@ typedef union {
   @endcode\r
   @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.\r
 **/\r
-#define MSR_XEON_E7_C9_PMON_BOX_CTRL             0x00000FC0\r
-\r
+#define MSR_XEON_E7_C9_PMON_BOX_CTRL  0x00000FC0\r
 \r
 /**\r
   Package. Uncore C-box 9 perfmon local box status MSR.\r
@@ -281,8 +272,7 @@ typedef union {
   @endcode\r
   @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
 **/\r
-#define MSR_XEON_E7_C9_PMON_BOX_STATUS           0x00000FC1\r
-\r
+#define MSR_XEON_E7_C9_PMON_BOX_STATUS  0x00000FC1\r
 \r
 /**\r
   Package. Uncore C-box 9 perfmon local box overflow control MSR.\r
@@ -300,8 +290,7 @@ typedef union {
   @endcode\r
   @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.\r
 **/\r
-#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL         0x00000FC2\r
-\r
+#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL  0x00000FC2\r
 \r
 /**\r
   Package. Uncore C-box 9 perfmon event select MSR.\r
@@ -325,15 +314,14 @@ typedef union {
         MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.\r
   @{\r
 **/\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL0            0x00000FD0\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL1            0x00000FD2\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL2            0x00000FD4\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL3            0x00000FD6\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL4            0x00000FD8\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL5            0x00000FDA\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL0  0x00000FD0\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL1  0x00000FD2\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL2  0x00000FD4\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL3  0x00000FD6\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL4  0x00000FD8\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL5  0x00000FDA\r
 /// @}\r
 \r
-\r
 /**\r
   Package. Uncore C-box 9 perfmon counter MSR.\r
 \r
@@ -356,12 +344,12 @@ typedef union {
         MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.\r
   @{\r
 **/\r
-#define MSR_XEON_E7_C9_PMON_CTR0                 0x00000FD1\r
-#define MSR_XEON_E7_C9_PMON_CTR1                 0x00000FD3\r
-#define MSR_XEON_E7_C9_PMON_CTR2                 0x00000FD5\r
-#define MSR_XEON_E7_C9_PMON_CTR3                 0x00000FD7\r
-#define MSR_XEON_E7_C9_PMON_CTR4                 0x00000FD9\r
-#define MSR_XEON_E7_C9_PMON_CTR5                 0x00000FDB\r
+#define MSR_XEON_E7_C9_PMON_CTR0  0x00000FD1\r
+#define MSR_XEON_E7_C9_PMON_CTR1  0x00000FD3\r
+#define MSR_XEON_E7_C9_PMON_CTR2  0x00000FD5\r
+#define MSR_XEON_E7_C9_PMON_CTR3  0x00000FD7\r
+#define MSR_XEON_E7_C9_PMON_CTR4  0x00000FD9\r
+#define MSR_XEON_E7_C9_PMON_CTR5  0x00000FDB\r
 /// @}\r
 \r
 #endif\r