@endcode\r
@note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
**/\r
-#define MSR_XEON_PHI_SMI_COUNT 0x00000034\r
+#define MSR_XEON_PHI_SMI_COUNT 0x00000034\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT\r
///\r
/// [Bits 31:0] SMI Count (R/O).\r
///\r
- UINT32 SMICount:32;\r
- UINT32 Reserved:32;\r
+ UINT32 SMICount : 32;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_SMI_COUNT_REGISTER;\r
\r
/**\r
AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_XEON_PHI_PPIN_CTL 0x0000004E\r
+#define MSR_XEON_PHI_PPIN_CTL 0x0000004E\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL\r
/// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r
/// prevent unauthorized modification to MSR_PPIN_CTL.\r
///\r
- UINT32 LockOut:1;\r
+ UINT32 LockOut : 1;\r
///\r
/// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r
/// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]\r
/// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.\r
/// Default is 0.\r
///\r
- UINT32 Enable_PPIN:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 Enable_PPIN : 1;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_PPIN_CTL_REGISTER;\r
\r
-\r
/**\r
Package. Protected Processor Inventory Number (R/O). Protected Processor\r
Inventory Number (R/O) A unique value within a given CPUID\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);\r
@endcode\r
**/\r
-#define MSR_XEON_PHI_PPIN 0x0000004F\r
+#define MSR_XEON_PHI_PPIN 0x0000004F\r
\r
/**\r
Package. Platform Information Contains power management and other model\r
@endcode\r
@note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
-#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE\r
+#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
/// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
/// MHz.\r
///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
+ UINT32 MaximumNonTurboRatio : 8;\r
+ UINT32 Reserved2 : 12;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
/// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
/// Turbo mode is disabled.\r
///\r
- UINT32 RatioLimit:1;\r
+ UINT32 RatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
/// and when set to 0, indicates TDP Limit for Turbo mode is not\r
/// programmable.\r
///\r
- UINT32 TDPLimit:1;\r
- UINT32 Reserved3:2;\r
- UINT32 Reserved4:8;\r
+ UINT32 TDPLimit : 1;\r
+ UINT32 Reserved3 : 2;\r
+ UINT32 Reserved4 : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
/// minimum ratio (maximum efficiency) that the processor can operates, in\r
/// units of 100MHz.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved5:16;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
+ UINT32 Reserved5 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_PLATFORM_INFO_REGISTER;\r
\r
-\r
/**\r
Module. C-State Configuration Control (R/W).\r
\r
@endcode\r
@note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL\r
/// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No\r
/// Retention 011b: C6 Retention 111b: No limit.\r
///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 Limit : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO).\r
///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved5:10;\r
+ UINT32 CFGLock : 1;\r
+ UINT32 Reserved5 : 10;\r
///\r
/// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor\r
/// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
/// auto-demote information.\r
///\r
- UINT32 C1StateAutoDemotionEnable:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 C1StateAutoDemotionEnable : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables\r
/// Undemotion from Demoted C1.\r
///\r
- UINT32 C1StateAutoUndemotionEnable:1;\r
+ UINT32 C1StateAutoUndemotionEnable : 1;\r
///\r
/// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables\r
/// Package C state demotion.\r
///\r
- UINT32 PKGC_StateAutoDemotionEnable:1;\r
- UINT32 Reserved7:2;\r
- UINT32 Reserved4:32;\r
+ UINT32 PKGC_StateAutoDemotionEnable : 1;\r
+ UINT32 Reserved7 : 2;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Module. Power Management IO Redirection in C-state (R/W).\r
\r
@endcode\r
@note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
**/\r
-#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4\r
+#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE\r
///\r
/// [Bits 15:0] LVL_2 Base Address (R/W).\r
///\r
- UINT32 Lvl2Base:16;\r
+ UINT32 Lvl2Base : 16;\r
///\r
/// [Bits 22:16] C-State Range (R/W) The IO-port block size in which\r
/// IO-redirection will be executed (0-127). Should be programmed based on\r
/// the number of LVLx registers existing in the chipset.\r
///\r
- UINT32 CStateRange:7;\r
- UINT32 Reserved3:9;\r
- UINT32 Reserved2:32;\r
+ UINT32 CStateRange : 7;\r
+ UINT32 Reserved3 : 9;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;\r
\r
-\r
/**\r
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
handler to handle unsuccessful read of this MSR.\r
@endcode\r
@note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
**/\r
-#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C\r
+#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG\r
/// 01b, AES instruction can be mis-configured if a privileged agent\r
/// unintentionally writes 11b.\r
///\r
- UINT32 AESConfiguration:2;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 AESConfiguration : 2;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;\r
\r
-\r
/**\r
Thread. MISC_FEATURE_ENABLES.\r
\r
AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140\r
+#define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and\r
/// MWAIT instructions do not cause invalid-opcode exceptions when\r
/// other than C0 or C1, the instruction operates as if EAX indicated the\r
/// C-state C1.\r
///\r
- UINT32 UserModeMonitorAndMwait:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
+ UINT32 UserModeMonitorAndMwait : 1;\r
+ UINT32 Reserved2 : 30;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER;\r
\r
/**\r
@endcode\r
@note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
**/\r
-#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D\r
+#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP\r
/// set, that bank supports Enhanced MCA (Default all 0; does not support\r
/// EMCA).\r
///\r
- UINT32 BankSupport:32;\r
- UINT32 Reserved4:24;\r
+ UINT32 BankSupport : 32;\r
+ UINT32 Reserved4 : 24;\r
///\r
/// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.\r
///\r
- UINT32 TargetedSMI:1;\r
+ UINT32 TargetedSMI : 1;\r
///\r
/// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature\r
/// is supported.\r
///\r
- UINT32 SMM_CPU_SVRSTR:1;\r
+ UINT32 SMM_CPU_SVRSTR : 1;\r
///\r
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
/// SMM code access restriction is supported and a host-space interface\r
/// available to SMM handler.\r
///\r
- UINT32 SMM_Code_Access_Chk:1;\r
+ UINT32 SMM_Code_Access_Chk : 1;\r
///\r
/// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
/// SMM long flow indicator is supported and a host-space interface\r
/// available to SMM handler.\r
///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 Long_Flow_Indication : 1;\r
+ UINT32 Reserved3 : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;\r
\r
-\r
/**\r
Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE\r
///\r
/// [Bit 0] Fast-Strings Enable.\r
///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 FastStrings : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value\r
/// is 1.\r
///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 AutomaticThermalControlCircuit : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 7] Performance Monitoring Available (R).\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:3;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved3 : 3;\r
///\r
/// [Bit 11] Branch Trace Storage Unavailable (RO).\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] Processor Event Based Sampling Unavailable (RO).\r
///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved4:3;\r
+ UINT32 PEBS : 1;\r
+ UINT32 Reserved4 : 3;\r
///\r
/// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 18] ENABLE MONITOR FSM (R/W).\r
///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved6:3;\r
+ UINT32 MONITOR : 1;\r
+ UINT32 Reserved6 : 3;\r
///\r
/// [Bit 22] Limit CPUID Maxval (R/W).\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
+ UINT32 LimitCpuidMaxval : 1;\r
///\r
/// [Bit 23] xTPR Message Disable (R/W).\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
+ UINT32 xTPR_Message_Disable : 1;\r
+ UINT32 Reserved7 : 8;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bit 34] XD Bit Disable (R/W).\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:3;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved9 : 3;\r
///\r
/// [Bit 38] Turbo Mode Disable (R/W).\r
///\r
- UINT32 TurboModeDisable:1;\r
- UINT32 Reserved10:25;\r
+ UINT32 TurboModeDisable : 1;\r
+ UINT32 Reserved10 : 25;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Package.\r
\r
@endcode\r
@note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
**/\r
-#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2\r
+#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bits 23:16] Temperature Target (R).\r
///\r
- UINT32 TemperatureTarget:8;\r
+ UINT32 TemperatureTarget : 8;\r
///\r
/// [Bits 29:24] Target Offset (R/W).\r
///\r
- UINT32 TargetOffset:6;\r
- UINT32 Reserved2:2;\r
- UINT32 Reserved3:32;\r
+ UINT32 TargetOffset : 6;\r
+ UINT32 Reserved2 : 2;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;\r
\r
-\r
/**\r
Miscellaneous Feature Control (R/W).\r
\r
@endcode\r
@note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4\r
+#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL\r
/// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the\r
/// L1 data cache prefetcher.\r
///\r
- UINT32 DCUHardwarePrefetcherDisable:1;\r
+ UINT32 DCUHardwarePrefetcherDisable : 1;\r
///\r
/// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
/// L2 hardware prefetcher.\r
///\r
- UINT32 L2HardwarePrefetcherDisable:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 L2HardwarePrefetcherDisable : 1;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Shared. Offcore Response Event Select Register (R/W).\r
\r
@endcode\r
@note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
**/\r
-#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6\r
-\r
+#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6\r
\r
/**\r
Shared. Offcore Response Event Select Register (R/W).\r
@endcode\r
@note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
**/\r
-#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7\r
-\r
+#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7\r
\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).\r
@endcode\r
@note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved:1;\r
+ UINT32 Reserved : 1;\r
///\r
/// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active\r
/// processor cores which operates under the maximum ratio limit for group\r
/// 0.\r
///\r
- UINT32 MaxCoresGroup0:7;\r
+ UINT32 MaxCoresGroup0 : 7;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo\r
/// ratio limit when the number of active cores are not more than the\r
/// group 0 maximum core count.\r
///\r
- UINT32 MaxRatioLimitGroup0:8;\r
+ UINT32 MaxRatioLimitGroup0 : 8;\r
///\r
/// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1\r
/// Group 1, which includes the specified number of additional cores plus\r
/// the cores in group 0, operates under the group 1 turbo max ratio limit\r
/// = "group 0 Max ratio limit" - "group ratio delta for group 1".\r
///\r
- UINT32 MaxIncrementalCoresGroup1:5;\r
+ UINT32 MaxIncrementalCoresGroup1 : 5;\r
///\r
/// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned\r
/// integer specifying the ratio decrement relative to the Max ratio limit\r
/// to Group 0.\r
///\r
- UINT32 DeltaRatioGroup1:3;\r
+ UINT32 DeltaRatioGroup1 : 3;\r
///\r
/// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2\r
/// Group 2, which includes the specified number of additional cores plus\r
/// all the cores in group 1, operates under the group 2 turbo max ratio\r
/// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".\r
///\r
- UINT32 MaxIncrementalCoresGroup2:5;\r
+ UINT32 MaxIncrementalCoresGroup2 : 5;\r
///\r
/// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned\r
/// integer specifying the ratio decrement relative to the Max ratio limit\r
/// for Group 1.\r
///\r
- UINT32 DeltaRatioGroup2:3;\r
+ UINT32 DeltaRatioGroup2 : 3;\r
///\r
/// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3\r
/// Group 3, which includes the specified number of additional cores plus\r
/// all the cores in group 2, operates under the group 3 turbo max ratio\r
/// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".\r
///\r
- UINT32 MaxIncrementalCoresGroup3:5;\r
+ UINT32 MaxIncrementalCoresGroup3 : 5;\r
///\r
/// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned\r
/// integer specifying the ratio decrement relative to the Max ratio limit\r
/// for Group 2.\r
///\r
- UINT32 DeltaRatioGroup3:3;\r
+ UINT32 DeltaRatioGroup3 : 3;\r
///\r
/// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4\r
/// Group 4, which includes the specified number of additional cores plus\r
/// all the cores in group 3, operates under the group 4 turbo max ratio\r
/// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".\r
///\r
- UINT32 MaxIncrementalCoresGroup4:5;\r
+ UINT32 MaxIncrementalCoresGroup4 : 5;\r
///\r
/// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned\r
/// integer specifying the ratio decrement relative to the Max ratio limit\r
/// for Group 3.\r
///\r
- UINT32 DeltaRatioGroup4:3;\r
+ UINT32 DeltaRatioGroup4 : 3;\r
///\r
/// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5\r
/// Group 5, which includes the specified number of additional cores plus\r
/// all the cores in group 4, operates under the group 5 turbo max ratio\r
/// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".\r
///\r
- UINT32 MaxIncrementalCoresGroup5:5;\r
+ UINT32 MaxIncrementalCoresGroup5 : 5;\r
///\r
/// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned\r
/// integer specifying the ratio decrement relative to the Max ratio limit\r
/// for Group 4.\r
///\r
- UINT32 DeltaRatioGroup5:3;\r
+ UINT32 DeltaRatioGroup5 : 3;\r
///\r
/// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6\r
/// Group 6, which includes the specified number of additional cores plus\r
/// all the cores in group 5, operates under the group 6 turbo max ratio\r
/// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".\r
///\r
- UINT32 MaxIncrementalCoresGroup6:5;\r
+ UINT32 MaxIncrementalCoresGroup6 : 5;\r
///\r
/// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned\r
/// integer specifying the ratio decrement relative to the Max ratio limit\r
/// for Group 5.\r
///\r
- UINT32 DeltaRatioGroup6:3;\r
+ UINT32 DeltaRatioGroup6 : 3;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Thread. Last Branch Record Filtering Select Register (R/W).\r
\r
@endcode\r
@note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
**/\r
-#define MSR_XEON_PHI_LBR_SELECT 0x000001C8\r
-\r
+#define MSR_XEON_PHI_LBR_SELECT 0x000001C8\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT\r
///\r
/// [Bit 0] CPL_EQ_0.\r
///\r
- UINT32 CPL_EQ_0:1;\r
+ UINT32 CPL_EQ_0 : 1;\r
///\r
/// [Bit 1] CPL_NEQ_0.\r
///\r
- UINT32 CPL_NEQ_0:1;\r
+ UINT32 CPL_NEQ_0 : 1;\r
///\r
/// [Bit 2] JCC.\r
///\r
- UINT32 JCC:1;\r
+ UINT32 JCC : 1;\r
///\r
/// [Bit 3] NEAR_REL_CALL.\r
///\r
- UINT32 NEAR_REL_CALL:1;\r
+ UINT32 NEAR_REL_CALL : 1;\r
///\r
/// [Bit 4] NEAR_IND_CALL.\r
///\r
- UINT32 NEAR_IND_CALL:1;\r
+ UINT32 NEAR_IND_CALL : 1;\r
///\r
/// [Bit 5] NEAR_RET.\r
///\r
- UINT32 NEAR_RET:1;\r
+ UINT32 NEAR_RET : 1;\r
///\r
/// [Bit 6] NEAR_IND_JMP.\r
///\r
- UINT32 NEAR_IND_JMP:1;\r
+ UINT32 NEAR_IND_JMP : 1;\r
///\r
/// [Bit 7] NEAR_REL_JMP.\r
///\r
- UINT32 NEAR_REL_JMP:1;\r
+ UINT32 NEAR_REL_JMP : 1;\r
///\r
/// [Bit 8] FAR_BRANCH.\r
///\r
- UINT32 FAR_BRANCH:1;\r
- UINT32 Reserved1:23;\r
- UINT32 Reserved2:32;\r
+ UINT32 FAR_BRANCH : 1;\r
+ UINT32 Reserved1 : 23;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_LBR_SELECT_REGISTER;\r
\r
/**\r
@endcode\r
@note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Thread. Last Exception Record From Linear IP (R).\r
@endcode\r
@note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
-#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD\r
-\r
+#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD\r
\r
/**\r
Thread. Last Exception Record To Linear IP (R).\r
@endcode\r
@note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
-#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE\r
-\r
+#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE\r
\r
/**\r
Thread. See Table 2-2.\r
@endcode\r
@note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1\r
-\r
+#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1\r
\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8\r
-\r
+#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8\r
\r
/**\r
Package. Package C6 Residency Counter. (R/O).\r
@endcode\r
@note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9\r
-\r
+#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9\r
\r
/**\r
Package. Package C7 Residency Counter. (R/O).\r
@endcode\r
@note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA\r
-\r
+#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA\r
\r
/**\r
Module. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.\r
**/\r
-#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC\r
-\r
+#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC\r
\r
/**\r
Module. Module C6 Residency Counter. (R/O).\r
@endcode\r
@note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.\r
**/\r
-#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD\r
-\r
+#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF\r
-\r
+#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF\r
\r
/**\r
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r
@endcode\r
@note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r
**/\r
-#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
-\r
+#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
\r
/**\r
Core. Capability Reporting Register of VM-Function Controls (R/O) See Table\r
@endcode\r
@note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.\r
**/\r
-#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491\r
-\r
+#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491\r
\r
/**\r
Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
@endcode\r
@note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
-#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606\r
+#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT\r
///\r
/// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
+ UINT32 PowerUnits : 4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 12:8] Package. Energy Status Units Energy related information\r
/// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
/// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
/// micro-joules).\r
///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
+ UINT32 EnergyStatusUnits : 5;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
/// Interfaces.".\r
///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
+ UINT32 TimeUnits : 4;\r
+ UINT32 Reserved3 : 12;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2\r
@endcode\r
@note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D\r
-\r
+#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D\r
\r
/**\r
Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
@endcode\r
@note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610\r
-\r
+#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610\r
\r
/**\r
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
@endcode\r
@note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611\r
-\r
+#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611\r
\r
/**\r
Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
@endcode\r
@note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613\r
-\r
+#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613\r
\r
/**\r
Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r
@endcode\r
@note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614\r
-\r
+#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614\r
\r
/**\r
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
@endcode\r
@note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618\r
-\r
+#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618\r
\r
/**\r
Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619\r
-\r
+#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619\r
\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
@endcode\r
@note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
-#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B\r
-\r
+#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B\r
\r
/**\r
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
**/\r
-#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C\r
-\r
+#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C\r
\r
/**\r
Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT\r
/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
/// LLC/Ring.\r
///\r
- UINT32 MAX_RATIO:7;\r
- UINT32 Reserved1:1;\r
+ UINT32 MAX_RATIO : 7;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
/// possible ratio of the LLC/Ring.\r
///\r
- UINT32 MIN_RATIO:7;\r
- UINT32 Reserved2:17;\r
- UINT32 Reserved3:32;\r
+ UINT32 MIN_RATIO : 7;\r
+ UINT32 Reserved2 : 17;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
RAPL Domains.".\r
@endcode\r
@note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638\r
-\r
+#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638\r
\r
/**\r
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Package. Base TDP Ratio (R/O) See Table 2-24.\r
@endcode\r
@note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
**/\r
-#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648\r
-\r
+#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648\r
\r
/**\r
Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.\r
@endcode\r
@note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
**/\r
-#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649\r
-\r
+#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649\r
\r
/**\r
Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.\r
@endcode\r
@note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
**/\r
-#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A\r
-\r
+#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A\r
\r
/**\r
Package. ConfigTDP Control (R/W) See Table 2-24.\r
@endcode\r
@note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
**/\r
-#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B\r
-\r
+#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B\r
\r
/**\r
Package. ConfigTDP Control (R/W) See Table 2-24.\r
@endcode\r
@note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
**/\r
-#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C\r
-\r
+#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C\r
\r
/**\r
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
@endcode\r
@note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
**/\r
-#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690\r
+#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS\r
///\r
/// [Bit 0] PROCHOT Status (R0).\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0).\r
///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 ThermalStatus : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0).\r
///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 8] Electrical Design Point Status (R0).\r
///\r
- UINT32 ElectricalDesignPointStatus:1;\r
- UINT32 Reserved3:23;\r
- UINT32 Reserved4:32;\r
+ UINT32 ElectricalDesignPointStatus : 1;\r
+ UINT32 Reserved3 : 23;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff