///\r
/// Default SMBASE address\r
///\r
-#define SMM_DEFAULT_SMBASE 0x30000\r
+#define SMM_DEFAULT_SMBASE 0x30000\r
\r
///\r
/// Offset of SMM handler from SMBASE\r
///\r
-#define SMM_HANDLER_OFFSET 0x8000\r
+#define SMM_HANDLER_OFFSET 0x8000\r
\r
///\r
/// Offset of SMRAM Save State Map from SMBASE\r
/// 32-bit SMRAM Save State Map\r
///\r
typedef struct {\r
- UINT8 Reserved[0x200]; // 7c00h\r
- // Padded an extra 0x200 bytes so 32-bit and 64-bit\r
- // SMRAM Save State Maps are the same size\r
- UINT8 Reserved1[0xf8]; // 7e00h\r
- UINT32 SMBASE; // 7ef8h\r
- UINT32 SMMRevId; // 7efch\r
- UINT16 IORestart; // 7f00h\r
- UINT16 AutoHALTRestart; // 7f02h\r
- UINT8 Reserved2[0x9C]; // 7f08h\r
- UINT32 IOMemAddr; // 7fa0h\r
- UINT32 IOMisc; // 7fa4h\r
- UINT32 _ES; // 7fa8h\r
- UINT32 _CS; // 7fach\r
- UINT32 _SS; // 7fb0h\r
- UINT32 _DS; // 7fb4h\r
- UINT32 _FS; // 7fb8h\r
- UINT32 _GS; // 7fbch\r
- UINT32 Reserved3; // 7fc0h\r
- UINT32 _TR; // 7fc4h\r
- UINT32 _DR7; // 7fc8h\r
- UINT32 _DR6; // 7fcch\r
- UINT32 _EAX; // 7fd0h\r
- UINT32 _ECX; // 7fd4h\r
- UINT32 _EDX; // 7fd8h\r
- UINT32 _EBX; // 7fdch\r
- UINT32 _ESP; // 7fe0h\r
- UINT32 _EBP; // 7fe4h\r
- UINT32 _ESI; // 7fe8h\r
- UINT32 _EDI; // 7fech\r
- UINT32 _EIP; // 7ff0h\r
- UINT32 _EFLAGS; // 7ff4h\r
- UINT32 _CR3; // 7ff8h\r
- UINT32 _CR0; // 7ffch\r
+ UINT8 Reserved[0x200]; // 7c00h\r
+ // Padded an extra 0x200 bytes so 32-bit and 64-bit\r
+ // SMRAM Save State Maps are the same size\r
+ UINT8 Reserved1[0xf8]; // 7e00h\r
+ UINT32 SMBASE; // 7ef8h\r
+ UINT32 SMMRevId; // 7efch\r
+ UINT16 IORestart; // 7f00h\r
+ UINT16 AutoHALTRestart; // 7f02h\r
+ UINT8 Reserved2[0x9C]; // 7f08h\r
+ UINT32 IOMemAddr; // 7fa0h\r
+ UINT32 IOMisc; // 7fa4h\r
+ UINT32 _ES; // 7fa8h\r
+ UINT32 _CS; // 7fach\r
+ UINT32 _SS; // 7fb0h\r
+ UINT32 _DS; // 7fb4h\r
+ UINT32 _FS; // 7fb8h\r
+ UINT32 _GS; // 7fbch\r
+ UINT32 Reserved3; // 7fc0h\r
+ UINT32 _TR; // 7fc4h\r
+ UINT32 _DR7; // 7fc8h\r
+ UINT32 _DR6; // 7fcch\r
+ UINT32 _EAX; // 7fd0h\r
+ UINT32 _ECX; // 7fd4h\r
+ UINT32 _EDX; // 7fd8h\r
+ UINT32 _EBX; // 7fdch\r
+ UINT32 _ESP; // 7fe0h\r
+ UINT32 _EBP; // 7fe4h\r
+ UINT32 _ESI; // 7fe8h\r
+ UINT32 _EDI; // 7fech\r
+ UINT32 _EIP; // 7ff0h\r
+ UINT32 _EFLAGS; // 7ff4h\r
+ UINT32 _CR3; // 7ff8h\r
+ UINT32 _CR0; // 7ffch\r
} SMRAM_SAVE_STATE_MAP32;\r
\r
///\r
/// 64-bit SMRAM Save State Map\r
///\r
typedef struct {\r
- UINT8 Reserved1[0x1d0]; // 7c00h\r
- UINT32 GdtBaseHiDword; // 7dd0h\r
- UINT32 LdtBaseHiDword; // 7dd4h\r
- UINT32 IdtBaseHiDword; // 7dd8h\r
- UINT8 Reserved2[0xc]; // 7ddch\r
- UINT64 IO_EIP; // 7de8h\r
- UINT8 Reserved3[0x50]; // 7df0h\r
- UINT32 _CR4; // 7e40h\r
- UINT8 Reserved4[0x48]; // 7e44h\r
- UINT32 GdtBaseLoDword; // 7e8ch\r
- UINT32 Reserved5; // 7e90h\r
- UINT32 IdtBaseLoDword; // 7e94h\r
- UINT32 Reserved6; // 7e98h\r
- UINT32 LdtBaseLoDword; // 7e9ch\r
- UINT8 Reserved7[0x38]; // 7ea0h\r
- UINT64 EptVmxControl; // 7ed8h\r
- UINT32 EnEptVmxControl; // 7ee0h\r
- UINT8 Reserved8[0x14]; // 7ee4h\r
- UINT32 SMBASE; // 7ef8h\r
- UINT32 SMMRevId; // 7efch\r
- UINT16 IORestart; // 7f00h\r
- UINT16 AutoHALTRestart; // 7f02h\r
- UINT8 Reserved9[0x18]; // 7f04h\r
- UINT64 _R15; // 7f1ch\r
- UINT64 _R14;\r
- UINT64 _R13;\r
- UINT64 _R12;\r
- UINT64 _R11;\r
- UINT64 _R10;\r
- UINT64 _R9;\r
- UINT64 _R8;\r
- UINT64 _RAX; // 7f5ch\r
- UINT64 _RCX;\r
- UINT64 _RDX;\r
- UINT64 _RBX;\r
- UINT64 _RSP;\r
- UINT64 _RBP;\r
- UINT64 _RSI;\r
- UINT64 _RDI;\r
- UINT64 IOMemAddr; // 7f9ch\r
- UINT32 IOMisc; // 7fa4h\r
- UINT32 _ES; // 7fa8h\r
- UINT32 _CS;\r
- UINT32 _SS;\r
- UINT32 _DS;\r
- UINT32 _FS;\r
- UINT32 _GS;\r
- UINT32 _LDTR; // 7fc0h\r
- UINT32 _TR;\r
- UINT64 _DR7; // 7fc8h\r
- UINT64 _DR6;\r
- UINT64 _RIP; // 7fd8h\r
- UINT64 IA32_EFER; // 7fe0h\r
- UINT64 _RFLAGS; // 7fe8h\r
- UINT64 _CR3; // 7ff0h\r
- UINT64 _CR0; // 7ff8h\r
+ UINT8 Reserved1[0x1d0]; // 7c00h\r
+ UINT32 GdtBaseHiDword; // 7dd0h\r
+ UINT32 LdtBaseHiDword; // 7dd4h\r
+ UINT32 IdtBaseHiDword; // 7dd8h\r
+ UINT8 Reserved2[0xc]; // 7ddch\r
+ UINT64 IO_EIP; // 7de8h\r
+ UINT8 Reserved3[0x50]; // 7df0h\r
+ UINT32 _CR4; // 7e40h\r
+ UINT8 Reserved4[0x48]; // 7e44h\r
+ UINT32 GdtBaseLoDword; // 7e8ch\r
+ UINT32 Reserved5; // 7e90h\r
+ UINT32 IdtBaseLoDword; // 7e94h\r
+ UINT32 Reserved6; // 7e98h\r
+ UINT32 LdtBaseLoDword; // 7e9ch\r
+ UINT8 Reserved7[0x38]; // 7ea0h\r
+ UINT64 EptVmxControl; // 7ed8h\r
+ UINT32 EnEptVmxControl; // 7ee0h\r
+ UINT8 Reserved8[0x14]; // 7ee4h\r
+ UINT32 SMBASE; // 7ef8h\r
+ UINT32 SMMRevId; // 7efch\r
+ UINT16 IORestart; // 7f00h\r
+ UINT16 AutoHALTRestart; // 7f02h\r
+ UINT8 Reserved9[0x18]; // 7f04h\r
+ UINT64 _R15; // 7f1ch\r
+ UINT64 _R14;\r
+ UINT64 _R13;\r
+ UINT64 _R12;\r
+ UINT64 _R11;\r
+ UINT64 _R10;\r
+ UINT64 _R9;\r
+ UINT64 _R8;\r
+ UINT64 _RAX; // 7f5ch\r
+ UINT64 _RCX;\r
+ UINT64 _RDX;\r
+ UINT64 _RBX;\r
+ UINT64 _RSP;\r
+ UINT64 _RBP;\r
+ UINT64 _RSI;\r
+ UINT64 _RDI;\r
+ UINT64 IOMemAddr; // 7f9ch\r
+ UINT32 IOMisc; // 7fa4h\r
+ UINT32 _ES; // 7fa8h\r
+ UINT32 _CS;\r
+ UINT32 _SS;\r
+ UINT32 _DS;\r
+ UINT32 _FS;\r
+ UINT32 _GS;\r
+ UINT32 _LDTR; // 7fc0h\r
+ UINT32 _TR;\r
+ UINT64 _DR7; // 7fc8h\r
+ UINT64 _DR6;\r
+ UINT64 _RIP; // 7fd8h\r
+ UINT64 IA32_EFER; // 7fe0h\r
+ UINT64 _RFLAGS; // 7fe8h\r
+ UINT64 _CR3; // 7ff0h\r
+ UINT64 _CR0; // 7ff8h\r
} SMRAM_SAVE_STATE_MAP64;\r
\r
///\r
/// Union of 32-bit and 64-bit SMRAM Save State Maps\r
///\r
typedef union {\r
- SMRAM_SAVE_STATE_MAP32 x86;\r
- SMRAM_SAVE_STATE_MAP64 x64;\r
+ SMRAM_SAVE_STATE_MAP32 x86;\r
+ SMRAM_SAVE_STATE_MAP64 x64;\r
} SMRAM_SAVE_STATE_MAP;\r
\r
///\r
///\r
/// SMRAM Save State Map IOMisc I/O Length Values\r
///\r
-#define SMM_IO_LENGTH_BYTE 0x01\r
-#define SMM_IO_LENGTH_WORD 0x02\r
-#define SMM_IO_LENGTH_DWORD 0x04\r
+#define SMM_IO_LENGTH_BYTE 0x01\r
+#define SMM_IO_LENGTH_WORD 0x02\r
+#define SMM_IO_LENGTH_DWORD 0x04\r
\r
///\r
/// SMRAM Save State Map IOMisc I/O Instruction Type Values\r
///\r
-#define SMM_IO_TYPE_IN_IMMEDIATE 0x9\r
-#define SMM_IO_TYPE_IN_DX 0x1\r
-#define SMM_IO_TYPE_OUT_IMMEDIATE 0x8\r
-#define SMM_IO_TYPE_OUT_DX 0x0\r
-#define SMM_IO_TYPE_INS 0x3\r
-#define SMM_IO_TYPE_OUTS 0x2\r
-#define SMM_IO_TYPE_REP_INS 0x7\r
-#define SMM_IO_TYPE_REP_OUTS 0x6\r
+#define SMM_IO_TYPE_IN_IMMEDIATE 0x9\r
+#define SMM_IO_TYPE_IN_DX 0x1\r
+#define SMM_IO_TYPE_OUT_IMMEDIATE 0x8\r
+#define SMM_IO_TYPE_OUT_DX 0x0\r
+#define SMM_IO_TYPE_INS 0x3\r
+#define SMM_IO_TYPE_OUTS 0x2\r
+#define SMM_IO_TYPE_REP_INS 0x7\r
+#define SMM_IO_TYPE_REP_OUTS 0x6\r
\r
///\r
/// SMRAM Save State Map IOMisc structure\r
///\r
typedef union {\r
struct {\r
- UINT32 SmiFlag:1;\r
- UINT32 Length:3;\r
- UINT32 Type:4;\r
- UINT32 Reserved1:8;\r
- UINT32 Port:16;\r
+ UINT32 SmiFlag : 1;\r
+ UINT32 Length : 3;\r
+ UINT32 Type : 4;\r
+ UINT32 Reserved1 : 8;\r
+ UINT32 Port : 16;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} SMRAM_SAVE_STATE_IOMISC;\r
\r
#pragma pack ()\r
projects / mirror_edk2.git / blobdiff