/** @file\r
Cache Maintenance Functions.\r
\r
- Copyright (c) 2006, Intel Corporation<BR>\r
- All rights reserved. This program and the accompanying materials\r
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
+ http://opensource.org/licenses/bsd-license.php.\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
-typedef struct {\r
- UINT64 Status;\r
- UINT64 r9;\r
- UINT64 r10;\r
- UINT64 r11;\r
-} PAL_PROC_RETURN;\r
-\r
-PAL_PROC_RETURN\r
-CallPalProcStatic (\r
- IN UINT64 Arg1,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4\r
- );\r
+#include <Base.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PalLib.h>\r
\r
/**\r
Invalidates the entire instruction cache in cache coherency domain of the\r
calling CPU.\r
\r
- Invalidates the entire instruction cache in cache coherency domain of the\r
- calling CPU.\r
-\r
**/\r
VOID\r
EFIAPI\r
VOID\r
)\r
{\r
- CallPalProcStatic (1, 1, 1, 0);\r
+ PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r
}\r
\r
/**\r
aligned on a cache line boundary, then the entire instruction cache line\r
containing Address + Length -1 is invalidated. This function may choose to\r
invalidate the entire instruction cache if that is more efficient than\r
- invalidating the specified range. If Length is 0, the no instruction cache\r
+ invalidating the specified range. If Length is 0, then no instruction cache\r
lines are invalidated. Address is returned.\r
\r
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
\r
@param Length The number of bytes to invalidate from the instruction cache.\r
\r
- @return Address\r
+ @return Address.\r
\r
**/\r
-VOID*\r
+VOID *\r
EFIAPI\r
InvalidateInstructionCacheRange (\r
IN VOID *Address,\r
IN UINTN Length\r
)\r
{\r
- ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
-\r
- if (Length > 0) {\r
- InvalidateInstructionCache ();\r
- }\r
- return Address;\r
+ return AsmFlushCacheRange (Address, Length);\r
}\r
\r
/**\r
- Writes Back and Invalidates the entire data cache in cache coherency domain\r
+ Writes back and invalidates the entire data cache in cache coherency domain\r
of the calling CPU.\r
\r
- Writes Back and Invalidates the entire data cache in cache coherency domain\r
+ Writes back and invalidates the entire data cache in cache coherency domain\r
of the calling CPU. This function guarantees that all dirty cache lines are\r
written back to system memory, and also invalidates all the data cache lines\r
in the cache coherency domain of the calling CPU.\r
VOID\r
)\r
{\r
- CallPalProcStatic (1, 2, 1, 0);\r
+ PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r
}\r
\r
/**\r
- Writes Back and Invalidates a range of data cache lines in the cache\r
+ Writes back and invalidates a range of data cache lines in the cache\r
coherency domain of the calling CPU.\r
\r
- Writes Back and Invalidate the data cache lines specified by Address and\r
+ Writes back and invalidates the data cache lines specified by Address and\r
Length. If Address is not aligned on a cache line boundary, then entire data\r
cache line containing Address is written back and invalidated. If Address +\r
Length is not aligned on a cache line boundary, then the entire data cache\r
line containing Address + Length -1 is written back and invalidated. This\r
function may choose to write back and invalidate the entire data cache if\r
that is more efficient than writing back and invalidating the specified\r
- range. If Length is 0, the no data cache lines are written back and\r
+ range. If Length is 0, then no data cache lines are written back and\r
invalidated. Address is returned.\r
\r
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
@param Length The number of bytes to write back and invalidate from the\r
data cache.\r
\r
- @return Address\r
+ @return Address of cache invalidation.\r
\r
**/\r
VOID *\r
IN UINTN Length\r
)\r
{\r
- ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
-\r
- if (Length > 0) {\r
- WriteBackInvalidateDataCache ();\r
- }\r
- return Address;\r
+ return AsmFlushCacheRange (Address, Length);\r
}\r
\r
/**\r
VOID\r
)\r
{\r
- CallPalProcStatic (1, 2, 0, 0);\r
+ PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_NO_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r
}\r
\r
/**\r
cache line boundary, then the entire data cache line containing Address +\r
Length -1 is written back. This function may choose to write back the entire\r
data cache if that is more efficient than writing back the specified range.\r
- If Length is 0, the no data cache lines are written back. This function may\r
+ If Length is 0, then no data cache lines are written back. This function may\r
also invalidate all the data cache lines in the specified range of the cache\r
coherency domain of the calling CPU. Address is returned.\r
\r
mode, then Address is a virtual address.\r
@param Length The number of bytes to write back from the data cache.\r
\r
- @return Address\r
+ @return Address of cache written in main memory.\r
\r
**/\r
VOID *\r
IN UINTN Length\r
)\r
{\r
- ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
-\r
- if (Length > 0) {\r
- WriteBackDataCache ();\r
- }\r
- return Address;\r
+ return AsmFlushCacheRange (Address, Length);\r
}\r
\r
/**\r
VOID\r
)\r
{\r
+ //\r
+ // Invalidation of the entire data cache without writing back is not supported\r
+ // on IPF architecture, so a write back and invalidate operation is performed.\r
+ //\r
WriteBackInvalidateDataCache ();\r
}\r
\r
containing Address is invalidated. If Address + Length is not aligned on a\r
cache line boundary, then the entire data cache line containing Address +\r
Length -1 is invalidated. This function must never invalidate any cache lines\r
- outside the specified range. If Length is 0, the no data cache lines are\r
+ outside the specified range. If Length is 0, then no data cache lines are\r
invalidated. Address is returned. This function must be used with care\r
because dirty cache lines are not written back to system memory. It is\r
typically used for cache diagnostics. If the CPU does not support\r
then Address is a virtual address.\r
@param Length The number of bytes to invalidate from the data cache.\r
\r
- @return Address\r
+ @return Address.\r
\r
**/\r
VOID *\r
IN UINTN Length\r
)\r
{\r
- return WriteBackInvalidateDataCacheRange (Address, Length);\r
+ //\r
+ // Invalidation of a data cache range without writing back is not supported on\r
+ // IPF architecture, so write back and invalidate operation is performed.\r
+ //\r
+ return AsmFlushCacheRange (Address, Length);\r
}\r
projects / mirror_edk2.git / blobdiff