## @file\r
# Base Library implementation.\r
#\r
-# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>\r
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
+# Copyright (c) 2020 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
#\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
LIBRARY_CLASS = BaseLib\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64\r
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64\r
#\r
\r
[Sources]\r
SwapBytes16.c\r
LongJump.c\r
SetJump.c\r
+ QuickSort.c\r
RShiftU64.c\r
RRotU64.c\r
RRotU32.c\r
\r
\r
Ia32/GccInline.c | GCC\r
+ Ia32/GccInlinePriv.c | GCC\r
Ia32/Thunk16.nasm\r
Ia32/EnableDisableInterrupts.nasm| GCC\r
Ia32/EnablePaging64.nasm\r
Ia32/EnableCache.nasm| GCC\r
Ia32/DisableCache.nasm| GCC\r
Ia32/RdRand.nasm\r
+ Ia32/XGetBv.nasm\r
+ Ia32/XSetBv.nasm\r
+ Ia32/VmgExit.nasm\r
\r
Ia32/DivS64x64Remainder.c\r
Ia32/InternalSwitchStack.c | MSFT\r
X86RdRand.c\r
X86PatchInstruction.c\r
X86SpeculationBarrier.c\r
+ IntelTdxNull.c\r
\r
[Sources.X64]\r
X64/Thunk16.nasm\r
X64/ReadCr0.nasm| MSFT\r
X64/ReadEflags.nasm| MSFT\r
\r
+ X64/TdCall.nasm\r
+ X64/TdVmcall.nasm\r
+ X64/TdProbe.c\r
\r
X64/Non-existing.c\r
Math64.c\r
X86PatchInstruction.c\r
X86SpeculationBarrier.c\r
X64/GccInline.c | GCC\r
+ X64/GccInlinePriv.c | GCC\r
X64/EnableDisableInterrupts.nasm\r
X64/DisablePaging64.nasm\r
+ X64/Pvalidate.nasm\r
X64/RdRand.nasm\r
+ X64/RmpAdjust.nasm\r
+ X64/XGetBv.nasm\r
+ X64/XSetBv.nasm\r
+ X64/VmgExit.nasm\r
ChkStkGcc.c | GCC\r
\r
[Sources.EBC]\r
[Sources.ARM]\r
Arm/InternalSwitchStack.c\r
Arm/Unaligned.c\r
- Math64.c | RVCT\r
Math64.c | MSFT\r
\r
- Arm/SwitchStack.asm | RVCT\r
- Arm/SetJumpLongJump.asm | RVCT\r
- Arm/DisableInterrupts.asm | RVCT\r
- Arm/EnableInterrupts.asm | RVCT\r
- Arm/GetInterruptsState.asm | RVCT\r
- Arm/CpuPause.asm | RVCT\r
- Arm/CpuBreakpoint.asm | RVCT\r
- Arm/MemoryFence.asm | RVCT\r
- Arm/SpeculationBarrier.S | RVCT\r
-\r
Arm/SwitchStack.asm | MSFT\r
Arm/SetJumpLongJump.asm | MSFT\r
Arm/DisableInterrupts.asm | MSFT\r
AArch64/CpuBreakpoint.asm | MSFT\r
AArch64/SpeculationBarrier.asm | MSFT\r
\r
+[Sources.RISCV64]\r
+ Math64.c\r
+ Unaligned.c\r
+ RiscV64/InternalSwitchStack.c\r
+ RiscV64/CpuBreakpoint.c\r
+ RiscV64/GetInterruptState.c\r
+ RiscV64/DisableInterrupts.c\r
+ RiscV64/EnableInterrupts.c\r
+ RiscV64/CpuPause.c\r
+ RiscV64/MemoryFence.S | GCC\r
+ RiscV64/RiscVSetJumpLongJump.S | GCC\r
+ RiscV64/RiscVCpuBreakpoint.S | GCC\r
+ RiscV64/RiscVCpuPause.S | GCC\r
+ RiscV64/RiscVInterrupt.S | GCC\r
+ RiscV64/FlushCache.S | GCC\r
+ RiscV64/CpuScratch.S | GCC\r
+ RiscV64/ReadTimer.S | GCC\r
+ RiscV64/RiscVMmu.S | GCC\r
+\r
+[Sources.LOONGARCH64]\r
+ Math64.c\r
+ Unaligned.c\r
+ LoongArch64/InternalSwitchStack.c\r
+ LoongArch64/GetInterruptState.S | GCC\r
+ LoongArch64/EnableInterrupts.S | GCC\r
+ LoongArch64/DisableInterrupts.S | GCC\r
+ LoongArch64/Barrier.S | GCC\r
+ LoongArch64/MemoryFence.S | GCC\r
+ LoongArch64/CpuBreakpoint.S | GCC\r
+ LoongArch64/CpuPause.S | GCC\r
+ LoongArch64/SetJumpLongJump.S | GCC\r
+ LoongArch64/SwitchStack.S | GCC\r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
\r
DebugLib\r
BaseMemoryLib\r
\r
+[LibraryClasses.X64, LibraryClasses.IA32]\r
+ RegisterFilterLib\r
+\r
[Pcd]\r
gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength ## SOMETIMES_CONSUMES\r
gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength ## SOMETIMES_CONSUMES\r
gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength ## SOMETIMES_CONSUMES\r
gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask ## SOMETIMES_CONSUMES\r
+ gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType ## SOMETIMES_CONSUMES\r
\r
[FeaturePcd]\r
gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList ## CONSUMES\r