## @file\r
# Base Library implementation.\r
#\r
-# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>\r
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
+# Copyright (c) 2020 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
#\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
LIBRARY_CLASS = BaseLib\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64\r
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64\r
#\r
\r
[Sources]\r
SwapBytes16.c\r
LongJump.c\r
SetJump.c\r
+ QuickSort.c\r
RShiftU64.c\r
RRotU64.c\r
RRotU32.c\r
Ia32/WriteCr0.c | MSFT\r
Ia32/WriteMsr64.c | MSFT\r
Ia32/SwapBytes64.c | MSFT\r
- Ia32/SetJump.c | MSFT\r
Ia32/RRotU64.c | MSFT\r
Ia32/RShiftU64.c | MSFT\r
Ia32/ReadPmc.c | MSFT\r
Ia32/MultU64x32.c | MSFT\r
Ia32/LShiftU64.c | MSFT\r
Ia32/LRotU64.c | MSFT\r
- Ia32/LongJump.c | MSFT\r
Ia32/Invd.c | MSFT\r
Ia32/FxRestore.c | MSFT\r
Ia32/FxSave.c | MSFT\r
Ia32/EnablePaging32.c | MSFT\r
Ia32/EnableInterrupts.c | MSFT\r
Ia32/EnableDisableInterrupts.c | MSFT\r
- Ia32/DivU64x64Remainder.nasm| MSFT\r
Ia32/DivU64x32Remainder.c | MSFT\r
Ia32/DivU64x32.c | MSFT\r
Ia32/DisablePaging32.c | MSFT\r
Ia32/CpuId.c | MSFT\r
Ia32/CpuBreakpoint.c | MSFT\r
Ia32/ARShiftU64.c | MSFT\r
- Ia32/Thunk16.nasm | MSFT\r
- Ia32/EnablePaging64.nasm| MSFT\r
Ia32/EnableCache.c | MSFT\r
Ia32/DisableCache.c | MSFT\r
- Ia32/RdRand.nasm| MSFT\r
\r
- Ia32/Wbinvd.nasm| INTEL\r
- Ia32/WriteMm7.nasm| INTEL\r
- Ia32/WriteMm6.nasm| INTEL\r
- Ia32/WriteMm5.nasm| INTEL\r
- Ia32/WriteMm4.nasm| INTEL\r
- Ia32/WriteMm3.nasm| INTEL\r
- Ia32/WriteMm2.nasm| INTEL\r
- Ia32/WriteMm1.nasm| INTEL\r
- Ia32/WriteMm0.nasm| INTEL\r
- Ia32/WriteLdtr.nasm| INTEL\r
- Ia32/WriteIdtr.nasm| INTEL\r
- Ia32/WriteGdtr.nasm| INTEL\r
- Ia32/WriteDr7.nasm| INTEL\r
- Ia32/WriteDr6.nasm| INTEL\r
- Ia32/WriteDr5.nasm| INTEL\r
- Ia32/WriteDr4.nasm| INTEL\r
- Ia32/WriteDr3.nasm| INTEL\r
- Ia32/WriteDr2.nasm| INTEL\r
- Ia32/WriteDr1.nasm| INTEL\r
- Ia32/WriteDr0.nasm| INTEL\r
- Ia32/WriteCr4.nasm| INTEL\r
- Ia32/WriteCr3.nasm| INTEL\r
- Ia32/WriteCr2.nasm| INTEL\r
- Ia32/WriteCr0.nasm| INTEL\r
- Ia32/WriteMsr64.nasm| INTEL\r
- Ia32/SwapBytes64.nasm| INTEL\r
- Ia32/SetJump.nasm| INTEL\r
- Ia32/RRotU64.nasm| INTEL\r
- Ia32/RShiftU64.nasm| INTEL\r
- Ia32/ReadPmc.nasm| INTEL\r
- Ia32/ReadTsc.nasm| INTEL\r
- Ia32/ReadLdtr.nasm| INTEL\r
- Ia32/ReadIdtr.nasm| INTEL\r
- Ia32/ReadGdtr.nasm| INTEL\r
- Ia32/ReadTr.nasm| INTEL\r
- Ia32/ReadSs.nasm| INTEL\r
- Ia32/ReadGs.nasm| INTEL\r
- Ia32/ReadFs.nasm| INTEL\r
- Ia32/ReadEs.nasm| INTEL\r
- Ia32/ReadDs.nasm| INTEL\r
- Ia32/ReadCs.nasm| INTEL\r
- Ia32/ReadMsr64.nasm| INTEL\r
- Ia32/ReadMm7.nasm| INTEL\r
- Ia32/ReadMm6.nasm| INTEL\r
- Ia32/ReadMm5.nasm| INTEL\r
- Ia32/ReadMm4.nasm| INTEL\r
- Ia32/ReadMm3.nasm| INTEL\r
- Ia32/ReadMm2.nasm| INTEL\r
- Ia32/ReadMm1.nasm| INTEL\r
- Ia32/ReadMm0.nasm| INTEL\r
- Ia32/ReadEflags.nasm| INTEL\r
- Ia32/ReadDr7.nasm| INTEL\r
- Ia32/ReadDr6.nasm| INTEL\r
- Ia32/ReadDr5.nasm| INTEL\r
- Ia32/ReadDr4.nasm| INTEL\r
- Ia32/ReadDr3.nasm| INTEL\r
- Ia32/ReadDr2.nasm| INTEL\r
- Ia32/ReadDr1.nasm| INTEL\r
- Ia32/ReadDr0.nasm| INTEL\r
- Ia32/ReadCr4.nasm| INTEL\r
- Ia32/ReadCr3.nasm| INTEL\r
- Ia32/ReadCr2.nasm| INTEL\r
- Ia32/ReadCr0.nasm| INTEL\r
- Ia32/Mwait.nasm| INTEL\r
- Ia32/Monitor.nasm| INTEL\r
- Ia32/ModU64x32.nasm| INTEL\r
- Ia32/MultU64x64.nasm| INTEL\r
- Ia32/MultU64x32.nasm| INTEL\r
- Ia32/LShiftU64.nasm| INTEL\r
- Ia32/LRotU64.nasm| INTEL\r
- Ia32/LongJump.nasm| INTEL\r
- Ia32/Invd.nasm| INTEL\r
- Ia32/FxRestore.nasm| INTEL\r
- Ia32/FxSave.nasm| INTEL\r
- Ia32/FlushCacheLine.nasm| INTEL\r
- Ia32/EnablePaging32.nasm| INTEL\r
- Ia32/EnableInterrupts.nasm| INTEL\r
- Ia32/EnableDisableInterrupts.nasm| INTEL\r
- Ia32/DivU64x64Remainder.nasm| INTEL\r
- Ia32/DivU64x32Remainder.nasm| INTEL\r
- Ia32/DivU64x32.nasm| INTEL\r
- Ia32/DisablePaging32.nasm| INTEL\r
- Ia32/DisableInterrupts.nasm| INTEL\r
- Ia32/CpuPause.nasm| INTEL\r
- Ia32/CpuIdEx.nasm| INTEL\r
- Ia32/CpuId.nasm| INTEL\r
- Ia32/CpuBreakpoint.nasm| INTEL\r
- Ia32/ARShiftU64.nasm| INTEL\r
- Ia32/Thunk16.nasm | INTEL\r
- Ia32/EnablePaging64.nasm| INTEL\r
- Ia32/EnableCache.nasm| INTEL\r
- Ia32/DisableCache.nasm| INTEL\r
- Ia32/RdRand.nasm| INTEL\r
\r
Ia32/GccInline.c | GCC\r
- Ia32/Thunk16.nasm | GCC\r
+ Ia32/GccInlinePriv.c | GCC\r
+ Ia32/Thunk16.nasm\r
Ia32/EnableDisableInterrupts.nasm| GCC\r
- Ia32/EnablePaging64.nasm| GCC\r
+ Ia32/EnablePaging64.nasm\r
Ia32/DisablePaging32.nasm| GCC\r
Ia32/EnablePaging32.nasm| GCC\r
Ia32/Mwait.nasm| GCC\r
Ia32/Monitor.nasm| GCC\r
Ia32/CpuIdEx.nasm| GCC\r
Ia32/CpuId.nasm| GCC\r
- Ia32/LongJump.nasm| GCC\r
- Ia32/SetJump.nasm| GCC\r
+ Ia32/LongJump.nasm\r
+ Ia32/SetJump.nasm\r
Ia32/SwapBytes64.nasm| GCC\r
- Ia32/DivU64x64Remainder.nasm| GCC\r
+ Ia32/DivU64x64Remainder.nasm\r
Ia32/DivU64x32Remainder.nasm| GCC\r
Ia32/ModU64x32.nasm| GCC\r
Ia32/DivU64x32.nasm| GCC\r
Ia32/LShiftU64.nasm| GCC\r
Ia32/EnableCache.nasm| GCC\r
Ia32/DisableCache.nasm| GCC\r
- Ia32/RdRand.nasm| GCC\r
+ Ia32/RdRand.nasm\r
+ Ia32/XGetBv.nasm\r
+ Ia32/XSetBv.nasm\r
+ Ia32/VmgExit.nasm\r
\r
Ia32/DivS64x64Remainder.c\r
Ia32/InternalSwitchStack.c | MSFT\r
- Ia32/InternalSwitchStack.c | INTEL\r
Ia32/InternalSwitchStack.nasm | GCC\r
Ia32/Non-existing.c\r
Unaligned.c\r
X86ReadGdtr.c\r
X86Msr.c\r
X86MemoryFence.c | MSFT\r
- X86MemoryFence.c | INTEL\r
X86GetInterruptState.c\r
X86FxSave.c\r
X86FxRestore.c\r
X86RdRand.c\r
X86PatchInstruction.c\r
X86SpeculationBarrier.c\r
+ IntelTdxNull.c\r
\r
[Sources.X64]\r
X64/Thunk16.nasm\r
X64/CpuBreakpoint.c | MSFT\r
X64/WriteMsr64.c | MSFT\r
X64/ReadMsr64.c | MSFT\r
- X64/RdRand.nasm| MSFT\r
X64/CpuPause.nasm| MSFT\r
- X64/EnableDisableInterrupts.nasm| MSFT\r
X64/DisableInterrupts.nasm| MSFT\r
X64/EnableInterrupts.nasm| MSFT\r
X64/FlushCacheLine.nasm| MSFT\r
X64/Invd.nasm| MSFT\r
X64/Wbinvd.nasm| MSFT\r
- X64/DisablePaging64.nasm| MSFT\r
X64/Mwait.nasm| MSFT\r
X64/Monitor.nasm| MSFT\r
X64/ReadPmc.nasm| MSFT\r
X64/ReadCr0.nasm| MSFT\r
X64/ReadEflags.nasm| MSFT\r
\r
- X64/CpuBreakpoint.nasm| INTEL\r
- X64/WriteMsr64.nasm| INTEL\r
- X64/ReadMsr64.nasm| INTEL\r
- X64/RdRand.nasm| INTEL\r
- X64/CpuPause.nasm| INTEL\r
- X64/EnableDisableInterrupts.nasm| INTEL\r
- X64/DisableInterrupts.nasm| INTEL\r
- X64/EnableInterrupts.nasm| INTEL\r
- X64/FlushCacheLine.nasm| INTEL\r
- X64/Invd.nasm| INTEL\r
- X64/Wbinvd.nasm| INTEL\r
- X64/DisablePaging64.nasm| INTEL\r
- X64/Mwait.nasm| INTEL\r
- X64/Monitor.nasm| INTEL\r
- X64/ReadPmc.nasm| INTEL\r
- X64/ReadTsc.nasm| INTEL\r
- X64/WriteMm7.nasm| INTEL\r
- X64/WriteMm6.nasm| INTEL\r
- X64/WriteMm5.nasm| INTEL\r
- X64/WriteMm4.nasm| INTEL\r
- X64/WriteMm3.nasm| INTEL\r
- X64/WriteMm2.nasm| INTEL\r
- X64/WriteMm1.nasm| INTEL\r
- X64/WriteMm0.nasm| INTEL\r
- X64/ReadMm7.nasm| INTEL\r
- X64/ReadMm6.nasm| INTEL\r
- X64/ReadMm5.nasm| INTEL\r
- X64/ReadMm4.nasm| INTEL\r
- X64/ReadMm3.nasm| INTEL\r
- X64/ReadMm2.nasm| INTEL\r
- X64/ReadMm1.nasm| INTEL\r
- X64/ReadMm0.nasm| INTEL\r
- X64/FxRestore.nasm| INTEL\r
- X64/FxSave.nasm| INTEL\r
- X64/WriteLdtr.nasm| INTEL\r
- X64/ReadLdtr.nasm| INTEL\r
- X64/WriteIdtr.nasm| INTEL\r
- X64/ReadIdtr.nasm| INTEL\r
- X64/WriteGdtr.nasm| INTEL\r
- X64/ReadGdtr.nasm| INTEL\r
- X64/ReadTr.nasm| INTEL\r
- X64/ReadSs.nasm| INTEL\r
- X64/ReadGs.nasm| INTEL\r
- X64/ReadFs.nasm| INTEL\r
- X64/ReadEs.nasm| INTEL\r
- X64/ReadDs.nasm| INTEL\r
- X64/ReadCs.nasm| INTEL\r
- X64/WriteDr7.nasm| INTEL\r
- X64/WriteDr6.nasm| INTEL\r
- X64/WriteDr5.nasm| INTEL\r
- X64/WriteDr4.nasm| INTEL\r
- X64/WriteDr3.nasm| INTEL\r
- X64/WriteDr2.nasm| INTEL\r
- X64/WriteDr1.nasm| INTEL\r
- X64/WriteDr0.nasm| INTEL\r
- X64/ReadDr7.nasm| INTEL\r
- X64/ReadDr6.nasm| INTEL\r
- X64/ReadDr5.nasm| INTEL\r
- X64/ReadDr4.nasm| INTEL\r
- X64/ReadDr3.nasm| INTEL\r
- X64/ReadDr2.nasm| INTEL\r
- X64/ReadDr1.nasm| INTEL\r
- X64/ReadDr0.nasm| INTEL\r
- X64/WriteCr4.nasm| INTEL\r
- X64/WriteCr3.nasm| INTEL\r
- X64/WriteCr2.nasm| INTEL\r
- X64/WriteCr0.nasm| INTEL\r
- X64/ReadCr4.nasm| INTEL\r
- X64/ReadCr3.nasm| INTEL\r
- X64/ReadCr2.nasm| INTEL\r
- X64/ReadCr0.nasm| INTEL\r
- X64/ReadEflags.nasm| INTEL\r
+ X64/TdCall.nasm\r
+ X64/TdVmcall.nasm\r
+ X64/TdProbe.c\r
\r
X64/Non-existing.c\r
Math64.c\r
X86ReadGdtr.c\r
X86Msr.c\r
X86MemoryFence.c | MSFT\r
- X86MemoryFence.c | INTEL\r
X86GetInterruptState.c\r
X86FxSave.c\r
X86FxRestore.c\r
X86PatchInstruction.c\r
X86SpeculationBarrier.c\r
X64/GccInline.c | GCC\r
- X64/SwitchStack.nasm| GCC\r
- X64/SetJump.nasm| GCC\r
- X64/LongJump.nasm| GCC\r
- X64/EnableDisableInterrupts.nasm| GCC\r
- X64/DisablePaging64.nasm| GCC\r
- X64/CpuId.nasm| GCC\r
- X64/CpuIdEx.nasm| GCC\r
- X64/EnableCache.nasm| GCC\r
- X64/DisableCache.nasm| GCC\r
- X64/RdRand.nasm| GCC\r
+ X64/GccInlinePriv.c | GCC\r
+ X64/EnableDisableInterrupts.nasm\r
+ X64/DisablePaging64.nasm\r
+ X64/Pvalidate.nasm\r
+ X64/RdRand.nasm\r
+ X64/RmpAdjust.nasm\r
+ X64/XGetBv.nasm\r
+ X64/XSetBv.nasm\r
+ X64/VmgExit.nasm\r
ChkStkGcc.c | GCC\r
\r
[Sources.EBC]\r
[Sources.ARM]\r
Arm/InternalSwitchStack.c\r
Arm/Unaligned.c\r
- Math64.c | RVCT\r
Math64.c | MSFT\r
\r
- Arm/SwitchStack.asm | RVCT\r
- Arm/SetJumpLongJump.asm | RVCT\r
- Arm/DisableInterrupts.asm | RVCT\r
- Arm/EnableInterrupts.asm | RVCT\r
- Arm/GetInterruptsState.asm | RVCT\r
- Arm/CpuPause.asm | RVCT\r
- Arm/CpuBreakpoint.asm | RVCT\r
- Arm/MemoryFence.asm | RVCT\r
- Arm/SpeculationBarrier.S | RVCT\r
-\r
Arm/SwitchStack.asm | MSFT\r
Arm/SetJumpLongJump.asm | MSFT\r
Arm/DisableInterrupts.asm | MSFT\r
AArch64/CpuBreakpoint.asm | MSFT\r
AArch64/SpeculationBarrier.asm | MSFT\r
\r
+[Sources.RISCV64]\r
+ Math64.c\r
+ Unaligned.c\r
+ RiscV64/InternalSwitchStack.c\r
+ RiscV64/CpuBreakpoint.c\r
+ RiscV64/GetInterruptState.c\r
+ RiscV64/DisableInterrupts.c\r
+ RiscV64/EnableInterrupts.c\r
+ RiscV64/CpuPause.c\r
+ RiscV64/MemoryFence.S | GCC\r
+ RiscV64/RiscVSetJumpLongJump.S | GCC\r
+ RiscV64/RiscVCpuBreakpoint.S | GCC\r
+ RiscV64/RiscVCpuPause.S | GCC\r
+ RiscV64/RiscVInterrupt.S | GCC\r
+ RiscV64/FlushCache.S | GCC\r
+ RiscV64/CpuScratch.S | GCC\r
+ RiscV64/ReadTimer.S | GCC\r
+ RiscV64/RiscVMmu.S | GCC\r
+\r
+[Sources.LOONGARCH64]\r
+ Math64.c\r
+ Unaligned.c\r
+ LoongArch64/InternalSwitchStack.c\r
+ LoongArch64/GetInterruptState.S | GCC\r
+ LoongArch64/EnableInterrupts.S | GCC\r
+ LoongArch64/DisableInterrupts.S | GCC\r
+ LoongArch64/Barrier.S | GCC\r
+ LoongArch64/MemoryFence.S | GCC\r
+ LoongArch64/CpuBreakpoint.S | GCC\r
+ LoongArch64/CpuPause.S | GCC\r
+ LoongArch64/SetJumpLongJump.S | GCC\r
+ LoongArch64/SwitchStack.S | GCC\r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
\r
DebugLib\r
BaseMemoryLib\r
\r
+[LibraryClasses.X64, LibraryClasses.IA32]\r
+ RegisterFilterLib\r
+\r
[Pcd]\r
gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength ## SOMETIMES_CONSUMES\r
gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength ## SOMETIMES_CONSUMES\r
gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength ## SOMETIMES_CONSUMES\r
gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask ## SOMETIMES_CONSUMES\r
+ gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType ## SOMETIMES_CONSUMES\r
\r
[FeaturePcd]\r
gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList ## CONSUMES\r
projects / mirror_edk2.git / blobdiff