## @file\r
# Base Library implementation.\r
#\r
-# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>\r
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
#\r
##\r
LIBRARY_CLASS = BaseLib\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64\r
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64\r
#\r
\r
[Sources]\r
\r
[Sources.Ia32]\r
Ia32/WriteTr.nasm\r
+ Ia32/Lfence.nasm\r
\r
Ia32/Wbinvd.c | MSFT\r
Ia32/WriteMm7.c | MSFT\r
\r
Ia32/GccInline.c | GCC\r
Ia32/Thunk16.nasm | GCC\r
- Ia32/Thunk16.S | XCODE\r
Ia32/EnableDisableInterrupts.nasm| GCC\r
- Ia32/EnableDisableInterrupts.S | GCC\r
Ia32/EnablePaging64.nasm| GCC\r
- Ia32/EnablePaging64.S | GCC\r
Ia32/DisablePaging32.nasm| GCC\r
- Ia32/DisablePaging32.S | GCC\r
Ia32/EnablePaging32.nasm| GCC\r
- Ia32/EnablePaging32.S | GCC\r
Ia32/Mwait.nasm| GCC\r
- Ia32/Mwait.S | GCC\r
Ia32/Monitor.nasm| GCC\r
- Ia32/Monitor.S | GCC\r
Ia32/CpuIdEx.nasm| GCC\r
- Ia32/CpuIdEx.S | GCC\r
Ia32/CpuId.nasm| GCC\r
- Ia32/CpuId.S | GCC\r
Ia32/LongJump.nasm| GCC\r
- Ia32/LongJump.S | GCC\r
Ia32/SetJump.nasm| GCC\r
- Ia32/SetJump.S | GCC\r
Ia32/SwapBytes64.nasm| GCC\r
- Ia32/SwapBytes64.S | GCC\r
Ia32/DivU64x64Remainder.nasm| GCC\r
- Ia32/DivU64x64Remainder.S | GCC\r
Ia32/DivU64x32Remainder.nasm| GCC\r
- Ia32/DivU64x32Remainder.S | GCC\r
Ia32/ModU64x32.nasm| GCC\r
- Ia32/ModU64x32.S | GCC\r
Ia32/DivU64x32.nasm| GCC\r
- Ia32/DivU64x32.S | GCC\r
Ia32/MultU64x64.nasm| GCC\r
- Ia32/MultU64x64.S | GCC\r
Ia32/MultU64x32.nasm| GCC\r
- Ia32/MultU64x32.S | GCC\r
Ia32/RRotU64.nasm| GCC\r
- Ia32/RRotU64.S | GCC\r
Ia32/LRotU64.nasm| GCC\r
- Ia32/LRotU64.S | GCC\r
Ia32/ARShiftU64.nasm| GCC\r
- Ia32/ARShiftU64.S | GCC\r
Ia32/RShiftU64.nasm| GCC\r
- Ia32/RShiftU64.S | GCC\r
Ia32/LShiftU64.nasm| GCC\r
- Ia32/LShiftU64.S | GCC\r
Ia32/EnableCache.nasm| GCC\r
- Ia32/EnableCache.S | GCC\r
Ia32/DisableCache.nasm| GCC\r
- Ia32/DisableCache.S | GCC\r
Ia32/RdRand.nasm| GCC\r
- Ia32/RdRand.S | GCC\r
\r
Ia32/DivS64x64Remainder.c\r
Ia32/InternalSwitchStack.c | MSFT\r
Ia32/InternalSwitchStack.c | INTEL\r
- Ia32/InternalSwitchStack.S | GCC\r
Ia32/InternalSwitchStack.nasm | GCC\r
Ia32/Non-existing.c\r
Unaligned.c\r
X86DisablePaging32.c\r
X86RdRand.c\r
X86PatchInstruction.c\r
+ X86SpeculationBarrier.c\r
\r
[Sources.X64]\r
X64/Thunk16.nasm\r
X64/EnableCache.nasm\r
X64/DisableCache.nasm\r
X64/WriteTr.nasm\r
+ X64/Lfence.nasm\r
\r
X64/CpuBreakpoint.c | MSFT\r
X64/WriteMsr64.c | MSFT\r
X86DisablePaging32.c\r
X86RdRand.c\r
X86PatchInstruction.c\r
+ X86SpeculationBarrier.c\r
X64/GccInline.c | GCC\r
- X64/Thunk16.S | XCODE\r
X64/SwitchStack.nasm| GCC\r
- X64/SwitchStack.S | GCC\r
X64/SetJump.nasm| GCC\r
- X64/SetJump.S | GCC\r
X64/LongJump.nasm| GCC\r
- X64/LongJump.S | GCC\r
X64/EnableDisableInterrupts.nasm| GCC\r
- X64/EnableDisableInterrupts.S | GCC\r
X64/DisablePaging64.nasm| GCC\r
- X64/DisablePaging64.S | GCC\r
X64/CpuId.nasm| GCC\r
- X64/CpuId.S | GCC\r
X64/CpuIdEx.nasm| GCC\r
- X64/CpuIdEx.S | GCC\r
X64/EnableCache.nasm| GCC\r
- X64/EnableCache.S | GCC\r
X64/DisableCache.nasm| GCC\r
- X64/DisableCache.S | GCC\r
X64/RdRand.nasm| GCC\r
- X64/RdRand.S | GCC\r
ChkStkGcc.c | GCC\r
\r
-[Sources.IPF]\r
- Ipf/AccessGp.s\r
- Ipf/ReadCpuid.s\r
- Ipf/ExecFc.s\r
- Ipf/AsmPalCall.s\r
- Ipf/AccessPsr.s\r
- Ipf/AccessPmr.s\r
- Ipf/AccessKr.s\r
- Ipf/AccessKr7.s\r
- Ipf/AccessGcr.s\r
- Ipf/AccessEicr.s\r
- Ipf/AccessDbr.s\r
- Ipf/AccessMsr.s | INTEL\r
- Ipf/AccessMsr.s | GCC\r
- Ipf/AccessMsrDb.s | MSFT\r
- Ipf/InternalFlushCacheRange.s\r
- Ipf/FlushCacheRange.c\r
- Ipf/InternalSwitchStack.c\r
- Ipf/GetInterruptState.s\r
- Ipf/CpuPause.s\r
- Ipf/CpuBreakpoint.c | INTEL\r
- Ipf/CpuBreakpointMsc.c | MSFT\r
- Ipf/AsmCpuMisc.s | GCC\r
- Ipf/Unaligned.c\r
- Ipf/SwitchStack.s\r
- Ipf/LongJmp.s\r
- Ipf/SetJmp.s\r
- Ipf/ReadCr.s\r
- Ipf/ReadAr.s\r
- Ipf/Ia64gen.h\r
- Ipf/Asm.h\r
- Math64.c\r
-\r
[Sources.EBC]\r
Ebc/CpuBreakpoint.c\r
Ebc/SetJumpLongJump.c\r
Ebc/SwitchStack.c\r
+ Ebc/SpeculationBarrier.c\r
Unaligned.c\r
Math64.c\r
\r
Arm/CpuPause.asm | RVCT\r
Arm/CpuBreakpoint.asm | RVCT\r
Arm/MemoryFence.asm | RVCT\r
+ Arm/SpeculationBarrier.S | RVCT\r
\r
Arm/SwitchStack.asm | MSFT\r
Arm/SetJumpLongJump.asm | MSFT\r
Arm/CpuPause.asm | MSFT\r
Arm/CpuBreakpoint.asm | MSFT\r
Arm/MemoryFence.asm | MSFT\r
+ Arm/SpeculationBarrier.asm | MSFT\r
\r
Arm/Math64.S | GCC\r
Arm/SwitchStack.S | GCC\r
Arm/SetJumpLongJump.S | GCC\r
Arm/CpuBreakpoint.S | GCC\r
Arm/MemoryFence.S | GCC\r
+ Arm/SpeculationBarrier.S | GCC\r
\r
[Sources.AARCH64]\r
Arm/InternalSwitchStack.c\r
AArch64/GetInterruptsState.S | GCC\r
AArch64/SetJumpLongJump.S | GCC\r
AArch64/CpuBreakpoint.S | GCC\r
+ AArch64/SpeculationBarrier.S | GCC\r
\r
AArch64/MemoryFence.asm | MSFT\r
AArch64/SwitchStack.asm | MSFT\r
AArch64/GetInterruptsState.asm | MSFT\r
AArch64/SetJumpLongJump.asm | MSFT\r
AArch64/CpuBreakpoint.asm | MSFT\r
+ AArch64/SpeculationBarrier.asm | MSFT\r
\r
[Packages]\r
MdePkg/MdePkg.dec\r
gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength ## SOMETIMES_CONSUMES\r
gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength ## SOMETIMES_CONSUMES\r
gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength ## SOMETIMES_CONSUMES\r
- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask ## SOMETIMES_CONSUMES\r
+ gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask ## SOMETIMES_CONSUMES\r
\r
[FeaturePcd]\r
gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList ## CONSUMES\r
projects / mirror_edk2.git / blobdiff