## @file\r
# Base Library implementation.\r
#\r
-# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>\r
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
#\r
##\r
\r
Ia32/GccInline.c | GCC\r
Ia32/Thunk16.nasm | GCC\r
- Ia32/Thunk16.S | XCODE\r
Ia32/EnableDisableInterrupts.nasm| GCC\r
- Ia32/EnableDisableInterrupts.S | GCC\r
Ia32/EnablePaging64.nasm| GCC\r
- Ia32/EnablePaging64.S | GCC\r
Ia32/DisablePaging32.nasm| GCC\r
- Ia32/DisablePaging32.S | GCC\r
Ia32/EnablePaging32.nasm| GCC\r
- Ia32/EnablePaging32.S | GCC\r
Ia32/Mwait.nasm| GCC\r
- Ia32/Mwait.S | GCC\r
Ia32/Monitor.nasm| GCC\r
- Ia32/Monitor.S | GCC\r
Ia32/CpuIdEx.nasm| GCC\r
- Ia32/CpuIdEx.S | GCC\r
Ia32/CpuId.nasm| GCC\r
- Ia32/CpuId.S | GCC\r
Ia32/LongJump.nasm| GCC\r
- Ia32/LongJump.S | GCC\r
Ia32/SetJump.nasm| GCC\r
- Ia32/SetJump.S | GCC\r
Ia32/SwapBytes64.nasm| GCC\r
- Ia32/SwapBytes64.S | GCC\r
Ia32/DivU64x64Remainder.nasm| GCC\r
- Ia32/DivU64x64Remainder.S | GCC\r
Ia32/DivU64x32Remainder.nasm| GCC\r
- Ia32/DivU64x32Remainder.S | GCC\r
Ia32/ModU64x32.nasm| GCC\r
- Ia32/ModU64x32.S | GCC\r
Ia32/DivU64x32.nasm| GCC\r
- Ia32/DivU64x32.S | GCC\r
Ia32/MultU64x64.nasm| GCC\r
- Ia32/MultU64x64.S | GCC\r
Ia32/MultU64x32.nasm| GCC\r
- Ia32/MultU64x32.S | GCC\r
Ia32/RRotU64.nasm| GCC\r
- Ia32/RRotU64.S | GCC\r
Ia32/LRotU64.nasm| GCC\r
- Ia32/LRotU64.S | GCC\r
Ia32/ARShiftU64.nasm| GCC\r
- Ia32/ARShiftU64.S | GCC\r
Ia32/RShiftU64.nasm| GCC\r
- Ia32/RShiftU64.S | GCC\r
Ia32/LShiftU64.nasm| GCC\r
- Ia32/LShiftU64.S | GCC\r
Ia32/EnableCache.nasm| GCC\r
- Ia32/EnableCache.S | GCC\r
Ia32/DisableCache.nasm| GCC\r
- Ia32/DisableCache.S | GCC\r
Ia32/RdRand.nasm| GCC\r
- Ia32/RdRand.S | GCC\r
\r
Ia32/DivS64x64Remainder.c\r
Ia32/InternalSwitchStack.c | MSFT\r
Ia32/InternalSwitchStack.c | INTEL\r
- Ia32/InternalSwitchStack.S | GCC\r
Ia32/InternalSwitchStack.nasm | GCC\r
Ia32/Non-existing.c\r
Unaligned.c\r
X86PatchInstruction.c\r
X86SpeculationBarrier.c\r
X64/GccInline.c | GCC\r
- X64/Thunk16.S | XCODE\r
X64/SwitchStack.nasm| GCC\r
- X64/SwitchStack.S | GCC\r
X64/SetJump.nasm| GCC\r
- X64/SetJump.S | GCC\r
X64/LongJump.nasm| GCC\r
- X64/LongJump.S | GCC\r
X64/EnableDisableInterrupts.nasm| GCC\r
- X64/EnableDisableInterrupts.S | GCC\r
X64/DisablePaging64.nasm| GCC\r
- X64/DisablePaging64.S | GCC\r
X64/CpuId.nasm| GCC\r
- X64/CpuId.S | GCC\r
X64/CpuIdEx.nasm| GCC\r
- X64/CpuIdEx.S | GCC\r
X64/EnableCache.nasm| GCC\r
- X64/EnableCache.S | GCC\r
X64/DisableCache.nasm| GCC\r
- X64/DisableCache.S | GCC\r
X64/RdRand.nasm| GCC\r
- X64/RdRand.S | GCC\r
ChkStkGcc.c | GCC\r
\r
[Sources.EBC]\r
gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength ## SOMETIMES_CONSUMES\r
gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength ## SOMETIMES_CONSUMES\r
gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength ## SOMETIMES_CONSUMES\r
+ gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask ## SOMETIMES_CONSUMES\r
\r
[FeaturePcd]\r
gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList ## CONSUMES\r