+\r
+/**\r
+ Internal worker function to invalidate a range of instruction cache lines\r
+ in the cache coherency domain of the calling CPU.\r
+\r
+ Internal worker function to invalidate the instruction cache lines specified\r
+ by Address and Length. If Address is not aligned on a cache line boundary,\r
+ then entire instruction cache line containing Address is invalidated. If\r
+ Address + Length is not aligned on a cache line boundary, then the entire\r
+ instruction cache line containing Address + Length -1 is invalidated. This\r
+ function may choose to invalidate the entire instruction cache if that is more\r
+ efficient than invalidating the specified range. If Length is 0, the no instruction\r
+ cache lines are invalidated. Address is returned.\r
+ This function is only available on IPF.\r
+\r
+ @param Address The base address of the instruction cache lines to\r
+ invalidate. If the CPU is in a physical addressing mode, then\r
+ Address is a physical address. If the CPU is in a virtual\r
+ addressing mode, then Address is a virtual address.\r
+\r
+ @param Length The number of bytes to invalidate from the instruction cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InternalFlushCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ );\r
+\r