UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / MdePkg / Library / BaseLib / Ia32 / FlushCacheLine.c

diff --git a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
index 7ad12aba14cbbf07fb8d269ed3a4221b64bbe2be..d6466880be5e00e1f2139878713b73e1975d6e70 100644 (file)
--- a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
+++ b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
@@ -1,20 +1,11 @@
 /** @file\r
   AsmFlushCacheLine function\r
 \r
-  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
-  This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php.\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
-\r
-\r
-\r
 /**\r
   Flushes a cache line from all the instruction and data caches within the\r
   coherency domain of the CPU.\r
@@ -33,11 +24,11 @@
 VOID *\r
 EFIAPI\r
 AsmFlushCacheLine (\r
-  IN      VOID                      *LinearAddress\r
+  IN      VOID  *LinearAddress\r
   )\r
 {\r
   //\r
-  // If the CPU does not support CLFLUSH instruction, \r
+  // If the CPU does not support CLFLUSH instruction,\r
   // then promote flush range to flush entire cache.\r
   //\r
   _asm {\r
@@ -45,14 +36,13 @@ AsmFlushCacheLine (
     cpuid\r
     test    edx, BIT19\r
     jz      NoClflush\r
-    mov     eax, [esp + 4]\r
+    mov     eax, dword ptr [LinearAddress]\r
     clflush [eax]\r
     jmp     Done\r
 NoClflush:\r
     wbinvd\r
 Done:\r
   }\r
-  \r
+\r
   return LinearAddress;\r
 }\r
-\r