Synchronize function comment in h file

[mirror_edk2.git] / MdePkg / Library / BasePciLibCf8 / PciLib.c

diff --git a/MdePkg/Library/BasePciLibCf8/PciLib.c b/MdePkg/Library/BasePciLibCf8/PciLib.c
index 7e21e23174c50979fba95d700540fc80f79ea5ee..e8416c846bc9367a4301611d202e4bc9669de22b 100644 (file)
--- a/MdePkg/Library/BasePciLibCf8/PciLib.c
+++ b/MdePkg/Library/BasePciLibCf8/PciLib.c
@@ -1,7 +1,8 @@
 /** @file\r
-  PCI Library using Port CF8/CFC access.\r
+  PCI Library functions that use I/O ports 0xCF8 and 0xCFC to perform\r
+  PCI Configuration cycles. Layers on top of one PCI CF8 Library instance.\r
 \r
-  Copyright (c) 2006, Intel Corporation<BR>\r
+  Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
   All rights reserved. This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -10,9 +11,40 @@
   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 \r
-  Module Name:  PciLib.c\r
+**/\r
+\r
+\r
+#include <Base.h>\r
+\r
+#include <Library/PciLib.h>\r
+#include <Library/PciCf8Lib.h>\r
+\r
+/**\r
+  Register a PCI device so PCI configuration registers may be accessed after \r
+  SetVirtualAddressMap().\r
+  \r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+  \r
+  @retval RETURN_SUCCESS           The PCI device was registered for runtime access.\r
+  @retval RETURN_UNSUPPORTED       An attempt was made to call this function \r
+                                   after ExitBootServices().\r
+  @retval RETURN_UNSUPPORTED       The resources required to access the PCI device\r
+                                   at runtime could not be mapped.\r
+  @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to\r
+                                   complete the registration.\r
 \r
 **/\r
+RETURN_STATUS\r
+EFIAPI\r
+PciRegisterForRuntimeAccess (\r
+  IN UINTN  Address\r
+  )\r
+{\r
+  return PciCf8RegisterForRuntimeAccess (Address);\r
+}\r
 \r
 /**\r
   Reads an 8-bit PCI configuration register.\r
@@ -58,10 +90,10 @@ UINT8
 EFIAPI\r
 PciWrite8 (\r
   IN      UINTN                     Address,\r
-  IN      UINT8                     Data\r
+  IN      UINT8                     Value\r
   )\r
 {\r
-  return PciCf8Write8 (Address, Data);\r
+  return PciCf8Write8 (Address, Value);\r
 }\r
 \r
 /**\r
@@ -350,6 +382,7 @@ PciBitFieldAndThenOr8 (
   serialized.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
@@ -374,6 +407,7 @@ PciRead16 (
   that all PCI read and write operations are serialized.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
@@ -386,10 +420,10 @@ UINT16
 EFIAPI\r
 PciWrite16 (\r
   IN      UINTN                     Address,\r
-  IN      UINT16                    Data\r
+  IN      UINT16                    Value\r
   )\r
 {\r
-  return PciCf8Write16 (Address, Data);\r
+  return PciCf8Write16 (Address, Value);\r
 }\r
 \r
 /**\r
@@ -404,6 +438,7 @@ PciWrite16 (
   are serialized.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
@@ -434,6 +469,7 @@ PciOr16 (
   serialized.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
@@ -465,6 +501,7 @@ PciAnd16 (
   read and write operations are serialized.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
@@ -493,6 +530,7 @@ PciAndThenOr16 (
   returned.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
@@ -526,6 +564,7 @@ PciBitFieldRead16 (
   16-bit register is returned.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
@@ -564,6 +603,7 @@ PciBitFieldWrite16 (
   are serialized. Extra left bits in OrData are stripped.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
@@ -602,6 +642,7 @@ PciBitFieldOr16 (
   serialized. Extra left bits in AndData are stripped.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
@@ -642,6 +683,7 @@ PciBitFieldAnd16 (
   OrData are stripped.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
@@ -678,6 +720,7 @@ PciBitFieldAndThenOr16 (
   serialized.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
@@ -702,6 +745,7 @@ PciRead32 (
   that all PCI read and write operations are serialized.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
@@ -714,10 +758,10 @@ UINT32
 EFIAPI\r
 PciWrite32 (\r
   IN      UINTN                     Address,\r
-  IN      UINT32                    Data\r
+  IN      UINT32                    Value\r
   )\r
 {\r
-  return PciCf8Write32 (Address, Data);\r
+  return PciCf8Write32 (Address, Value);\r
 }\r
 \r
 /**\r
@@ -732,6 +776,7 @@ PciWrite32 (
   are serialized.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
@@ -762,6 +807,7 @@ PciOr32 (
   serialized.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
@@ -793,6 +839,7 @@ PciAnd32 (
   read and write operations are serialized.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
@@ -821,6 +868,7 @@ PciAndThenOr32 (
   returned.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
@@ -854,6 +902,7 @@ PciBitFieldRead32 (
   32-bit register is returned.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
@@ -892,6 +941,7 @@ PciBitFieldWrite32 (
   are serialized. Extra left bits in OrData are stripped.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
@@ -930,6 +980,7 @@ PciBitFieldOr32 (
   serialized. Extra left bits in AndData are stripped.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
@@ -970,6 +1021,7 @@ PciBitFieldAnd32 (
   OrData are stripped.\r
 \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r