THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
- Module Name: SmbusLib.h\r
+ Module Name: SmbusLib.c\r
\r
**/\r
\r
-RETURN_STATUS\r
-EFIAPI\r
-BaseSmBusLibConstructor (\r
- IN VOID *Param1,\r
- IN VOID *Param2\r
- )\r
-{\r
- return RETURN_SUCCESS;\r
-}\r
+#include "SmbusLibRegisters.h"\r
\r
-//\r
-// BUGBUG: use PCD to retrieve BUS, DEV, FUNC & OFFSET for SMBUS host BAR\r
-//\r
-#define SMBUS_HOST_BUS 0\r
-#define SMBUS_HOST_DEV 31\r
-#define SMBUS_HOST_FUNC 3\r
-#define SMBUS_HOST_SMB_BASE 0x20\r
-\r
-//\r
-// Offsets of registers for SMBUS controller\r
-//\r
-#define R_HST_STS 0\r
-#define R_HST_CNT 2\r
-#define R_HST_CMD 3\r
-#define R_XMIT_SLVA 4\r
-#define R_HST_D0 5\r
-#define R_HST_D1 6\r
-#define R_HOST_BLOCK_DB 7\r
-#define R_PEC 8\r
-#define R_RCV_SLVA 9\r
-#define R_SLV_DATA 0x0a\r
-#define R_AUX_STS 0x0c\r
-#define R_AUX_CTL 0x0d\r
-#define R_SMLINK_PIN_CTL 0x0e\r
-#define R_SMBUS_PIN_CTL 0x0f\r
-#define R_SLV_STS 0x10\r
-#define R_SLV_CMD 0x11\r
-#define R_NOTIFY_DADDR 0x14\r
-#define R_NOTIFY_DLOW 0x16\r
-#define R_NOTIFY_DHIGH 0x17\r
+#define SMBUS_LIB_SLAVE_ADDRESS(SmBusAddress) (((SmBusAddress) >> 1) & 0x7f)\r
+#define SMBUS_LIB_COMMAND(SmBusAddress) (((SmBusAddress) >> 8) & 0xff)\r
+#define SMBUS_LIB_LENGTH(SmBusAddress) (((SmBusAddress) >> 16) & 0x3f)\r
+#define SMBUS_LIB_PEC(SmBusAddress) ((BOOLEAN) (((SmBusAddress) & SMBUS_LIB_PEC_BIT) != 0))\r
+#define SMBUS_LIB_RESEARVED(SmBusAddress) ((SmBusAddress) & ~(((1 << 22) - 2) | SMBUS_LIB_PEC_BIT))\r
\r
//\r
-// Bits in HST_STS\r
+// Replaced by PCD\r
//\r
-#define B_HST_STS_DS 0x80\r
-#define B_HST_STS_INUSE 0x40\r
-#define B_HST_STS_SMBALERT 0x20\r
-#define B_HST_STS_FAILED 0x10\r
-#define B_HST_STS_BUS_ERR 0x08\r
-#define B_HST_STS_DEV_ERR 0x04\r
-#define B_HST_STS_INTR 0x02\r
-#define B_HST_STS_BUSY 0x01\r
-#define B_HST_STS_ERR ( B_HST_STS_BUS_ERR | \\r
- B_HST_STS_DEV_ERR | \\r
- B_HST_STS_FAILED )\r
-#define B_HST_STS_ALL ( B_HST_STS_DS | \\r
- B_HST_STS_INUSE | \\r
- B_HST_STS_SMBALERT | \\r
- B_HST_STS_ERR | \\r
- B_HST_STS_INTR )\r
+#define ICH_SMBUS_IO_BASE_ADDRESS 0xEFA0\r
\r
-//\r
-// Bits in HST_CNT\r
-//\r
-#define B_HST_CNT_PEC 0x80\r
-#define B_HST_CNT_START 0x40\r
-#define B_HST_CNT_LAST_BYTE 0x20\r
-#define B_HST_CNT_SMB_CMD 0x1c\r
-#define B_HST_CNT_KILL 0x02\r
-#define B_HST_CNT_INTREN 0x01\r
+/**\r
+ Reads an 8-bit register on ICH SMBUS controller.\r
\r
-//\r
-// SMBUS Protocols\r
-//\r
-#define B_SMB_CMD_QUICK 0\r
-#define B_SMB_CMD_BYTE 1\r
-#define B_SMB_CMD_BYTE_DATA 2\r
-#define B_SMB_CMD_WORD_DATA 3\r
-#define B_SMB_CMD_PROCESS_CALL 4\r
-#define B_SMB_CMD_BLOCK 5\r
-#define B_SMB_CMD_I2C 6\r
-#define B_SMB_CMD_BLOCK_PROCESS 7\r
+ This internal function reads an SMBUS register specified by Offset.\r
\r
-//\r
-// Bits in AUX_CTL\r
-//\r
-#define B_AUX_CTL_E32B 0x02\r
-#define B_AUX_CTL_AAC 0x01\r
+ @param Offset The offset of SMBUS register.\r
\r
-//\r
-// SMBUS Rd/Wr control\r
-//\r
-#define B_SMBUS_READ 1\r
-#define B_SMBUS_WRITE 0\r
+ @return The value read.\r
\r
-static\r
-UINT16\r
-EFIAPI\r
-GetSmBusIOBaseAddress (\r
- VOID\r
+**/\r
+UINT8\r
+InternalSmBusIoRead8 (\r
+ IN UINTN Offset\r
)\r
{\r
- UINT32 SmbusBar;\r
-\r
- SmbusBar = PciRead32 (\r
- PCI_LIB_ADDRESS (\r
- SMBUS_HOST_BUS,\r
- SMBUS_HOST_DEV,\r
- SMBUS_HOST_FUNC,\r
- SMBUS_HOST_SMB_BASE\r
- )\r
- );\r
- ASSERT ((SmbusBar & 0xffff001f) == 1);\r
- return (UINT16)(SmbusBar & ~1);\r
+ return IoRead8 (ICH_SMBUS_IO_BASE_ADDRESS + Offset);\r
}\r
\r
-static\r
-BOOLEAN\r
-EFIAPI\r
-SmBusAcquire (\r
- IN UINT16 SmBusBase\r
- )\r
-{\r
- UINT8 HstSts;\r
+/**\r
+ Writes an 8-bit register on ICH SMBUS controller.\r
\r
- HstSts = IoRead8 (SmBusBase + R_HST_STS);\r
- if (HstSts & B_HST_STS_INUSE) {\r
- return FALSE;\r
- }\r
+ This internal function writes an SMBUS register specified by Offset.\r
\r
- //\r
- // BUGBUG: Dead loop may occur here\r
- //\r
- while (HstSts & B_HST_STS_BUSY) {\r
- ASSERT (HstSts & B_HST_STS_INUSE);\r
- HstSts = IoRead8 (SmBusBase + R_HST_STS);\r
- }\r
- return TRUE;\r
-}\r
+ @param Offset The offset of SMBUS register.\r
+ @param Value The value to write to SMBUS register.\r
\r
-static\r
-VOID\r
-EFIAPI\r
-SmBusStart (\r
- IN UINT16 SmBusBase,\r
- IN UINT8 SmBusProtocol,\r
- IN UINT8 SlaveAddress\r
+ @return The value written the SMBUS register.\r
+\r
+**/\r
+UINT8\r
+InternalSmBusIoWrite8 (\r
+ IN UINTN Offset,\r
+ IN UINT8 Value\r
)\r
{\r
- IoWrite8 (SmBusBase + R_XMIT_SLVA, SlaveAddress);\r
- IoWrite8 (\r
- SmBusBase + R_HST_CNT,\r
- IoBitFieldWrite8 (SmBusBase + R_HST_CNT, 2, 4, SmBusProtocol) |\r
- B_HST_CNT_START\r
- );\r
+ return IoWrite8 (ICH_SMBUS_IO_BASE_ADDRESS + Offset, Value);\r
}\r
\r
-static\r
-UINT8\r
-EFIAPI\r
-SmBusWait (\r
- IN UINT16 SmBusBase\r
+/**\r
+ Acquires the ownership of SMBUS.\r
+\r
+ This internal function reads the host state register.\r
+ If the SMBUS is not available, RETURN_TIMEOUT is returned;\r
+ Otherwise, it performs some basic initializations and returns\r
+ RETURN_SUCCESS. \r
+\r
+ @retval RETURN_SUCCESS The SMBUS command was executed successfully.\r
+ @retval RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.\r
+\r
+**/\r
+RETURN_STATUS\r
+InternalSmBusAcquire (\r
+ VOID \r
)\r
{\r
- UINT8 HstSts;\r
+ UINT8 HostStatus;\r
\r
- while (((HstSts = IoRead8 (SmBusBase + R_HST_STS)) & B_HST_STS_INTR) == 0);\r
- return HstSts;\r
+ HostStatus = InternalSmBusIoRead8 (SMBUS_R_HST_STS);\r
+ if ((HostStatus & SMBUS_B_INUSE_STS) != 0) {\r
+ return RETURN_TIMEOUT;\r
+ } else if ((HostStatus & SMBUS_B_HOST_BUSY) != 0) {\r
+ //\r
+ // Clear host status register and exit.\r
+ //\r
+ InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_HSTS_ALL);\r
+ return RETURN_TIMEOUT;\r
+ }\r
+ //\r
+ // Clear out any odd status information (Will Not Clear In Use).\r
+ //\r
+ InternalSmBusIoWrite8 (SMBUS_R_HST_STS, HostStatus);\r
+ \r
+ return RETURN_SUCCESS;\r
}\r
\r
-static\r
-VOID\r
-EFIAPI\r
-SmBusCleanup (\r
- IN UINT16 SmBusBase\r
+/**\r
+ Starts the SMBUS transaction and waits until the end.\r
+\r
+ This internal function start the SMBUS transaction and waits until the transaction\r
+ of SMBUS is over by polling the INTR bit of Host status register.\r
+ If the SMBUS is not available, RETURN_TIMEOUT is returned;\r
+ Otherwise, it performs some basic initializations and returns\r
+ RETURN_SUCCESS.\r
+ \r
+ @param HostControl The Host control command to start SMBUS transaction.\r
+\r
+ @retval RETURN_SUCCESS The SMBUS command was executed successfully.\r
+ @retval RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect).\r
+ @retval RETURN_DEVICE_ERROR The request was not completed because a failure reflected\r
+ in the Host Status Register bit. Device errors are\r
+ a result of a transaction collision, illegal command field,\r
+ unclaimed cycle (host initiated), or bus errors (collisions).\r
+\r
+**/\r
+RETURN_STATUS\r
+InternalSmBusStart (\r
+ IN UINT8 HostControl\r
)\r
{\r
- IoWrite8 (SmBusBase + R_HST_STS, B_HST_STS_ALL);\r
+ UINT8 HostStatus;\r
+ UINT8 AuxiliaryStatus;\r
+\r
+ //\r
+ // Set Host Control Register (Initiate Operation, Interrupt disabled).\r
+ //\r
+ InternalSmBusIoWrite8 (SMBUS_R_HST_CTL, HostControl + SMBUS_B_START);\r
+\r
+ do {\r
+ //\r
+ // Poll INTR bit of Host Status Register.\r
+ //\r
+ HostStatus = InternalSmBusIoRead8 (SMBUS_R_HST_STS);\r
+ } while ((HostStatus & (SMBUS_B_INTR | SMBUS_B_ERROR | SMBUS_B_BYTE_DONE_STS)) == 0);\r
+ \r
+ if ((HostStatus & SMBUS_B_ERROR) == 0) {\r
+ return RETURN_SUCCESS;\r
+ }\r
+ //\r
+ // Clear error bits of Host Status Register.\r
+ //\r
+ InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_ERROR);\r
+ //\r
+ // Read Auxiliary Status Register to judge CRC error.\r
+ //\r
+ AuxiliaryStatus = InternalSmBusIoRead8 (SMBUS_R_AUX_STS);\r
+ if ((AuxiliaryStatus & SMBUS_B_CRCE) != 0) {\r
+ return RETURN_CRC_ERROR;\r
+ }\r
+\r
+ return RETURN_DEVICE_ERROR;\r
}\r
\r
-static\r
-RETURN_STATUS\r
-EFIAPI\r
-SmBusQuick (\r
- IN UINT8 SmBusAddress\r
+/**\r
+ Executes an SMBUS quick, byte or word command.\r
+\r
+ This internal function executes an SMBUS quick, byte or word commond.\r
+ If Status is not NULL, then the status of the executed command is returned in Status.\r
+\r
+ @param HostControl The value of Host Control Register to set. \r
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,\r
+ SMBUS Command, SMBUS Data Length, and PEC.\r
+ @param Value The byte/word write to the SMBUS.\r
+ @param Status Return status for the executed command.\r
+ This is an optional parameter and may be NULL.\r
+\r
+ @return The byte/word read from the SMBUS.\r
+\r
+**/\r
+UINT16\r
+InternalSmBusNonBlock (\r
+ IN UINT8 HostControl,\r
+ IN UINTN SmBusAddress,\r
+ IN UINT16 Value,\r
+ OUT RETURN_STATUS *Status\r
)\r
{\r
- RETURN_STATUS Status;\r
- UINT16 SmBusBase;\r
+ RETURN_STATUS ReturnStatus;\r
+ UINT8 AuxiliaryControl;\r
\r
- SmBusBase = GetSmBusIOBaseAddress ();\r
- if (!SmBusAcquire (SmBusBase)) {\r
- return RETURN_TIMEOUT;\r
+ //\r
+ // Try to acquire the ownership of ICH SMBUS.\r
+ //\r
+ ReturnStatus = InternalSmBusAcquire ();\r
+ if (RETURN_ERROR (ReturnStatus)) {\r
+ goto Done;\r
}\r
+ //\r
+ // Set the appropriate Host Control Register and auxiliary Control Register.\r
+ //\r
+ AuxiliaryControl = 0;\r
+ if (SMBUS_LIB_PEC (SmBusAddress)) {\r
+ AuxiliaryControl |= SMBUS_B_AAC;\r
+ HostControl |= SMBUS_B_PEC_EN;\r
+ }\r
+ //\r
+ // Set Host Commond Register.\r
+ //\r
+ InternalSmBusIoWrite8 (SMBUS_R_HST_CMD, (UINT8) SMBUS_LIB_COMMAND (SmBusAddress));\r
+ //\r
+ // Write value to Host Data 0 and Host Data 1 Registers.\r
+ //\r
+ InternalSmBusIoWrite8 (SMBUS_R_HST_D0, (UINT8) Value);\r
+ InternalSmBusIoWrite8 (SMBUS_R_HST_D1, (UINT8) (Value >> 8));\r
+ //\r
+ // Set Auxiliary Control Regiester.\r
+ //\r
+ InternalSmBusIoWrite8 (SMBUS_R_AUX_CTL, AuxiliaryControl);\r
+ //\r
+ // Set SMBUS slave address for the device to send/receive from.\r
+ //\r
+ InternalSmBusIoWrite8 (SMBUS_R_XMIT_SLVA, (UINT8) SmBusAddress);\r
+ //\r
+ // Start the SMBUS transaction and wait for the end.\r
+ //\r
+ ReturnStatus = InternalSmBusStart (HostControl);\r
+ //\r
+ // Read value from Host Data 0 and Host Data 1 Registers.\r
+ //\r
+ Value = InternalSmBusIoRead8 (SMBUS_R_HST_D1) << 8;\r
+ Value |= InternalSmBusIoRead8 (SMBUS_R_HST_D0);\r
+ //\r
+ // Clear Host Status Register and Auxiliary Status Register.\r
+ //\r
+ InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_HSTS_ALL);\r
+ InternalSmBusIoWrite8 (SMBUS_R_AUX_STS, SMBUS_B_CRCE);\r
\r
- SmBusStart (SmBusAddress, B_SMB_CMD_QUICK, SmBusAddress);\r
- if (SmBusWait (SmBusAddress) & B_HST_STS_ERR) {\r
- Status = RETURN_DEVICE_ERROR;\r
- } else {\r
- Status = RETURN_SUCCESS;\r
+Done:\r
+ if (Status != NULL) {\r
+ *Status = ReturnStatus;\r
}\r
\r
- SmBusCleanup (SmBusAddress);\r
- return Status;\r
+ return Value;\r
}\r
\r
+/**\r
+ Executes an SMBUS quick read command.\r
+\r
+ Executes an SMBUS quick read command on the SMBUS device specified by SmBusAddress.\r
+ Only the SMBUS slave address field of SmBusAddress is required.\r
+ If Status is not NULL, then the status of the executed command is returned in Status.\r
+ If PEC is set in SmBusAddress, then ASSERT().\r
+ If Command in SmBusAddress is not zero, then ASSERT().\r
+ If Length in SmBusAddress is not zero, then ASSERT().\r
+ If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,\r
+ SMBUS Command, SMBUS Data Length, and PEC.\r
+ @param Status Return status for the executed command.\r
+ This is an optional parameter and may be NULL.\r
+\r
+**/\r
VOID\r
EFIAPI\r
SmBusQuickRead (\r
- IN UINTN SmBusAddress,\r
- OUT RETURN_STATUS *Status\r
+ IN UINTN SmBusAddress,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- RETURN_STATUS RetStatus;\r
-\r
- ASSERT ((SmBusAddress & ~0xfe) == 0);\r
- RetStatus = SmBusQuick ((UINT8)SmBusAddress | B_SMBUS_READ);\r
- if (Status) {\r
- *Status = RetStatus;\r
- }\r
+ ASSERT (!SMBUS_LIB_PEC (SmBusAddress));\r
+ ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);\r
+ ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
+ ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
+\r
+ InternalSmBusNonBlock (\r
+ SMBUS_V_SMB_CMD_QUICK,\r
+ SmBusAddress | SMBUS_B_READ,\r
+ 0,\r
+ Status\r
+ );\r
}\r
\r
-BOOLEAN\r
-EFIAPI\r
-SmBusQuickWrite (\r
- IN UINTN SmBusAddress,\r
- OUT RETURN_STATUS *Status\r
- )\r
-{\r
- RETURN_STATUS RetStatus;\r
+/**\r
+ Executes an SMBUS quick write command.\r
\r
- ASSERT ((SmBusAddress & ~0xfe) == 0);\r
- RetStatus = SmBusQuick ((UINT8)SmBusAddress | B_SMBUS_WRITE);\r
- if (Status) {\r
- *Status = RetStatus;\r
- }\r
- return (BOOLEAN)!RETURN_ERROR (RetStatus);\r
-}\r
+ Executes an SMBUS quick write command on the SMBUS device specified by SmBusAddress.\r
+ Only the SMBUS slave address field of SmBusAddress is required.\r
+ If Status is not NULL, then the status of the executed command is returned in Status.\r
+ If PEC is set in SmBusAddress, then ASSERT().\r
+ If Command in SmBusAddress is not zero, then ASSERT().\r
+ If Length in SmBusAddress is not zero, then ASSERT().\r
+ If any reserved bits of SmBusAddress are set, then ASSERT().\r
\r
-static\r
-UINT16\r
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,\r
+ SMBUS Command, SMBUS Data Length, and PEC.\r
+ @param Status Return status for the executed command.\r
+ This is an optional parameter and may be NULL.\r
+\r
+**/\r
+VOID\r
EFIAPI\r
-SmBusByteWord (\r
- IN UINTN SmBusAddress,\r
- IN UINT16 Value,\r
- IN UINT8 SmBusProtocol,\r
- OUT RETURN_STATUS *Status\r
+SmBusQuickWrite (\r
+ IN UINTN SmBusAddress,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- RETURN_STATUS RetStatus;\r
- UINT16 SmBusBase;\r
-\r
- if (Status == NULL) {\r
- Status = &RetStatus;\r
- }\r
-\r
- SmBusBase = GetSmBusIOBaseAddress ();\r
- if (!SmBusAcquire (SmBusBase)) {\r
- *Status = RETURN_TIMEOUT;\r
- return Value;\r
- }\r
+ ASSERT (!SMBUS_LIB_PEC (SmBusAddress));\r
+ ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);\r
+ ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
+ ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
+\r
+ InternalSmBusNonBlock (\r
+ SMBUS_V_SMB_CMD_QUICK,\r
+ SmBusAddress | SMBUS_B_WRITE,\r
+ 0,\r
+ Status\r
+ );\r
+}\r
\r
- IoWrite8 (SmBusBase + R_HST_CMD, (UINT8)(SmBusAddress >> 8));\r
- IoWrite8 (SmBusBase + R_HST_D0, (UINT8)Value);\r
- IoWrite8 (SmBusBase + R_HST_D1, (UINT8)(Value >> 8));\r
- if ((INTN)SmBusAddress < 0) {\r
- IoOr8 (SmBusBase + R_HST_CNT, B_HST_CNT_PEC);\r
- IoOr8 (SmBusBase + R_AUX_CTL, B_AUX_CTL_AAC);\r
- } else {\r
- IoAnd8 (SmBusBase + R_HST_CNT, (UINT8)~B_HST_CNT_PEC);\r
- IoAnd8 (SmBusBase + R_AUX_CTL, (UINT8)~B_AUX_CTL_AAC);\r
- }\r
+/**\r
+ Executes an SMBUS receive byte command.\r
\r
- SmBusStart (SmBusBase, SmBusProtocol, (UINT8)SmBusAddress);\r
+ Executes an SMBUS receive byte command on the SMBUS device specified by SmBusAddress.\r
+ Only the SMBUS slave address field of SmBusAddress is required.\r
+ The byte received from the SMBUS is returned.\r
+ If Status is not NULL, then the status of the executed command is returned in Status.\r
+ If Command in SmBusAddress is not zero, then ASSERT().\r
+ If Length in SmBusAddress is not zero, then ASSERT().\r
+ If any reserved bits of SmBusAddress are set, then ASSERT().\r
\r
- if (SmBusWait (SmBusBase) & B_HST_STS_ERR) {\r
- *Status = RETURN_DEVICE_ERROR;\r
- } else {\r
- *Status = RETURN_SUCCESS;\r
- Value = IoRead8 (SmBusBase + R_HST_D0);\r
- Value |= (UINT16)IoRead8 (SmBusBase + R_HST_D1) << 8;\r
- }\r
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,\r
+ SMBUS Command, SMBUS Data Length, and PEC.\r
+ @param Status Return status for the executed command.\r
+ This is an optional parameter and may be NULL.\r
\r
- SmBusCleanup (SmBusBase);\r
- return Value;\r
-}\r
+ @return The byte received from the SMBUS.\r
\r
+**/\r
UINT8\r
EFIAPI\r
SmBusReceiveByte (\r
- IN UINTN SmBusAddress,\r
- OUT RETURN_STATUS *Status\r
+ IN UINTN SmBusAddress,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- ASSERT ((SmBusAddress & ~(0xfe | MAX_BIT)) == 0);\r
- return (UINT8)SmBusByteWord (\r
- SmBusAddress | B_SMBUS_READ,\r
- 0,\r
- B_SMB_CMD_BYTE,\r
- Status\r
- );\r
+ ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);\r
+ ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
+ ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
+\r
+ return (UINT8) InternalSmBusNonBlock (\r
+ SMBUS_V_SMB_CMD_BYTE,\r
+ SmBusAddress | SMBUS_B_READ,\r
+ 0,\r
+ Status\r
+ );\r
}\r
\r
+/**\r
+ Executes an SMBUS send byte command.\r
+\r
+ Executes an SMBUS send byte command on the SMBUS device specified by SmBusAddress.\r
+ The byte specified by Value is sent.\r
+ Only the SMBUS slave address field of SmBusAddress is required. Value is returned.\r
+ If Status is not NULL, then the status of the executed command is returned in Status.\r
+ If Command in SmBusAddress is not zero, then ASSERT().\r
+ If Length in SmBusAddress is not zero, then ASSERT().\r
+ If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,\r
+ SMBUS Command, SMBUS Data Length, and PEC.\r
+ @param Value The 8-bit value to send.\r
+ @param Status Return status for the executed command.\r
+ This is an optional parameter and may be NULL.\r
+\r
+ @return The parameter of Value.\r
+\r
+**/\r
UINT8\r
EFIAPI\r
SmBusSendByte (\r
- IN UINTN SmBusAddress,\r
- IN UINT8 Value,\r
- OUT RETURN_STATUS *Status\r
+ IN UINTN SmBusAddress,\r
+ IN UINT8 Value,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- ASSERT ((SmBusAddress & ~(0xfe | MAX_BIT)) == 0);\r
- return (UINT8)SmBusByteWord (\r
- SmBusAddress | B_SMBUS_WRITE,\r
- Value,\r
- B_SMB_CMD_BYTE,\r
- Status\r
- );\r
+ ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);\r
+ ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
+ ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
+\r
+ return (UINT8) InternalSmBusNonBlock (\r
+ SMBUS_V_SMB_CMD_BYTE,\r
+ SmBusAddress | SMBUS_B_WRITE,\r
+ Value,\r
+ Status\r
+ );\r
}\r
\r
+/**\r
+ Executes an SMBUS read data byte command.\r
+\r
+ Executes an SMBUS read data byte command on the SMBUS device specified by SmBusAddress.\r
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.\r
+ The 8-bit value read from the SMBUS is returned.\r
+ If Status is not NULL, then the status of the executed command is returned in Status.\r
+ If Length in SmBusAddress is not zero, then ASSERT().\r
+ If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,\r
+ SMBUS Command, SMBUS Data Length, and PEC.\r
+ @param Status Return status for the executed command.\r
+ This is an optional parameter and may be NULL.\r
+\r
+ @return The byte read from the SMBUS.\r
+\r
+**/\r
UINT8\r
EFIAPI\r
SmBusReadDataByte (\r
- IN UINTN SmBusAddress,\r
- OUT RETURN_STATUS *Status\r
+ IN UINTN SmBusAddress,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- ASSERT ((SmBusAddress & ~(0xfffe | MAX_BIT)) == 0);\r
- return (UINT8)SmBusByteWord (\r
- SmBusAddress | B_SMBUS_READ,\r
- 0,\r
- B_SMB_CMD_BYTE_DATA,\r
- Status\r
- );\r
+ ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
+ ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
+\r
+ return (UINT8) InternalSmBusNonBlock (\r
+ SMBUS_V_SMB_CMD_BYTE_DATA,\r
+ SmBusAddress | SMBUS_B_READ,\r
+ 0,\r
+ Status\r
+ );\r
}\r
\r
+/**\r
+ Executes an SMBUS write data byte command.\r
+\r
+ Executes an SMBUS write data byte command on the SMBUS device specified by SmBusAddress.\r
+ The 8-bit value specified by Value is written.\r
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.\r
+ Value is returned.\r
+ If Status is not NULL, then the status of the executed command is returned in Status.\r
+ If Length in SmBusAddress is not zero, then ASSERT().\r
+ If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,\r
+ SMBUS Command, SMBUS Data Length, and PEC.\r
+ @param Value The 8-bit value to write.\r
+ @param Status Return status for the executed command.\r
+ This is an optional parameter and may be NULL.\r
+\r
+ @return The parameter of Value.\r
+\r
+**/\r
UINT8\r
EFIAPI\r
SmBusWriteDataByte (\r
- IN UINTN SmBusAddress,\r
- IN UINT8 Value,\r
- OUT RETURN_STATUS *Status\r
+ IN UINTN SmBusAddress,\r
+ IN UINT8 Value,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- ASSERT (((UINT32)SmBusAddress & ~(0xfffe | MAX_BIT)) == 0);\r
- return (UINT8)SmBusByteWord (\r
- SmBusAddress | B_SMBUS_WRITE,\r
- Value,\r
- B_SMB_CMD_BYTE_DATA,\r
- Status\r
- );\r
+ ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
+ ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
+\r
+ return (UINT8) InternalSmBusNonBlock (\r
+ SMBUS_V_SMB_CMD_BYTE_DATA,\r
+ SmBusAddress | SMBUS_B_WRITE,\r
+ Value,\r
+ Status\r
+ );\r
}\r
\r
+/**\r
+ Executes an SMBUS read data word command.\r
+\r
+ Executes an SMBUS read data word command on the SMBUS device specified by SmBusAddress.\r
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.\r
+ The 16-bit value read from the SMBUS is returned.\r
+ If Status is not NULL, then the status of the executed command is returned in Status.\r
+ If Length in SmBusAddress is not zero, then ASSERT().\r
+ If any reserved bits of SmBusAddress are set, then ASSERT().\r
+ \r
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,\r
+ SMBUS Command, SMBUS Data Length, and PEC.\r
+ @param Status Return status for the executed command.\r
+ This is an optional parameter and may be NULL.\r
+\r
+ @return The byte read from the SMBUS.\r
+\r
+**/\r
UINT16\r
EFIAPI\r
SmBusReadDataWord (\r
- IN UINTN SmBusAddress,\r
- OUT RETURN_STATUS *Status\r
+ IN UINTN SmBusAddress,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- ASSERT ((SmBusAddress & ~(0xfffe | MAX_BIT)) == 0);\r
- return SmBusByteWord (\r
- SmBusAddress | B_SMBUS_READ,\r
+ ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
+ ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
+\r
+ return InternalSmBusNonBlock (\r
+ SMBUS_V_SMB_CMD_WORD_DATA,\r
+ SmBusAddress | SMBUS_B_READ,\r
0,\r
- B_SMB_CMD_WORD_DATA,\r
Status\r
);\r
}\r
\r
+/**\r
+ Executes an SMBUS write data word command.\r
+\r
+ Executes an SMBUS write data word command on the SMBUS device specified by SmBusAddress.\r
+ The 16-bit value specified by Value is written.\r
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.\r
+ Value is returned.\r
+ If Status is not NULL, then the status of the executed command is returned in Status.\r
+ If Length in SmBusAddress is not zero, then ASSERT().\r
+ If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,\r
+ SMBUS Command, SMBUS Data Length, and PEC.\r
+ @param Value The 16-bit value to write.\r
+ @param Status Return status for the executed command.\r
+ This is an optional parameter and may be NULL.\r
+\r
+ @return The parameter of Value.\r
+\r
+**/\r
UINT16\r
EFIAPI\r
SmBusWriteDataWord (\r
- IN UINTN SmBusAddress,\r
- IN UINT16 Value,\r
- OUT RETURN_STATUS *Status\r
+ IN UINTN SmBusAddress,\r
+ IN UINT16 Value,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- ASSERT ((SmBusAddress & ~(0xfffe | MAX_BIT)) == 0);\r
- return SmBusByteWord (\r
- SmBusAddress | B_SMBUS_WRITE,\r
+ ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
+ ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
+\r
+ return InternalSmBusNonBlock (\r
+ SMBUS_V_SMB_CMD_WORD_DATA,\r
+ SmBusAddress | SMBUS_B_WRITE,\r
Value,\r
- B_SMB_CMD_WORD_DATA,\r
Status\r
);\r
}\r
\r
+/**\r
+ Executes an SMBUS process call command.\r
+\r
+ Executes an SMBUS process call command on the SMBUS device specified by SmBusAddress.\r
+ The 16-bit value specified by Value is written.\r
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.\r
+ The 16-bit value returned by the process call command is returned.\r
+ If Status is not NULL, then the status of the executed command is returned in Status.\r
+ If Length in SmBusAddress is not zero, then ASSERT().\r
+ If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,\r
+ SMBUS Command, SMBUS Data Length, and PEC.\r
+ @param Value The 16-bit value to write.\r
+ @param Status Return status for the executed command.\r
+ This is an optional parameter and may be NULL.\r
+\r
+ @return The 16-bit value returned by the process call command.\r
+\r
+**/\r
UINT16\r
EFIAPI\r
SmBusProcessCall (\r
- IN UINTN SmBusAddress,\r
- IN UINT16 Value,\r
- OUT RETURN_STATUS *Status\r
+ IN UINTN SmBusAddress,\r
+ IN UINT16 Value,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- ASSERT ((SmBusAddress & ~(0xfffe | MAX_BIT)) == 0);\r
- return SmBusByteWord (\r
- SmBusAddress | B_SMBUS_WRITE,\r
+ ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
+ ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
+\r
+ return InternalSmBusNonBlock (\r
+ SMBUS_V_SMB_CMD_PROCESS_CALL,\r
+ SmBusAddress | SMBUS_B_WRITE,\r
Value,\r
- B_SMB_CMD_PROCESS_CALL,\r
Status\r
);\r
}\r
\r
-static\r
+/**\r
+ Executes an SMBUS block command.\r
+\r
+ Executes an SMBUS block read, block write and block write-block read command\r
+ on the SMBUS device specified by SmBusAddress.\r
+ Bytes are read from the SMBUS and stored in Buffer.\r
+ The number of bytes read is returned, and will never return a value larger than 32-bytes.\r
+ If Status is not NULL, then the status of the executed command is returned in Status.\r
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.\r
+ SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes.\r
+\r
+ @param HostControl The value of Host Control Register to set. \r
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,\r
+ SMBUS Command, SMBUS Data Length, and PEC.\r
+ @param WriteBuffer Pointer to the buffer of bytes to write to the SMBUS.\r
+ @param ReadBuffer Pointer to the buffer of bytes to read from the SMBUS.\r
+ @param Status Return status for the executed command.\r
+ This is an optional parameter and may be NULL.\r
+\r
+ @return The number of bytes read from the SMBUS.\r
+\r
+**/\r
UINTN\r
-EFIAPI\r
-SmBusBlock (\r
- IN UINTN SmBusAddress,\r
- IN UINT8 SmBusProtocol,\r
- IN VOID *InBuffer,\r
- OUT VOID *OutBuffer,\r
- OUT RETURN_STATUS *Status\r
+InternalSmBusBlock (\r
+ IN UINT8 HostControl,\r
+ IN UINTN SmBusAddress,\r
+ IN UINT8 *WriteBuffer,\r
+ OUT UINT8 *ReadBuffer,\r
+ OUT RETURN_STATUS *Status\r
)\r
{\r
- RETURN_STATUS RetStatus;\r
- UINT16 SmBusBase;\r
- UINTN Index;\r
- UINTN BytesCount;\r
-\r
- BytesCount = (UINT8)(SmBusAddress >> 16);\r
- ASSERT (BytesCount <= 32);\r
-\r
- if (Status == NULL) {\r
- Status = &RetStatus;\r
+ RETURN_STATUS ReturnStatus;\r
+ UINTN Index;\r
+ UINTN BytesCount;\r
+ UINT8 AuxiliaryControl;\r
+ \r
+ BytesCount = SMBUS_LIB_LENGTH (SmBusAddress);\r
+ //\r
+ // Try to acquire the ownership of ICH SMBUS.\r
+ //\r
+ ReturnStatus = InternalSmBusAcquire ();\r
+ if (RETURN_ERROR (ReturnStatus)) {\r
+ goto Done;\r
}\r
-\r
- SmBusBase = GetSmBusIOBaseAddress ();\r
- if (!SmBusAcquire (SmBusBase)) {\r
- *Status = RETURN_TIMEOUT;\r
- return 0;\r
+ //\r
+ // Set the appropriate Host Control Register and auxiliary Control Register.\r
+ //\r
+ AuxiliaryControl = SMBUS_B_E32B;\r
+ if (SMBUS_LIB_PEC (SmBusAddress)) {\r
+ AuxiliaryControl |= SMBUS_B_AAC;\r
+ HostControl |= SMBUS_B_PEC_EN;\r
}\r
-\r
- IoWrite8 (SmBusBase + R_HST_CMD, (UINT8)(SmBusAddress >> 8));\r
- IoWrite8 (SmBusBase + R_HST_D0, (UINT8)BytesCount);\r
- if ((INTN)SmBusAddress < 0) {\r
- IoOr8 (SmBusBase + R_HST_CNT, B_HST_CNT_PEC);\r
- IoOr8 (SmBusBase + R_AUX_CTL, B_AUX_CTL_AAC);\r
- } else {\r
- IoAnd8 (SmBusBase + R_HST_CNT, (UINT8)~B_HST_CNT_PEC);\r
- IoAnd8 (SmBusBase + R_AUX_CTL, (UINT8)~B_AUX_CTL_AAC);\r
+ //\r
+ // Set Host Command Register.\r
+ //\r
+ InternalSmBusIoWrite8 (SMBUS_R_HST_CMD, (UINT8) SMBUS_LIB_COMMAND (SmBusAddress));\r
+ //\r
+ // Set Auxiliary Control Regiester.\r
+ //\r
+ InternalSmBusIoWrite8 (SMBUS_R_AUX_CTL, AuxiliaryControl);\r
+ //\r
+ // Clear byte pointer of 32-byte buffer.\r
+ //\r
+ InternalSmBusIoRead8 (SMBUS_R_HST_CTL);\r
+\r
+ if (WriteBuffer != NULL) {\r
+ //\r
+ // Write the number of block to Host Block Data Byte Register.\r
+ //\r
+ InternalSmBusIoWrite8 (SMBUS_R_HST_D0, (UINT8) BytesCount);\r
+ //\r
+ // Write data block to Host Block Data Register.\r
+ //\r
+ for (Index = 0; Index < BytesCount; Index++) {\r
+ InternalSmBusIoWrite8 (SMBUS_R_HOST_BLOCK_DB, WriteBuffer[Index]);\r
+ }\r
}\r
-\r
//\r
- // BUGBUG: E32B bit does not exist in ICH3 or earlier\r
+ // Set SMBUS slave address for the device to send/receive from.\r
//\r
- IoOr8 (SmBusBase + R_AUX_CTL, B_AUX_CTL_E32B);\r
- ASSERT (IoRead8 (SmBusBase + R_AUX_CTL) & B_AUX_CTL_E32B);\r
- for (Index = 0; InBuffer != NULL && Index < BytesCount; Index++) {\r
- IoWrite8 (SmBusBase + R_HOST_BLOCK_DB, ((UINT8*)InBuffer)[Index]);\r
+ InternalSmBusIoWrite8 (SMBUS_R_XMIT_SLVA, (UINT8) SmBusAddress);\r
+ //\r
+ // Start the SMBUS transaction and wait for the end.\r
+ //\r
+ ReturnStatus = InternalSmBusStart (HostControl);\r
+ if (RETURN_ERROR (ReturnStatus)) {\r
+ goto Done;\r
}\r
\r
- SmBusStart (SmBusBase, SmBusProtocol, (UINT8)SmBusAddress);\r
-\r
- if (SmBusWait (SmBusBase) & B_HST_STS_ERR) {\r
- *Status = RETURN_DEVICE_ERROR;\r
- } else {\r
- *Status = RETURN_SUCCESS;\r
- BytesCount = IoRead8 (SmBusBase + R_HST_D0);\r
- for (Index = 0; OutBuffer != NULL && Index < BytesCount; Index++) {\r
- ((UINT8*)OutBuffer)[Index] = IoRead8 (SmBusBase + R_HOST_BLOCK_DB);\r
+ if (ReadBuffer != NULL) {\r
+ //\r
+ // Read the number of block from host block data byte register.\r
+ //\r
+ BytesCount = InternalSmBusIoRead8 (SMBUS_R_HST_D0);\r
+ //\r
+ // Write data block from Host Block Data Register.\r
+ //\r
+ for (Index = 0; Index < BytesCount; Index++) {\r
+ ReadBuffer[Index] = InternalSmBusIoRead8 (SMBUS_R_HOST_BLOCK_DB);\r
}\r
}\r
+ //\r
+ // Clear Host Status Register and Auxiliary Status Register.\r
+ //\r
+ InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_HSTS_ALL);\r
+ InternalSmBusIoWrite8 (SMBUS_R_AUX_STS, SMBUS_B_CRCE);\r
+\r
+Done:\r
+ if (Status != NULL) {\r
+ *Status = ReturnStatus;\r
+ }\r
\r
- SmBusCleanup (SmBusBase);\r
return BytesCount;\r
}\r
\r
+/**\r
+ Executes an SMBUS read block command.\r
+\r
+ Executes an SMBUS read block command on the SMBUS device specified by SmBusAddress.\r
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.\r
+ Bytes are read from the SMBUS and stored in Buffer.\r
+ The number of bytes read is returned, and will never return a value larger than 32-bytes.\r
+ If Status is not NULL, then the status of the executed command is returned in Status.\r
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.\r
+ SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes.\r
+ If Length in SmBusAddress is not zero, then ASSERT().\r
+ If Buffer is NULL, then ASSERT().\r
+ If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,\r
+ SMBUS Command, SMBUS Data Length, and PEC.\r
+ @param Buffer Pointer to the buffer to store the bytes read from the SMBUS.\r
+ @param Status Return status for the executed command.\r
+ This is an optional parameter and may be NULL.\r
+\r
+ @return The number of bytes read.\r
+\r
+**/\r
UINTN\r
EFIAPI\r
SmBusReadBlock (\r
- IN UINTN SmBusAddress,\r
- OUT VOID *Buffer,\r
- OUT RETURN_STATUS *Status\r
+ IN UINTN SmBusAddress,\r
+ OUT VOID *Buffer,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- ASSERT ((SmBusAddress & ~(0xfffffe | MAX_BIT)) == 0);\r
- return SmBusBlock (\r
- SmBusAddress | B_SMBUS_READ,\r
- B_SMB_CMD_BLOCK,\r
+ ASSERT (Buffer != NULL);\r
+ ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
+ ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
+\r
+ return InternalSmBusBlock (\r
+ SMBUS_V_SMB_CMD_BLOCK,\r
+ SmBusAddress | SMBUS_B_READ,\r
NULL,\r
Buffer,\r
Status\r
);\r
}\r
\r
+/**\r
+ Executes an SMBUS write block command.\r
+\r
+ Executes an SMBUS write block command on the SMBUS device specified by SmBusAddress.\r
+ The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBusAddress are required.\r
+ Bytes are written to the SMBUS from Buffer.\r
+ The number of bytes written is returned, and will never return a value larger than 32-bytes.\r
+ If Status is not NULL, then the status of the executed command is returned in Status. \r
+ If Length in SmBusAddress is zero or greater than 32, then ASSERT().\r
+ If Buffer is NULL, then ASSERT().\r
+ If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,\r
+ SMBUS Command, SMBUS Data Length, and PEC.\r
+ @param Buffer Pointer to the buffer to store the bytes read from the SMBUS.\r
+ @param Status Return status for the executed command.\r
+ This is an optional parameter and may be NULL.\r
+\r
+ @return The number of bytes written.\r
+\r
+**/\r
UINTN\r
EFIAPI\r
SmBusWriteBlock (\r
- IN UINTN SmBusAddress,\r
- OUT VOID *Buffer,\r
- OUT RETURN_STATUS *Status\r
+ IN UINTN SmBusAddress,\r
+ OUT VOID *Buffer,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- ASSERT ((SmBusAddress & ~(0xfffffe | MAX_BIT)) == 0);\r
- return SmBusBlock (\r
- SmBusAddress | B_SMBUS_WRITE,\r
- B_SMB_CMD_BLOCK,\r
+ ASSERT (Buffer != NULL);\r
+ ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) >= 1);\r
+ ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) <= 32);\r
+ ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
+\r
+ return InternalSmBusBlock (\r
+ SMBUS_V_SMB_CMD_BLOCK,\r
+ SmBusAddress | SMBUS_B_WRITE,\r
Buffer,\r
NULL,\r
Status\r
);\r
}\r
\r
+/**\r
+ Executes an SMBUS block process call command.\r
+\r
+ Executes an SMBUS block process call command on the SMBUS device specified by SmBusAddress.\r
+ The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBusAddress are required.\r
+ Bytes are written to the SMBUS from WriteBuffer. Bytes are then read from the SMBUS into ReadBuffer.\r
+ If Status is not NULL, then the status of the executed command is returned in Status.\r
+ It is the caller's responsibility to make sure ReadBuffer is large enough for the total number of bytes read.\r
+ SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes.\r
+ If Length in SmBusAddress is zero or greater than 32, then ASSERT().\r
+ If WriteBuffer is NULL, then ASSERT().\r
+ If ReadBuffer is NULL, then ASSERT().\r
+ If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,\r
+ SMBUS Command, SMBUS Data Length, and PEC.\r
+ @param WriteBuffer Pointer to the buffer of bytes to write to the SMBUS.\r
+ @param ReadBuffer Pointer to the buffer of bytes to read from the SMBUS.\r
+ @param Status Return status for the executed command.\r
+ This is an optional parameter and may be NULL.\r
+\r
+ @return The number of bytes written.\r
+\r
+**/\r
UINTN\r
EFIAPI\r
SmBusBlockProcessCall (\r
- IN UINTN SmBusAddress,\r
- IN VOID *OutBuffer,\r
- OUT VOID *InBuffer,\r
- OUT RETURN_STATUS *Status\r
+ IN UINTN SmBusAddress,\r
+ IN VOID *WriteBuffer,\r
+ OUT VOID *ReadBuffer,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- ASSERT ((SmBusAddress & ~(0xfffffe | MAX_BIT)) == 0);\r
- return SmBusBlock (\r
- SmBusAddress | B_SMBUS_WRITE,\r
- B_SMB_CMD_BLOCK_PROCESS,\r
- OutBuffer,\r
- InBuffer,\r
+ ASSERT (WriteBuffer != NULL);\r
+ ASSERT (ReadBuffer != NULL);\r
+ ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) >= 1);\r
+ ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) <= 32);\r
+ ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);\r
+\r
+ return InternalSmBusBlock (\r
+ SMBUS_V_SMB_CMD_BLOCK_PROCESS,\r
+ SmBusAddress | SMBUS_B_WRITE,\r
+ WriteBuffer,\r
+ ReadBuffer,\r
Status\r
);\r
}\r
-\r
-RETURN_STATUS\r
-EFIAPI\r
-SmBusArpAll (\r
- IN UINTN SmBusAddress\r
- );\r
-\r
-RETURN_STATUS\r
-EFIAPI\r
-SmBusArpDevice (\r
- IN UINTN SmBusAddress,\r
- IN CONST GUID *Uuid\r
- );\r
-\r
-RETURN_STATUS\r
-EFIAPI\r
-SmBusGetUuid (\r
- IN UINTN SmBusAddress,\r
- OUT GUID *Uuid\r
- );\r
projects / mirror_edk2.git / blobdiff