All assertions for I/O operations are handled in MMIO functions in the IoLib\r
Library.\r
\r
- Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
- All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
-\r
#include <PiDxe.h>\r
\r
+#include <Guid/EventGroup.h>\r
+\r
#include <Library/BaseLib.h>\r
#include <Library/PciExpressLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/DxeServicesTableLib.h>\r
#include <Library/UefiRuntimeLib.h>\r
\r
+/**\r
+ Assert the validity of a PCI address. A valid PCI address should contain 1's\r
+ only in the low 28 bits.\r
+\r
+ @param A The address to validate.\r
+\r
+**/\r
+#define ASSERT_INVALID_PCI_ADDRESS(A) \\r
+ ASSERT (((A) & ~0xfffffff) == 0)\r
+\r
///\r
/// Define table for mapping PCI Express MMIO physical addresses to virtual addresses at OS runtime\r
///\r
typedef struct {\r
- UINTN PhysicalAddress;\r
- UINTN VirtualAddress;\r
+ UINTN PhysicalAddress;\r
+ UINTN VirtualAddress;\r
} PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE;\r
\r
///\r
/// Set Virtual Address Map Event\r
///\r
-EFI_EVENT mDxeRuntimePciExpressLibVirtualNotifyEvent = NULL;\r
+EFI_EVENT mDxeRuntimePciExpressLibVirtualNotifyEvent = NULL;\r
\r
///\r
-/// Module global that contains the base physical address of the PCI Express MMIO range\r
+/// Module global that contains the base physical address and size of the PCI Express MMIO range.\r
///\r
-UINTN mDxeRuntimePciExpressLibPciExpressBaseAddress = 0;\r
+UINTN mDxeRuntimePciExpressLibPciExpressBaseAddress = 0;\r
+UINTN mDxeRuntimePciExpressLibPciExpressBaseSize = 0;\r
\r
///\r
-/// The number of PCI devices that have been registered for runtime access\r
+/// The number of PCI devices that have been registered for runtime access.\r
///\r
-UINTN mDxeRuntimePciExpressLibNumberOfRuntimeRanges = 0;\r
+UINTN mDxeRuntimePciExpressLibNumberOfRuntimeRanges = 0;\r
\r
///\r
-/// The table of PCI devices that have been registered for runtime access\r
+/// The table of PCI devices that have been registered for runtime access.\r
///\r
PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE *mDxeRuntimePciExpressLibRegistrationTable = NULL;\r
\r
///\r
-/// The table index of the most recent virtual address lookup\r
+/// The table index of the most recent virtual address lookup.\r
///\r
-UINTN mDxeRuntimePciExpressLibLastRuntimeRange = 0;\r
-\r
+UINTN mDxeRuntimePciExpressLibLastRuntimeRange = 0;\r
\r
/**\r
Convert the physical PCI Express MMIO addresses for all registered PCI devices\r
to virtual addresses.\r
\r
- @param[in] Event The Event that is being processed\r
- @param[in] Context Event Context\r
+ @param[in] Event The event that is being processed.\r
+ @param[in] Context The Event Context.\r
**/\r
VOID\r
EFIAPI\r
// virtual addresses.\r
//\r
for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {\r
- EfiConvertPointer (0, (VOID **) &(mDxeRuntimePciExpressLibRegistrationTable[Index].VirtualAddress));\r
+ EfiConvertPointer (0, (VOID **)&(mDxeRuntimePciExpressLibRegistrationTable[Index].VirtualAddress));\r
}\r
\r
//\r
// Convert table pointer that is allocated from EfiRuntimeServicesData to a virtual address.\r
//\r
- EfiConvertPointer (0, (VOID **) &mDxeRuntimePciExpressLibRegistrationTable);\r
+ EfiConvertPointer (0, (VOID **)&mDxeRuntimePciExpressLibRegistrationTable);\r
}\r
\r
/**\r
- The constructor function caches the PCI Express Base Address and creates a \r
+ The constructor function caches the PCI Express Base Address and creates a\r
Set Virtual Address Map event to convert physical address to virtual addresses.\r
- \r
+\r
@param ImageHandle The firmware allocated handle for the EFI image.\r
@param SystemTable A pointer to the EFI System Table.\r
- \r
+\r
@retval EFI_SUCCESS The constructor completed successfully.\r
@retval Other value The constructor did not complete successfully.\r
\r
//\r
// Cache the physical address of the PCI Express MMIO range into a module global variable\r
//\r
- mDxeRuntimePciExpressLibPciExpressBaseAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);\r
+ mDxeRuntimePciExpressLibPciExpressBaseAddress = (UINTN)PcdGet64 (PcdPciExpressBaseAddress);\r
+ mDxeRuntimePciExpressLibPciExpressBaseSize = (UINTN)PcdGet64 (PcdPciExpressBaseSize);\r
\r
//\r
// Register SetVirtualAddressMap () notify function\r
}\r
\r
/**\r
- The destructor function frees any allocated buffers and closes the Set Virtual \r
+ The destructor function frees any allocated buffers and closes the Set Virtual\r
Address Map event.\r
- \r
+\r
@param ImageHandle The firmware allocated handle for the EFI image.\r
@param SystemTable A pointer to the EFI System Table.\r
- \r
+\r
@retval EFI_SUCCESS The destructor completed successfully.\r
@retval Other value The destructor did not complete successfully.\r
\r
EFI_STATUS Status;\r
\r
//\r
- // If one or more PCI devices have been registered for runtime access, then \r
+ // If one or more PCI devices have been registered for runtime access, then\r
// free the registration table.\r
//\r
if (mDxeRuntimePciExpressLibRegistrationTable != NULL) {\r
\r
/**\r
Gets the base address of PCI Express.\r
- \r
+\r
This internal functions retrieves PCI Express Base Address via a PCD entry\r
PcdPciExpressBaseAddress.\r
- \r
- @return The base address of PCI Express.\r
+\r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and Register.\r
+\r
+ @retval (UINTN)-1 Invalid PCI address.\r
+ @retval other The base address of PCI Express.\r
\r
**/\r
UINTN\r
//\r
// Make sure Address is valid\r
//\r
- ASSERT (((Address) & ~0xfffffff) == 0);\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+\r
+ //\r
+ // Make sure the Address is in MMCONF address space\r
+ //\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINTN)-1;\r
+ }\r
\r
//\r
// Convert Address to a physical address in the MMIO PCI Express range\r
//\r
// See if there is a physical address match at the exact same index as the last address match\r
//\r
- if (mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibLastRuntimeRange].PhysicalAddress == (Address & 0x0ffff000)) {\r
+ if (mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibLastRuntimeRange].PhysicalAddress == (Address & (~0x00000fff))) {\r
//\r
// Convert the physical address to a virtual address and return the virtual address\r
//\r
}\r
\r
//\r
- // Search the entire table for a phyical address match\r
+ // Search the entire table for a physical address match\r
//\r
for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {\r
- if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == (Address & 0x0ffff000)) {\r
+ if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == (Address & (~0x00000fff))) {\r
//\r
// Cache the matching index value\r
//\r
//\r
// No match was found. This is a critical error at OS runtime, so ASSERT() and force a breakpoint.\r
//\r
- ASSERT (FALSE);\r
- CpuBreakpoint();\r
+ CpuBreakpoint ();\r
\r
//\r
- // Return the physical address \r
+ // Return the physical address\r
//\r
return Address;\r
}\r
\r
/**\r
- Registers a PCI device so PCI configuration registers may be accessed after \r
+ Registers a PCI device so PCI configuration registers may be accessed after\r
SetVirtualAddressMap().\r
- \r
- Registers the PCI device specified by Address so all the PCI configuration \r
- registers associated with that PCI device may be accessed after SetVirtualAddressMap() \r
+\r
+ Registers the PCI device specified by Address so all the PCI configuration\r
+ registers associated with that PCI device may be accessed after SetVirtualAddressMap()\r
is called.\r
- \r
+\r
If Address > 0x0FFFFFFF, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
- \r
+\r
@retval RETURN_SUCCESS The PCI device was registered for runtime access.\r
- @retval RETURN_UNSUPPORTED An attempt was made to call this function \r
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function\r
after ExitBootServices().\r
@retval RETURN_UNSUPPORTED The resources required to access the PCI device\r
at runtime could not be mapped.\r
//\r
// Make sure Address is valid\r
//\r
- ASSERT (((Address) & ~0xfffffff) == 0);\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+\r
+ //\r
+ // Make sure the Address is in MMCONF address space\r
+ //\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return RETURN_UNSUPPORTED;\r
+ }\r
\r
//\r
// Convert Address to a physical address in the MMIO PCI Express range\r
Address = GetPciExpressAddress (Address & 0x0ffff000);\r
\r
//\r
- // See if Address has already been registerd for runtime access\r
+ // See if Address has already been registered for runtime access\r
//\r
for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {\r
if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == Address) {\r
// Grow the size of the registration table\r
//\r
NewTable = ReallocateRuntimePool (\r
- (mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 0) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE), \r
- (mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 1) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE), \r
+ (mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 0) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE),\r
+ (mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 1) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE),\r
mDxeRuntimePciExpressLibRegistrationTable\r
);\r
if (NewTable == NULL) {\r
return RETURN_OUT_OF_RESOURCES;\r
}\r
- mDxeRuntimePciExpressLibRegistrationTable = NewTable;\r
+\r
+ mDxeRuntimePciExpressLibRegistrationTable = NewTable;\r
mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibNumberOfRuntimeRanges].PhysicalAddress = Address;\r
mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibNumberOfRuntimeRanges].VirtualAddress = Address;\r
mDxeRuntimePciExpressLibNumberOfRuntimeRanges++;\r
return RETURN_SUCCESS;\r
}\r
\r
-\r
/**\r
Reads an 8-bit PCI configuration register.\r
\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
-\r
- @return The read value from the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The read value from the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioRead8 (GetPciExpressAddress (Address));\r
}\r
\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param Value The value to write.\r
\r
- @return The value written to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioWrite8 (GetPciExpressAddress (Address), Value);\r
}\r
\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioOr8 (GetPciExpressAddress (Address), OrData);\r
}\r
\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioAnd8 (GetPciExpressAddress (Address), AndData);\r
}\r
\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the result of the AND operation.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioAndThenOr8 (\r
GetPciExpressAddress (Address),\r
AndData,\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
\r
- @param Address PCI configuration register to read.\r
+ @param Address The PCI configuration register to read.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..7.\r
\r
- @return The value of the bit field read from the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value of the bit field read from the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioBitFieldRead8 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..7.\r
- @param Value New value of the bit field.\r
+ @param Value The new value of the bit field.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioBitFieldWrite8 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..7.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioBitFieldOr8 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..7.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioBitFieldAnd8 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the result of the AND operation.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
return MmioBitFieldAndThenOr8 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
\r
- @return The read value from the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The read value from the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioRead16 (GetPciExpressAddress (Address));\r
}\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param Value The value to write.\r
\r
- @return The value written to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioWrite16 (GetPciExpressAddress (Address), Value);\r
}\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioOr16 (GetPciExpressAddress (Address), OrData);\r
}\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioAnd16 (GetPciExpressAddress (Address), AndData);\r
}\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the result of the AND operation.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioAndThenOr16 (\r
GetPciExpressAddress (Address),\r
AndData,\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
\r
- @param Address PCI configuration register to read.\r
+ @param Address The PCI configuration register to read.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..15.\r
\r
- @return The value of the bit field read from the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value of the bit field read from the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioBitFieldRead16 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..15.\r
- @param Value New value of the bit field.\r
+ @param Value The new value of the bit field.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioBitFieldWrite16 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..15.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioBitFieldOr16 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..15.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioBitFieldAnd16 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the result of the AND operation.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
return MmioBitFieldAndThenOr16 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
\r
- @return The read value from the PCI configuration register.\r
+ @retval 0xFFFF Invalid PCI address.\r
+ @retval other The read value from the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioRead32 (GetPciExpressAddress (Address));\r
}\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param Value The value to write.\r
\r
- @return The value written to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioWrite32 (GetPciExpressAddress (Address), Value);\r
}\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioOr32 (GetPciExpressAddress (Address), OrData);\r
}\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioAnd32 (GetPciExpressAddress (Address), AndData);\r
}\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the result of the AND operation.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioAndThenOr32 (\r
GetPciExpressAddress (Address),\r
AndData,\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
\r
- @param Address PCI configuration register to read.\r
+ @param Address The PCI configuration register to read.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..31.\r
\r
- @return The value of the bit field read from the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value of the bit field read from the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioBitFieldRead32 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..31.\r
- @param Value New value of the bit field.\r
+ @param Value The new value of the bit field.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioBitFieldWrite32 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..31.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioBitFieldOr32 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
Range 0..31.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioBitFieldAnd32 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
@param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the result of the AND operation.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
+ if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
return MmioBitFieldAndThenOr32 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
Size into the buffer specified by Buffer. This function only allows the PCI\r
configuration registers from a single PCI function to be read. Size is\r
returned. When possible 32-bit PCI configuration read cycles are used to read\r
- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
+ from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
and 16-bit PCI configuration read cycles may be used at the beginning and the\r
end of the range.\r
\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
- @param StartAddress Starting address that encodes the PCI Bus, Device,\r
+ @param StartAddress The starting address that encodes the PCI Bus, Device,\r
Function and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer receiving the data read.\r
+ @param Size The size in bytes of the transfer.\r
+ @param Buffer The pointer to a buffer receiving the data read.\r
\r
- @return Size read data from StartAddress.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other Size read data from StartAddress.\r
\r
**/\r
UINTN\r
EFIAPI\r
PciExpressReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
+ //\r
+ // Make sure Address is valid\r
+ //\r
+ ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
+ //\r
+ // Make sure the Address is in MMCONF address space\r
+ //\r
+ if (StartAddress >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINTN)-1;\r
+ }\r
+\r
if (Size == 0) {\r
return Size;\r
}\r
// Read a byte if StartAddress is byte aligned\r
//\r
*(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));\r
\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
// Read as many double words as possible\r
//\r
- WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));\r
+ WriteUnaligned32 ((UINT32 *)Buffer, (UINT32)PciExpressRead32 (StartAddress));\r
\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
// Read the last remaining word if exist\r
//\r
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
Size from the buffer specified by Buffer. This function only allows the PCI\r
configuration registers from a single PCI function to be written. Size is\r
returned. When possible 32-bit PCI configuration write cycles are used to\r
- write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
+ write from StartAddress to StartAddress + Size. Due to alignment restrictions,\r
8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
and the end of the range.\r
\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
- @param StartAddress Starting address that encodes the PCI Bus, Device,\r
+ @param StartAddress The starting address that encodes the PCI Bus, Device,\r
Function and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer containing the data to write.\r
+ @param Size The size in bytes of the transfer.\r
+ @param Buffer The pointer to a buffer containing the data to write.\r
\r
- @return Size written to StartAddress.\r
+ @retval 0xFFFFFFFF Invalid PCI address.\r
+ @retval other Size written to StartAddress.\r
\r
**/\r
UINTN\r
EFIAPI\r
PciExpressWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
+ //\r
+ // Make sure Address is valid\r
+ //\r
+ ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
+ //\r
+ // Make sure the Address is in MMCONF address space\r
+ //\r
+ if (StartAddress >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
+ return (UINTN)-1;\r
+ }\r
+\r
if (Size == 0) {\r
return 0;\r
}\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);\r
StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
// Write as many double words as possible\r
//\r
- PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r
+ PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32 *)Buffer));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
// Write the last remaining word if exist\r
//\r
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
//\r
// Write the last remaining byte if exist\r
//\r
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);\r
}\r
\r
return ReturnValue;\r
projects / mirror_edk2.git / blobdiff