--- /dev/null
+/** @file\r
+ Unit Test Host BaseLib hooks.\r
+\r
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef __UNIT_TEST_HOST_BASE_LIB_H__\r
+#define __UNIT_TEST_HOST_BASE_LIB_H__\r
+\r
+/**\r
+ Prototype of service with no parameters and no return value.\r
+**/\r
+typedef\r
+VOID\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_VOID)(\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Prototype of service that reads and returns a BOOLEAN value.\r
+\r
+ @return The value read.\r
+**/\r
+typedef\r
+BOOLEAN\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_READ_BOOLEAN)(\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Prototype of service that reads and returns a UINT16 value.\r
+\r
+ @return The value read.\r
+**/\r
+typedef\r
+UINT16\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_READ_UINT16)(\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Prototype of service that reads and returns a UINTN value.\r
+\r
+ @return The value read.\r
+**/\r
+typedef\r
+UINTN\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_READ_UINTN)(\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Prototype of service that writes and returns a UINT16 value.\r
+\r
+ @param[in] Value The value to write.\r
+\r
+ @return The value written.\r
+**/\r
+typedef\r
+VOID\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16)(\r
+ IN UINT16 Value\r
+ );\r
+\r
+/**\r
+ Prototype of service that writes and returns a UINTN value.\r
+\r
+ @param[in] Value The value to write.\r
+\r
+ @return The value written.\r
+**/\r
+typedef\r
+UINTN\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN)(\r
+ IN UINTN Value\r
+ );\r
+\r
+/**\r
+ Prototype of service that reads and returns an IA32_DESCRIPTOR.\r
+\r
+ @param[out] Ia32Descriptor Pointer to the descriptor read.\r
+**/\r
+typedef\r
+VOID\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR)(\r
+ OUT IA32_DESCRIPTOR *Ia32Descriptor\r
+ );\r
+\r
+/**\r
+ Prototype of service that writes an IA32_DESCRIPTOR.\r
+\r
+ @param[in] Ia32Descriptor Pointer to the descriptor to write.\r
+**/\r
+typedef\r
+VOID\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR)(\r
+ IN CONST IA32_DESCRIPTOR *Ia32Descriptor\r
+ );\r
+\r
+/**\r
+ Retrieves CPUID information.\r
+\r
+ Executes the CPUID instruction with EAX set to the value specified by Index.\r
+ This function always returns Index.\r
+ If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.\r
+ If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.\r
+ If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.\r
+ If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.\r
+ This function is only available on IA-32 and x64.\r
+\r
+ @param Index The 32-bit value to load into EAX prior to invoking the CPUID\r
+ instruction.\r
+ @param Eax The pointer to the 32-bit EAX value returned by the CPUID\r
+ instruction. This is an optional parameter that may be NULL.\r
+ @param Ebx The pointer to the 32-bit EBX value returned by the CPUID\r
+ instruction. This is an optional parameter that may be NULL.\r
+ @param Ecx The pointer to the 32-bit ECX value returned by the CPUID\r
+ instruction. This is an optional parameter that may be NULL.\r
+ @param Edx The pointer to the 32-bit EDX value returned by the CPUID\r
+ instruction. This is an optional parameter that may be NULL.\r
+\r
+ @return Index.\r
+\r
+**/\r
+typedef\r
+UINT32\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_CPUID)(\r
+ IN UINT32 Index,\r
+ OUT UINT32 *Eax, OPTIONAL\r
+ OUT UINT32 *Ebx, OPTIONAL\r
+ OUT UINT32 *Ecx, OPTIONAL\r
+ OUT UINT32 *Edx OPTIONAL\r
+ );\r
+\r
+/**\r
+ Retrieves CPUID information using an extended leaf identifier.\r
+\r
+ Executes the CPUID instruction with EAX set to the value specified by Index\r
+ and ECX set to the value specified by SubIndex. This function always returns\r
+ Index. This function is only available on IA-32 and x64.\r
+\r
+ If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.\r
+ If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.\r
+ If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.\r
+ If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.\r
+\r
+ @param Index The 32-bit value to load into EAX prior to invoking the\r
+ CPUID instruction.\r
+ @param SubIndex The 32-bit value to load into ECX prior to invoking the\r
+ CPUID instruction.\r
+ @param Eax The pointer to the 32-bit EAX value returned by the CPUID\r
+ instruction. This is an optional parameter that may be\r
+ NULL.\r
+ @param Ebx The pointer to the 32-bit EBX value returned by the CPUID\r
+ instruction. This is an optional parameter that may be\r
+ NULL.\r
+ @param Ecx The pointer to the 32-bit ECX value returned by the CPUID\r
+ instruction. This is an optional parameter that may be\r
+ NULL.\r
+ @param Edx The pointer to the 32-bit EDX value returned by the CPUID\r
+ instruction. This is an optional parameter that may be\r
+ NULL.\r
+\r
+ @return Index.\r
+\r
+**/\r
+typedef\r
+UINT32\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_CPUID_EX)(\r
+ IN UINT32 Index,\r
+ IN UINT32 SubIndex,\r
+ OUT UINT32 *Eax, OPTIONAL\r
+ OUT UINT32 *Ebx, OPTIONAL\r
+ OUT UINT32 *Ecx, OPTIONAL\r
+ OUT UINT32 *Edx OPTIONAL\r
+ );\r
+\r
+/**\r
+ Returns a 64-bit Machine Specific Register(MSR).\r
+\r
+ Reads and returns the 64-bit MSR specified by Index. No parameter checking is\r
+ performed on Index, and some Index values may cause CPU exceptions. The\r
+ caller must either guarantee that Index is valid, or the caller must set up\r
+ exception handlers to catch the exceptions. This function is only available\r
+ on IA-32 and x64.\r
+\r
+ @param Index The 32-bit MSR index to read.\r
+\r
+ @return The value of the MSR identified by Index.\r
+\r
+**/\r
+typedef\r
+UINT64\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_READ_MSR_64)(\r
+ IN UINT32 Index\r
+ );\r
+\r
+/**\r
+ Writes a 64-bit value to a Machine Specific Register(MSR), and returns the\r
+ value.\r
+\r
+ Writes the 64-bit value specified by Value to the MSR specified by Index. The\r
+ 64-bit value written to the MSR is returned. No parameter checking is\r
+ performed on Index or Value, and some of these may cause CPU exceptions. The\r
+ caller must either guarantee that Index and Value are valid, or the caller\r
+ must establish proper exception handlers. This function is only available on\r
+ IA-32 and x64.\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param Value The 64-bit value to write to the MSR.\r
+\r
+ @return Value\r
+\r
+**/\r
+typedef\r
+UINT64\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_MSR_64)(\r
+ IN UINT32 Index,\r
+ IN UINT64 Value\r
+ );\r
+\r
+/**\r
+ Reads the current value of a Performance Counter (PMC).\r
+\r
+ Reads and returns the current value of performance counter specified by\r
+ Index. This function is only available on IA-32 and x64.\r
+\r
+ @param Index The 32-bit Performance Counter index to read.\r
+\r
+ @return The value of the PMC specified by Index.\r
+\r
+**/\r
+typedef\r
+UINT64\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_READ_PMC)(\r
+ IN UINT32 Index\r
+ );\r
+\r
+/**\r
+ Sets up a monitor buffer that is used by AsmMwait().\r
+\r
+ Executes a MONITOR instruction with the register state specified by Eax, Ecx\r
+ and Edx. Returns Eax. This function is only available on IA-32 and x64.\r
+\r
+ @param Eax The value to load into EAX or RAX before executing the MONITOR\r
+ instruction.\r
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR\r
+ instruction.\r
+ @param Edx The value to load into EDX or RDX before executing the MONITOR\r
+ instruction.\r
+\r
+ @return Eax\r
+\r
+**/\r
+typedef\r
+UINTN\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_MONITOR)(\r
+ IN UINTN Eax,\r
+ IN UINTN Ecx,\r
+ IN UINTN Edx\r
+ );\r
+\r
+/**\r
+ Executes an MWAIT instruction.\r
+\r
+ Executes an MWAIT instruction with the register state specified by Eax and\r
+ Ecx. Returns Eax. This function is only available on IA-32 and x64.\r
+\r
+ @param Eax The value to load into EAX or RAX before executing the MONITOR\r
+ instruction.\r
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR\r
+ instruction.\r
+\r
+ @return Eax\r
+\r
+**/\r
+typedef\r
+UINTN\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_MWAIT)(\r
+ IN UINTN Eax,\r
+ IN UINTN Ecx\r
+ );\r
+\r
+/**\r
+ Flushes a cache line from all the instruction and data caches within the\r
+ coherency domain of the CPU.\r
+\r
+ Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r
+ This function is only available on IA-32 and x64.\r
+\r
+ @param LinearAddress The address of the cache line to flush. If the CPU is\r
+ in a physical addressing mode, then LinearAddress is a\r
+ physical address. If the CPU is in a virtual\r
+ addressing mode, then LinearAddress is a virtual\r
+ address.\r
+\r
+ @return LinearAddress.\r
+**/\r
+typedef\r
+VOID *\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_FLUSH_CACHE_LINE)(\r
+ IN VOID *LinearAddress\r
+ );\r
+\r
+/**\r
+ Prototype of service that enables ot disables 32-bit paging modes.\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack after\r
+ paging is enabled.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function as the first parameter after paging is enabled.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function as the second parameter after paging is enabled.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function after paging is enabled.\r
+\r
+**/\r
+typedef\r
+VOID\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32)(\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *NewStack\r
+ );\r
+\r
+/**\r
+ Enables the 64-bit paging mode on the CPU.\r
+\r
+ Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r
+ must be properly initialized prior to calling this service. This function\r
+ assumes the current execution mode is 32-bit protected mode with flat\r
+ descriptors. This function is only available on IA-32. After the 64-bit\r
+ paging mode is enabled, control is transferred to the function specified by\r
+ EntryPoint using the new stack specified by NewStack and passing in the\r
+ parameters specified by Context1 and Context2. Context1 and Context2 are\r
+ optional and may be 0. The function EntryPoint must never return.\r
+\r
+ If the current execution mode is not 32-bit protected mode with flat\r
+ descriptors, then ASSERT().\r
+ If EntryPoint is 0, then ASSERT().\r
+ If NewStack is 0, then ASSERT().\r
+\r
+ @param Cs The 16-bit selector to load in the CS before EntryPoint\r
+ is called. The descriptor in the GDT that this selector\r
+ references must be setup for long mode.\r
+ @param EntryPoint The 64-bit virtual address of the function to call with\r
+ the new stack after paging is enabled.\r
+ @param Context1 The 64-bit virtual address of the context to pass into\r
+ the EntryPoint function as the first parameter after\r
+ paging is enabled.\r
+ @param Context2 The 64-bit virtual address of the context to pass into\r
+ the EntryPoint function as the second parameter after\r
+ paging is enabled.\r
+ @param NewStack The 64-bit virtual address of the new stack to use for\r
+ the EntryPoint function after paging is enabled.\r
+\r
+**/\r
+typedef\r
+VOID\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_ENABLE_PAGING_64)(\r
+ IN UINT16 Cs,\r
+ IN UINT64 EntryPoint,\r
+ IN UINT64 Context1, OPTIONAL\r
+ IN UINT64 Context2, OPTIONAL\r
+ IN UINT64 NewStack\r
+ );\r
+\r
+/**\r
+ Disables the 64-bit paging mode on the CPU.\r
+\r
+ Disables the 64-bit paging mode on the CPU and returns to 32-bit protected\r
+ mode. This function assumes the current execution mode is 64-paging mode.\r
+ This function is only available on x64. After the 64-bit paging mode is\r
+ disabled, control is transferred to the function specified by EntryPoint\r
+ using the new stack specified by NewStack and passing in the parameters\r
+ specified by Context1 and Context2. Context1 and Context2 are optional and\r
+ may be 0. The function EntryPoint must never return.\r
+\r
+ If the current execution mode is not 64-bit paged mode, then ASSERT().\r
+ If EntryPoint is 0, then ASSERT().\r
+ If NewStack is 0, then ASSERT().\r
+\r
+ @param Cs The 16-bit selector to load in the CS before EntryPoint\r
+ is called. The descriptor in the GDT that this selector\r
+ references must be setup for 32-bit protected mode.\r
+ @param EntryPoint The 64-bit virtual address of the function to call with\r
+ the new stack after paging is disabled.\r
+ @param Context1 The 64-bit virtual address of the context to pass into\r
+ the EntryPoint function as the first parameter after\r
+ paging is disabled.\r
+ @param Context2 The 64-bit virtual address of the context to pass into\r
+ the EntryPoint function as the second parameter after\r
+ paging is disabled.\r
+ @param NewStack The 64-bit virtual address of the new stack to use for\r
+ the EntryPoint function after paging is disabled.\r
+\r
+**/\r
+typedef\r
+VOID\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_DISABLE_PAGING_64)(\r
+ IN UINT16 Cs,\r
+ IN UINT32 EntryPoint,\r
+ IN UINT32 Context1, OPTIONAL\r
+ IN UINT32 Context2, OPTIONAL\r
+ IN UINT32 NewStack\r
+ );\r
+\r
+/**\r
+ Retrieves the properties for 16-bit thunk functions.\r
+\r
+ Computes the size of the buffer and stack below 1MB required to use the\r
+ AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This\r
+ buffer size is returned in RealModeBufferSize, and the stack size is returned\r
+ in ExtraStackSize. If parameters are passed to the 16-bit real mode code,\r
+ then the actual minimum stack size is ExtraStackSize plus the maximum number\r
+ of bytes that need to be passed to the 16-bit real mode code.\r
+\r
+ If RealModeBufferSize is NULL, then ASSERT().\r
+ If ExtraStackSize is NULL, then ASSERT().\r
+\r
+ @param RealModeBufferSize A pointer to the size of the buffer below 1MB\r
+ required to use the 16-bit thunk functions.\r
+ @param ExtraStackSize A pointer to the extra size of stack below 1MB\r
+ that the 16-bit thunk functions require for\r
+ temporary storage in the transition to and from\r
+ 16-bit real mode.\r
+\r
+**/\r
+typedef\r
+VOID\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_GET_THUNK_16_PROPERTIES)(\r
+ OUT UINT32 *RealModeBufferSize,\r
+ OUT UINT32 *ExtraStackSize\r
+ );\r
+\r
+/**\r
+ Prototype of services that operates on a THUNK_CONTEXT structure.\r
+\r
+ @param ThunkContext A pointer to the context structure that describes the\r
+ 16-bit real mode code to call.\r
+\r
+**/\r
+typedef\r
+VOID\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16)(\r
+ IN OUT THUNK_CONTEXT *ThunkContext\r
+ );\r
+\r
+/**\r
+ Patch the immediate operand of an IA32 or X64 instruction such that the byte,\r
+ word, dword or qword operand is encoded at the end of the instruction's\r
+ binary representation.\r
+\r
+ This function should be used to update object code that was compiled with\r
+ NASM from assembly source code. Example:\r
+\r
+ NASM source code:\r
+\r
+ mov eax, strict dword 0 ; the imm32 zero operand will be patched\r
+ ASM_PFX(gPatchCr3):\r
+ mov cr3, eax\r
+\r
+ C source code:\r
+\r
+ X86_ASSEMBLY_PATCH_LABEL gPatchCr3;\r
+ PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);\r
+\r
+ @param[out] InstructionEnd Pointer right past the instruction to patch. The\r
+ immediate operand to patch is expected to\r
+ comprise the trailing bytes of the instruction.\r
+ If InstructionEnd is closer to address 0 than\r
+ ValueSize permits, then ASSERT().\r
+\r
+ @param[in] PatchValue The constant to write to the immediate operand.\r
+ The caller is responsible for ensuring that\r
+ PatchValue can be represented in the byte, word,\r
+ dword or qword operand (as indicated through\r
+ ValueSize); otherwise ASSERT().\r
+\r
+ @param[in] ValueSize The size of the operand in bytes; must be 1, 2,\r
+ 4, or 8. ASSERT() otherwise.\r
+**/\r
+typedef\r
+VOID\r
+(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_PATCH_INSTRUCTION_X86)(\r
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r
+ IN UINT64 PatchValue,\r
+ IN UINTN ValueSize\r
+ );\r
+\r
+///\r
+/// Common services\r
+///\r
+typedef struct {\r
+ UNIT_TEST_HOST_BASE_LIB_VOID EnableInterrupts;\r
+ UNIT_TEST_HOST_BASE_LIB_VOID DisableInterrupts;\r
+ UNIT_TEST_HOST_BASE_LIB_VOID EnableDisableInterrupts;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_BOOLEAN GetInterruptState;\r
+} UNIT_TEST_HOST_BASE_LIB_COMMON;\r
+\r
+///\r
+/// IA32/X64 services\r
+///\r
+typedef struct {\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_CPUID AsmCpuid;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_CPUID_EX AsmCpuidEx;\r
+ UNIT_TEST_HOST_BASE_LIB_VOID AsmDisableCache;\r
+ UNIT_TEST_HOST_BASE_LIB_VOID AsmEnableCache;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_READ_MSR_64 AsmReadMsr64;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_MSR_64 AsmWriteMsr64;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr0;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr2;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr3;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr4;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr0;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr2;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr3;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr4;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr0;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr1;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr2;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr3;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr4;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr5;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr6;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr7;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr0;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr1;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr2;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr3;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr4;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr5;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr6;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr7;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadCs;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadDs;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadEs;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadFs;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadGs;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadSs;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadTr;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR AsmReadGdtr;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR AsmWriteGdtr;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR AsmReadIdtr;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR AsmWriteIdtr;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadLdtr;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16 AsmWriteLdtr;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_READ_PMC AsmReadPmc;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_MONITOR AsmMonitor;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_MWAIT AsmMwait;\r
+ UNIT_TEST_HOST_BASE_LIB_VOID AsmWbinvd;\r
+ UNIT_TEST_HOST_BASE_LIB_VOID AsmInvd;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_FLUSH_CACHE_LINE AsmFlushCacheLine;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32 AsmEnablePaging32;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32 AsmDisablePaging32;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_ENABLE_PAGING_64 AsmEnablePaging64;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_DISABLE_PAGING_64 AsmDisablePaging64;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_GET_THUNK_16_PROPERTIES AsmGetThunk16Properties;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmPrepareThunk16;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmThunk16;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmPrepareAndThunk16;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16 AsmWriteTr;\r
+ UNIT_TEST_HOST_BASE_LIB_VOID AsmLfence;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_PATCH_INSTRUCTION_X86 PatchInstructionX86;\r
+} UNIT_TEST_HOST_BASE_LIB_X86;\r
+\r
+///\r
+/// Data structure that contains pointers structures of common services and CPU\r
+/// architctuire specific services. Support for additional CPU architectures\r
+/// can be added to the end of this structure.\r
+///\r
+typedef struct {\r
+ UNIT_TEST_HOST_BASE_LIB_COMMON *Common;\r
+ UNIT_TEST_HOST_BASE_LIB_X86 *X86;\r
+} UNIT_TEST_HOST_BASE_LIB;\r
+\r
+extern UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib;\r
+\r
+#endif\r
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