+++ /dev/null
-/** @file\r
- Functions accessing PCI configuration registers on any supported PCI segment\r
-\r
- Copyright (c) 2006, Intel Corporation\r
- All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
- Module Name: PciSegmentLib.h\r
-\r
-**/\r
-\r
-#ifndef __PCI_SEGMENT_LIB__\r
-#define __PCI_SEGMENT_LIB__\r
-\r
-\r
-/**\r
- Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r
- and PCI Register to an address that can be passed to the PCI Segment Library functions.\r
-\r
- Computes an address that is compatible with the PCI Segment Library functions.\r
- The unused upper bits of Segment, Bus, Device, Function,\r
- and Register are stripped prior to the generation of the address.\r
-\r
- @param Segment PCI Segment number. Range 0..65535.\r
- @param Bus PCI Bus number. Range 0..255.\r
- @param Device PCI Device number. Range 0..31.\r
- @param Function PCI Function number. Range 0..7.\r
- @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.\r
-\r
- @return The address that is compatible with the PCI Segment Library functions.\r
-\r
-**/\r
-#define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r
- ( ((Register) & 0xfff) | \\r
- (((Function) & 0x07) << 12) | \\r
- (((Device) & 0x1f) << 15) | \\r
- (((Bus) & 0xff) << 20) | \\r
- (LShiftU64((Segment) & 0xffff, 32)) \\r
- )\r
-\r
-/**\r
- Reads an 8-bit PCI configuration register.\r
-\r
- Reads and returns the 8-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- If any reserved bits in Address are set, then ASSERT().\r
- \r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
-\r
- @return The 8-bit PCI configuration register specified by Address.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentRead8 (\r
- IN UINT64 Address\r
- )\r
-;\r
-\r
-/**\r
- Writes an 8-bit PCI configuration register.\r
-\r
- Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
- Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Value The value to write.\r
-\r
- @return The parameter of Value.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentWrite8 (\r
- IN UINT64 Address,\r
- IN UINT8 Value\r
- )\r
-;\r
-\r
-/**\r
- Performs a bitwise inclusive OR of an 8-bit PCI configuration register with an 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
- and writes the result to the 8-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 OrData\r
- )\r
-;\r
-\r
-/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address,\r
- performs a bitwise AND between the read result and the value specified by AndData,\r
- and writes the result to the 8-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentAnd8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData\r
- )\r
-;\r
-\r
-/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r
- followed a bitwise inclusive OR with another 8-bit value.\r
- \r
- Reads the 8-bit PCI configuration register specified by Address,\r
- performs a bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r
- and writes the result to the 8-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-;\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in an 8-bit PCI configuration register.\r
- The bit field is specified by the StartBit and the EndBit.\r
- The value of the bit field is returned.\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
-\r
- @return The value of the bit field.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentBitFieldRead8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-;\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register.\r
- The bit field is specified by the StartBit and the EndBit.\r
- All other bits in the destination PCI configuration register are preserved.\r
- The new value of the 8-bit register is returned.\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param Value New value of the bit field.\r
-\r
- @return The new value of the 8-bit register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentBitFieldWrite8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
- )\r
-;\r
-\r
-/**\r
- Reads the 8-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
- and writes the result to the 8-bit PCI configuration register specified by Address. \r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param OrData The value to OR with the read value from the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentBitFieldOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
- )\r
-;\r
-\r
-/**\r
- Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR,\r
- and writes the result back to the bit field in the 8-bit port.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
- and writes the result to the 8-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- Extra left bits in OrData are stripped.\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param AndData The value to AND with the read value from the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentBitFieldAnd8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
- )\r
-;\r
-\r
-/**\r
- Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND,\r
- and writes the result back to the bit field in the 8-bit register.\r
- \r
- Reads the 8-bit PCI configuration register specified by Address,\r
- performs a bitwise AND between the read result and the value specified by AndData,\r
- and writes the result to the 8-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- Extra left bits in AndData are stripped.\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param AndData The value to AND with the read value from the PCI configuration register.\r
- @param OrData The value to OR with the read value from the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentBitFieldAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-;\r
-\r
-/**\r
- Reads a 16-bit PCI configuration register.\r
-\r
- Reads and returns the 16-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- If any reserved bits in Address are set, then ASSERT().\r
- \r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
-\r
- @return The 16-bit PCI configuration register specified by Address.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentRead16 (\r
- IN UINT64 Address\r
- )\r
-;\r
-\r
-/**\r
- Writes a 16-bit PCI configuration register.\r
-\r
- Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r
- Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Value The value to write.\r
-\r
- @return The parameter of Value.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentWrite16 (\r
- IN UINT64 Address,\r
- IN UINT16 Value\r
- )\r
-;\r
-\r
-/**\r
- Performs a bitwise inclusive OR of a 16-bit PCI configuration register with a 16-bit value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
- and writes the result to the 16-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 OrData\r
- )\r
-;\r
-\r
-/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise AND between the read result and the value specified by AndData,\r
- and writes the result to the 16-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentAnd16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData\r
- )\r
-;\r
-\r
-/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r
- followed a bitwise inclusive OR with another 16-bit value.\r
- \r
- Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r
- and writes the result to the 16-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-;\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in a 16-bit PCI configuration register.\r
- The bit field is specified by the StartBit and the EndBit.\r
- The value of the bit field is returned.\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
-\r
- @return The value of the bit field.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentBitFieldRead16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-;\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register.\r
- The bit field is specified by the StartBit and the EndBit.\r
- All other bits in the destination PCI configuration register are preserved.\r
- The new value of the 16-bit register is returned.\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param Value New value of the bit field.\r
-\r
- @return The new value of the 16-bit register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentBitFieldWrite16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
- )\r
-;\r
-\r
-/**\r
- Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
- and writes the result to the 16-bit PCI configuration register specified by Address. \r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param OrData The value to OR with the read value from the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentBitFieldOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
- )\r
-;\r
-\r
-/**\r
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,\r
- and writes the result back to the bit field in the 16-bit port.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
- and writes the result to the 16-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- Extra left bits in OrData are stripped.\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param AndData The value to AND with the read value from the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentBitFieldAnd16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
- )\r
-;\r
-\r
-/**\r
- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND,\r
- and writes the result back to the bit field in the 16-bit register.\r
- \r
- Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise AND between the read result and the value specified by AndData,\r
- and writes the result to the 16-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- Extra left bits in AndData are stripped.\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param AndData The value to AND with the read value from the PCI configuration register.\r
- @param OrData The value to OR with the read value from the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentBitFieldAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-;\r
-\r
-/**\r
- Reads a 32-bit PCI configuration register.\r
-\r
- Reads and returns the 32-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- If any reserved bits in Address are set, then ASSERT().\r
- \r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
-\r
- @return The 32-bit PCI configuration register specified by Address.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentRead32 (\r
- IN UINT64 Address\r
- )\r
-;\r
-\r
-/**\r
- Writes a 32-bit PCI configuration register.\r
-\r
- Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r
- Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Value The value to write.\r
-\r
- @return The parameter of Value.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentWrite32 (\r
- IN UINT64 Address,\r
- IN UINT32 Value\r
- )\r
-;\r
-\r
-/**\r
- Performs a bitwise inclusive OR of a 32-bit PCI configuration register with a 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
- and writes the result to the 32-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 OrData\r
- )\r
-;\r
-\r
-/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address,\r
- performs a bitwise AND between the read result and the value specified by AndData,\r
- and writes the result to the 32-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentAnd32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData\r
- )\r
-;\r
-\r
-/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r
- followed a bitwise inclusive OR with another 32-bit value.\r
- \r
- Reads the 32-bit PCI configuration register specified by Address,\r
- performs a bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r
- and writes the result to the 32-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-;\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in a 32-bit PCI configuration register.\r
- The bit field is specified by the StartBit and the EndBit.\r
- The value of the bit field is returned.\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
-\r
- @return The value of the bit field.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentBitFieldRead32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-;\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register.\r
- The bit field is specified by the StartBit and the EndBit.\r
- All other bits in the destination PCI configuration register are preserved.\r
- The new value of the 32-bit register is returned.\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param Value New value of the bit field.\r
-\r
- @return The new value of the 32-bit register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentBitFieldWrite32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
- )\r
-;\r
-\r
-/**\r
- Reads the 32-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
- and writes the result to the 32-bit PCI configuration register specified by Address. \r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param OrData The value to OR with the read value from the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentBitFieldOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
- )\r
-;\r
-\r
-/**\r
- Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR,\r
- and writes the result back to the bit field in the 32-bit port.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
- and writes the result to the 32-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- Extra left bits in OrData are stripped.\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param AndData The value to AND with the read value from the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentBitFieldAnd32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
- )\r
-;\r
-\r
-/**\r
- Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND,\r
- and writes the result back to the bit field in the 32-bit register.\r
- \r
- Reads the 32-bit PCI configuration register specified by Address,\r
- performs a bitwise AND between the read result and the value specified by AndData,\r
- and writes the result to the 32-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- Extra left bits in AndData are stripped.\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param AndData The value to AND with the read value from the PCI configuration register.\r
- @param OrData The value to OR with the read value from the PCI configuration register.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentBitFieldAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-;\r
-\r
-/**\r
- Reads a range of PCI configuration registers into a caller supplied buffer.\r
-\r
- Reads the range of PCI configuration registers specified by StartAddress\r
- and Size into the buffer specified by Buffer.\r
- This function only allows the PCI configuration registers from a single PCI function to be read.\r
- Size is returned.\r
- If any reserved bits in StartAddress are set, then ASSERT().\r
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
- If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r
- If Buffer is NULL, then ASSERT().\r
-\r
- @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer receiving the data read.\r
-\r
- @return The paramter of Size.\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PciSegmentReadBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
- )\r
-;\r
-\r
-/**\r
- Copies the data in a caller supplied buffer to a specified range of PCI configuration space.\r
-\r
- Writes the range of PCI configuration registers specified by StartAddress\r
- and Size from the buffer specified by Buffer.\r
- This function only allows the PCI configuration registers from a single PCI function to be written.\r
- Size is returned.\r
- If any reserved bits in StartAddress are set, then ASSERT().\r
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
- If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r
- If Buffer is NULL, then ASSERT().\r
-\r
- @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer containing the data to write.\r
-\r
- @return The paramter of Size.\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PciSegmentWriteBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
- )\r
-;\r
-\r
-#endif\r
projects / mirror_edk2.git / blobdiff