--- /dev/null
+/** @file\r
+ DebugSupport protocol and supporting definitions as defined in the UEFI2.0\r
+ specification.\r
+\r
+ The DebugSupport protocol is used by source level debuggers to abstract the\r
+ processor and handle context save and restore operations.\r
+\r
+ Copyright (c) 2006, Intel Corporation \r
+ All rights reserved. This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ Module Name: DebugSupport.h\r
+\r
+**/\r
+\r
+#ifndef __DEBUG_SUPPORT_H__\r
+#define __DEBUG_SUPPORT_H__\r
+\r
+typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;\r
+\r
+//\r
+// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}\r
+//\r
+#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \\r
+ { \\r
+ 0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \\r
+ }\r
+\r
+//\r
+// Debug Support definitions\r
+//\r
+typedef INTN EFI_EXCEPTION_TYPE;\r
+\r
+//\r
+// IA-32 processor exception types\r
+//\r
+#define EXCEPT_IA32_DIVIDE_ERROR 0\r
+#define EXCEPT_IA32_DEBUG 1\r
+#define EXCEPT_IA32_NMI 2\r
+#define EXCEPT_IA32_BREAKPOINT 3\r
+#define EXCEPT_IA32_OVERFLOW 4\r
+#define EXCEPT_IA32_BOUND 5\r
+#define EXCEPT_IA32_INVALID_OPCODE 6\r
+#define EXCEPT_IA32_DOUBLE_FAULT 8\r
+#define EXCEPT_IA32_INVALID_TSS 10\r
+#define EXCEPT_IA32_SEG_NOT_PRESENT 11\r
+#define EXCEPT_IA32_STACK_FAULT 12\r
+#define EXCEPT_IA32_GP_FAULT 13\r
+#define EXCEPT_IA32_PAGE_FAULT 14\r
+#define EXCEPT_IA32_FP_ERROR 16\r
+#define EXCEPT_IA32_ALIGNMENT_CHECK 17\r
+#define EXCEPT_IA32_MACHINE_CHECK 18\r
+#define EXCEPT_IA32_SIMD 19\r
+\r
+//\r
+// IA-32 processor context definition\r
+//\r
+//\r
+// FXSAVE_STATE\r
+// FP / MMX / XMM registers (see fxrstor instruction definition)\r
+//\r
+typedef struct {\r
+ UINT16 Fcw;\r
+ UINT16 Fsw;\r
+ UINT16 Ftw;\r
+ UINT16 Opcode;\r
+ UINT32 Eip;\r
+ UINT16 Cs;\r
+ UINT16 Reserved1;\r
+ UINT32 DataOffset;\r
+ UINT16 Ds;\r
+ UINT8 Reserved2[10];\r
+#if (EFI_SPECIFICATION_VERSION >= 0x00020000)\r
+ UINT8 St0Mm0[10], Reserved3[6];\r
+ UINT8 St1Mm1[10], Reserved4[6];\r
+ UINT8 St2Mm2[10], Reserved5[6];\r
+ UINT8 St3Mm3[10], Reserved6[6];\r
+ UINT8 St4Mm4[10], Reserved7[6];\r
+ UINT8 St5Mm5[10], Reserved8[6];\r
+ UINT8 St6Mm6[10], Reserved9[6];\r
+ UINT8 St7Mm7[10], Reserved10[6];\r
+ UINT8 Xmm0[16];\r
+ UINT8 Xmm1[16];\r
+ UINT8 Xmm2[16];\r
+ UINT8 Xmm3[16];\r
+ UINT8 Xmm4[16];\r
+ UINT8 Xmm5[16];\r
+ UINT8 Xmm6[16];\r
+ UINT8 Xmm7[16];\r
+ UINT8 Reserved11[14 * 16];\r
+} EFI_FX_SAVE_STATE_IA32;\r
+#else\r
+ UINT8 St0Mm0[10], Reserved3[6];\r
+ UINT8 St0Mm1[10], Reserved4[6];\r
+ UINT8 St0Mm2[10], Reserved5[6];\r
+ UINT8 St0Mm3[10], Reserved6[6];\r
+ UINT8 St0Mm4[10], Reserved7[6];\r
+ UINT8 St0Mm5[10], Reserved8[6];\r
+ UINT8 St0Mm6[10], Reserved9[6];\r
+ UINT8 St0Mm7[10], Reserved10[6];\r
+ UINT8 Reserved11[22 * 16];\r
+} EFI_FX_SAVE_STATE;\r
+#endif\r
+\r
+typedef struct {\r
+ UINT32 ExceptionData;\r
+#if (EFI_SPECIFICATION_VERSION >= 0x00020000)\r
+ EFI_FX_SAVE_STATE_IA32 FxSaveState;\r
+#else\r
+ EFI_FX_SAVE_STATE FxSaveState;\r
+#endif\r
+ UINT32 Dr0;\r
+ UINT32 Dr1;\r
+ UINT32 Dr2;\r
+ UINT32 Dr3;\r
+ UINT32 Dr6;\r
+ UINT32 Dr7;\r
+ UINT32 Cr0;\r
+ UINT32 Cr1; /* Reserved */\r
+ UINT32 Cr2;\r
+ UINT32 Cr3;\r
+ UINT32 Cr4;\r
+ UINT32 Eflags;\r
+ UINT32 Ldtr;\r
+ UINT32 Tr;\r
+ UINT32 Gdtr[2];\r
+ UINT32 Idtr[2];\r
+ UINT32 Eip;\r
+ UINT32 Gs;\r
+ UINT32 Fs;\r
+ UINT32 Es;\r
+ UINT32 Ds;\r
+ UINT32 Cs;\r
+ UINT32 Ss;\r
+ UINT32 Edi;\r
+ UINT32 Esi;\r
+ UINT32 Ebp;\r
+ UINT32 Esp;\r
+ UINT32 Ebx;\r
+ UINT32 Edx;\r
+ UINT32 Ecx;\r
+ UINT32 Eax;\r
+} EFI_SYSTEM_CONTEXT_IA32;\r
+\r
+//\r
+// X64 processor exception types\r
+//\r
+#define EXCEPT_X64_DIVIDE_ERROR 0\r
+#define EXCEPT_X64_DEBUG 1\r
+#define EXCEPT_X64_NMI 2\r
+#define EXCEPT_X64_BREAKPOINT 3\r
+#define EXCEPT_X64_OVERFLOW 4\r
+#define EXCEPT_X64_BOUND 5\r
+#define EXCEPT_X64_INVALID_OPCODE 6\r
+#define EXCEPT_X64_DOUBLE_FAULT 8\r
+#define EXCEPT_X64_INVALID_TSS 10\r
+#define EXCEPT_X64_SEG_NOT_PRESENT 11\r
+#define EXCEPT_X64_STACK_FAULT 12\r
+#define EXCEPT_X64_GP_FAULT 13\r
+#define EXCEPT_X64_PAGE_FAULT 14\r
+#define EXCEPT_X64_FP_ERROR 16\r
+#define EXCEPT_X64_ALIGNMENT_CHECK 17\r
+#define EXCEPT_X64_MACHINE_CHECK 18\r
+#define EXCEPT_X64_SIMD 19\r
+\r
+//\r
+// X64 processor context definition\r
+//\r
+// FXSAVE_STATE\r
+// FP / MMX / XMM registers (see fxrstor instruction definition)\r
+//\r
+typedef struct {\r
+ UINT16 Fcw;\r
+ UINT16 Fsw;\r
+ UINT16 Ftw;\r
+ UINT16 Opcode;\r
+ UINT64 Rip;\r
+ UINT64 DataOffset;\r
+ UINT8 Reserved1[8];\r
+ UINT8 St0Mm0[10], Reserved2[6];\r
+ UINT8 St1Mm1[10], Reserved3[6];\r
+ UINT8 St2Mm2[10], Reserved4[6];\r
+ UINT8 St3Mm3[10], Reserved5[6];\r
+ UINT8 St4Mm4[10], Reserved6[6];\r
+ UINT8 St5Mm5[10], Reserved7[6];\r
+ UINT8 St6Mm6[10], Reserved8[6];\r
+ UINT8 St7Mm7[10], Reserved9[6];\r
+ UINT8 Xmm0[16];\r
+ UINT8 Xmm1[16];\r
+ UINT8 Xmm2[16];\r
+ UINT8 Xmm3[16];\r
+ UINT8 Xmm4[16];\r
+ UINT8 Xmm5[16];\r
+ UINT8 Xmm6[16];\r
+ UINT8 Xmm7[16];\r
+#if (EFI_SPECIFICATION_VERSION >= 0x00020000)\r
+ //\r
+ // NOTE: UEFI 2.0 spec definition as follows. It should be updated \r
+ // after spec update.\r
+ //\r
+ UINT8 Reserved11[14 * 16];\r
+#else\r
+ UINT8 Xmm8[16];\r
+ UINT8 Xmm9[16];\r
+ UINT8 Xmm10[16];\r
+ UINT8 Xmm11[16];\r
+ UINT8 Xmm12[16];\r
+ UINT8 Xmm13[16];\r
+ UINT8 Xmm14[16];\r
+ UINT8 Xmm15[16];\r
+ UINT8 Reserved10[6 * 16];\r
+#endif\r
+} EFI_FX_SAVE_STATE_X64;\r
+\r
+typedef struct {\r
+ UINT64 ExceptionData;\r
+ EFI_FX_SAVE_STATE_X64 FxSaveState;\r
+ UINT64 Dr0;\r
+ UINT64 Dr1;\r
+ UINT64 Dr2;\r
+ UINT64 Dr3;\r
+ UINT64 Dr6;\r
+ UINT64 Dr7;\r
+ UINT64 Cr0;\r
+ UINT64 Cr1; /* Reserved */\r
+ UINT64 Cr2;\r
+ UINT64 Cr3;\r
+ UINT64 Cr4;\r
+ UINT64 Cr8;\r
+ UINT64 Rflags;\r
+ UINT64 Ldtr;\r
+ UINT64 Tr;\r
+ UINT64 Gdtr[2];\r
+ UINT64 Idtr[2];\r
+ UINT64 Rip;\r
+ UINT64 Gs;\r
+ UINT64 Fs;\r
+ UINT64 Es;\r
+ UINT64 Ds;\r
+ UINT64 Cs;\r
+ UINT64 Ss;\r
+ UINT64 Rdi;\r
+ UINT64 Rsi;\r
+ UINT64 Rbp;\r
+ UINT64 Rsp;\r
+ UINT64 Rbx;\r
+ UINT64 Rdx;\r
+ UINT64 Rcx;\r
+ UINT64 Rax;\r
+ UINT64 R8;\r
+ UINT64 R9;\r
+ UINT64 R10;\r
+ UINT64 R11;\r
+ UINT64 R12;\r
+ UINT64 R13;\r
+ UINT64 R14;\r
+ UINT64 R15;\r
+} EFI_SYSTEM_CONTEXT_X64;\r
+\r
+//\r
+// IPF processor exception types\r
+//\r
+#define EXCEPT_IPF_VHTP_TRANSLATION 0\r
+#define EXCEPT_IPF_INSTRUCTION_TLB 1\r
+#define EXCEPT_IPF_DATA_TLB 2\r
+#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3\r
+#define EXCEPT_IPF_ALT_DATA_TLB 4\r
+#define EXCEPT_IPF_DATA_NESTED_TLB 5\r
+#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r
+#define EXCEPT_IPF_DATA_KEY_MISSED 7\r
+#define EXCEPT_IPF_DIRTY_BIT 8\r
+#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r
+#define EXCEPT_IPF_DATA_ACCESS_BIT 10\r
+#define EXCEPT_IPF_BREAKPOINT 11\r
+#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12\r
+//\r
+// 13 - 19 reserved\r
+//\r
+#define EXCEPT_IPF_PAGE_NOT_PRESENT 20\r
+#define EXCEPT_IPF_KEY_PERMISSION 21\r
+#define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS 22\r
+#define EXCEPT_IPF_DATA_ACCESS_RIGHTS 23\r
+#define EXCEPT_IPF_GENERAL_EXCEPTION 24\r
+#define EXCEPT_IPF_DISABLED_FP_REGISTER 25\r
+#define EXCEPT_IPF_NAT_CONSUMPTION 26\r
+#define EXCEPT_IPF_SPECULATION 27\r
+//\r
+// 28 reserved\r
+//\r
+#define EXCEPT_IPF_DEBUG 29\r
+#define EXCEPT_IPF_UNALIGNED_REFERENCE 30\r
+#define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE 31\r
+#define EXCEPT_IPF_FP_FAULT 32\r
+#define EXCEPT_IPF_FP_TRAP 33\r
+#define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP 34\r
+#define EXCEPT_IPF_TAKEN_BRANCH 35\r
+#define EXCEPT_IPF_SINGLE_STEP 36\r
+//\r
+// 37 - 44 reserved\r
+//\r
+#define EXCEPT_IPF_IA32_EXCEPTION 45\r
+#define EXCEPT_IPF_IA32_INTERCEPT 46\r
+#define EXCEPT_IPF_IA32_INTERRUPT 47\r
+\r
+//\r
+// IPF processor context definition\r
+//\r
+typedef struct {\r
+ //\r
+ // The first reserved field is necessary to preserve alignment for the correct\r
+ // bits in UNAT and to insure F2 is 16 byte aligned..\r
+ //\r
+ UINT64 Reserved;\r
+ UINT64 R1;\r
+ UINT64 R2;\r
+ UINT64 R3;\r
+ UINT64 R4;\r
+ UINT64 R5;\r
+ UINT64 R6;\r
+ UINT64 R7;\r
+ UINT64 R8;\r
+ UINT64 R9;\r
+ UINT64 R10;\r
+ UINT64 R11;\r
+ UINT64 R12;\r
+ UINT64 R13;\r
+ UINT64 R14;\r
+ UINT64 R15;\r
+ UINT64 R16;\r
+ UINT64 R17;\r
+ UINT64 R18;\r
+ UINT64 R19;\r
+ UINT64 R20;\r
+ UINT64 R21;\r
+ UINT64 R22;\r
+ UINT64 R23;\r
+ UINT64 R24;\r
+ UINT64 R25;\r
+ UINT64 R26;\r
+ UINT64 R27;\r
+ UINT64 R28;\r
+ UINT64 R29;\r
+ UINT64 R30;\r
+ UINT64 R31;\r
+\r
+ UINT64 F2[2];\r
+ UINT64 F3[2];\r
+ UINT64 F4[2];\r
+ UINT64 F5[2];\r
+ UINT64 F6[2];\r
+ UINT64 F7[2];\r
+ UINT64 F8[2];\r
+ UINT64 F9[2];\r
+ UINT64 F10[2];\r
+ UINT64 F11[2];\r
+ UINT64 F12[2];\r
+ UINT64 F13[2];\r
+ UINT64 F14[2];\r
+ UINT64 F15[2];\r
+ UINT64 F16[2];\r
+ UINT64 F17[2];\r
+ UINT64 F18[2];\r
+ UINT64 F19[2];\r
+ UINT64 F20[2];\r
+ UINT64 F21[2];\r
+ UINT64 F22[2];\r
+ UINT64 F23[2];\r
+ UINT64 F24[2];\r
+ UINT64 F25[2];\r
+ UINT64 F26[2];\r
+ UINT64 F27[2];\r
+ UINT64 F28[2];\r
+ UINT64 F29[2];\r
+ UINT64 F30[2];\r
+ UINT64 F31[2];\r
+\r
+ UINT64 Pr;\r
+\r
+ UINT64 B0;\r
+ UINT64 B1;\r
+ UINT64 B2;\r
+ UINT64 B3;\r
+ UINT64 B4;\r
+ UINT64 B5;\r
+ UINT64 B6;\r
+ UINT64 B7;\r
+\r
+ //\r
+ // application registers\r
+ //\r
+ UINT64 ArRsc;\r
+ UINT64 ArBsp;\r
+ UINT64 ArBspstore;\r
+ UINT64 ArRnat;\r
+\r
+ UINT64 ArFcr;\r
+\r
+ UINT64 ArEflag;\r
+ UINT64 ArCsd;\r
+ UINT64 ArSsd;\r
+ UINT64 ArCflg;\r
+ UINT64 ArFsr;\r
+ UINT64 ArFir;\r
+ UINT64 ArFdr;\r
+\r
+ UINT64 ArCcv;\r
+\r
+ UINT64 ArUnat;\r
+\r
+ UINT64 ArFpsr;\r
+\r
+ UINT64 ArPfs;\r
+ UINT64 ArLc;\r
+ UINT64 ArEc;\r
+\r
+ //\r
+ // control registers\r
+ //\r
+ UINT64 CrDcr;\r
+ UINT64 CrItm;\r
+ UINT64 CrIva;\r
+ UINT64 CrPta;\r
+ UINT64 CrIpsr;\r
+ UINT64 CrIsr;\r
+ UINT64 CrIip;\r
+ UINT64 CrIfa;\r
+ UINT64 CrItir;\r
+ UINT64 CrIipa;\r
+ UINT64 CrIfs;\r
+ UINT64 CrIim;\r
+ UINT64 CrIha;\r
+\r
+ //\r
+ // debug registers\r
+ //\r
+ UINT64 Dbr0;\r
+ UINT64 Dbr1;\r
+ UINT64 Dbr2;\r
+ UINT64 Dbr3;\r
+ UINT64 Dbr4;\r
+ UINT64 Dbr5;\r
+ UINT64 Dbr6;\r
+ UINT64 Dbr7;\r
+\r
+ UINT64 Ibr0;\r
+ UINT64 Ibr1;\r
+ UINT64 Ibr2;\r
+ UINT64 Ibr3;\r
+ UINT64 Ibr4;\r
+ UINT64 Ibr5;\r
+ UINT64 Ibr6;\r
+ UINT64 Ibr7;\r
+\r
+ //\r
+ // virtual registers - nat bits for R1-R31\r
+ //\r
+ UINT64 IntNat;\r
+\r
+} EFI_SYSTEM_CONTEXT_IPF;\r
+\r
+//\r
+// EBC processor exception types\r
+//\r
+#define EXCEPT_EBC_UNDEFINED 0\r
+#define EXCEPT_EBC_DIVIDE_ERROR 1\r
+#define EXCEPT_EBC_DEBUG 2\r
+#define EXCEPT_EBC_BREAKPOINT 3\r
+#define EXCEPT_EBC_OVERFLOW 4\r
+#define EXCEPT_EBC_INVALID_OPCODE 5 // opcode out of range\r
+#define EXCEPT_EBC_STACK_FAULT 6\r
+#define EXCEPT_EBC_ALIGNMENT_CHECK 7\r
+#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 // malformed instruction\r
+#define EXCEPT_EBC_BAD_BREAK 9 // BREAK 0 or undefined BREAK\r
+#define EXCEPT_EBC_STEP 10 // to support debug stepping\r
+//\r
+// For coding convenience, define the maximum valid EBC exception.\r
+//\r
+#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r
+\r
+//\r
+// EBC processor context definition\r
+//\r
+typedef struct {\r
+ UINT64 R0;\r
+ UINT64 R1;\r
+ UINT64 R2;\r
+ UINT64 R3;\r
+ UINT64 R4;\r
+ UINT64 R5;\r
+ UINT64 R6;\r
+ UINT64 R7;\r
+ UINT64 Flags;\r
+ UINT64 ControlFlags;\r
+ UINT64 Ip;\r
+} EFI_SYSTEM_CONTEXT_EBC;\r
+\r
+//\r
+// Universal EFI_SYSTEM_CONTEXT definition\r
+//\r
+typedef union {\r
+ EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r
+ EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
+ EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r
+ EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r
+} EFI_SYSTEM_CONTEXT;\r
+\r
+//\r
+// DebugSupport callback function prototypes\r
+//\r
+\r
+/** \r
+ Registers and enables an exception callback function for the specified exception.\r
+ \r
+ @param ExceptionType Exception types in EBC, IA-32, X64, or IPF\r
+ @param SystemContext Exception content.\r
+ \r
+**/\r
+typedef\r
+VOID\r
+(*EFI_EXCEPTION_CALLBACK) (\r
+ IN EFI_EXCEPTION_TYPE ExceptionType,\r
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
+ );\r
+\r
+/** \r
+ Registers and enables the on-target debug agent's periodic entry point.\r
+ \r
+ @param SystemContext Exception content.\r
+ \r
+**/\r
+typedef\r
+VOID\r
+(*EFI_PERIODIC_CALLBACK) (\r
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
+ );\r
+\r
+//\r
+// Machine type definition\r
+//\r
+typedef enum {\r
+ IsaIa32 = IMAGE_FILE_MACHINE_I386, // 0x014C\r
+ IsaX64 = IMAGE_FILE_MACHINE_X64, // 0x8664\r
+ IsaIpf = IMAGE_FILE_MACHINE_IA64, // 0x0200\r
+ IsaEbc = IMAGE_FILE_MACHINE_EBC // 0x0EBC\r
+} EFI_INSTRUCTION_SET_ARCHITECTURE;\r
+\r
+\r
+//\r
+// DebugSupport member function definitions\r
+//\r
+\r
+/** \r
+ Returns the maximum value that may be used for the ProcessorIndex parameter in\r
+ RegisterPeriodicCallback() and RegisterExceptionCallback(). \r
+ \r
+ @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
+ @param MaxProcessorIndex Pointer to a caller-allocated UINTN in which the maximum supported\r
+ processor index is returned. \r
+ \r
+ @retval EFI_SUCCESS The function completed successfully. \r
+ \r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX) (\r
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
+ OUT UINTN *MaxProcessorIndex\r
+ );\r
+\r
+/** \r
+ Registers a function to be called back periodically in interrupt context.\r
+ \r
+ @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
+ @param ProcessorIndex Specifies which processor the callback function applies to.\r
+ @param PeriodicCallback A pointer to a function of type PERIODIC_CALLBACK that is the main\r
+ periodic entry point of the debug agent.\r
+ \r
+ @retval EFI_SUCCESS The function completed successfully. \r
+ @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r
+ function was previously registered. \r
+ @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback \r
+ function. \r
+ \r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK) (\r
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
+ IN UINTN ProcessorIndex,\r
+ IN EFI_PERIODIC_CALLBACK PeriodicCallback\r
+ );\r
+\r
+/** \r
+ Registers a function to be called when a given processor exception occurs.\r
+ \r
+ @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
+ @param ProcessorIndex Specifies which processor the callback function applies to.\r
+ @param PeriodicCallback A pointer to a function of type EXCEPTION_CALLBACK that is called\r
+ when the processor exception specified by ExceptionType occurs. \r
+ @param ExceptionType Specifies which processor exception to hook. \r
+ \r
+ @retval EFI_SUCCESS The function completed successfully. \r
+ @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r
+ function was previously registered. \r
+ @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback \r
+ function. \r
+ \r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK) (\r
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
+ IN UINTN ProcessorIndex,\r
+ IN EFI_EXCEPTION_CALLBACK ExceptionCallback,\r
+ IN EFI_EXCEPTION_TYPE ExceptionType\r
+ );\r
+\r
+/** \r
+ Invalidates processor instruction cache for a memory range. Subsequent execution in this range\r
+ causes a fresh memory fetch to retrieve code to be executed. \r
+ \r
+ @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
+ @param ProcessorIndex Specifies which processor's instruction cache is to be invalidated.\r
+ @param Start Specifies the physical base of the memory range to be invalidated. \r
+ @param Length Specifies the minimum number of bytes in the processor's instruction\r
+ cache to invalidate. \r
+ \r
+ @retval EFI_SUCCESS The function completed successfully. \r
+ \r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE) (\r
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
+ IN UINTN ProcessorIndex,\r
+ IN VOID *Start,\r
+ IN UINT64 Length\r
+ );\r
+\r
+//\r
+// DebugSupport protocol definition\r
+//\r
+struct _EFI_DEBUG_SUPPORT_PROTOCOL {\r
+ EFI_INSTRUCTION_SET_ARCHITECTURE Isa;\r
+ EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;\r
+ EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;\r
+ EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;\r
+ EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;\r
+};\r
+\r
+extern EFI_GUID gEfiDebugSupportProtocolGuid;\r
+\r
+#endif \r