--- /dev/null
+/** @file\r
+ This protocol abstracts the 8259 interrupt controller. This includes\r
+ PCI IRQ routing need to program the PCI Interrupt Line register.\r
+\r
+ Copyright (c) 2006, Intel Corporation \r
+ All rights reserved. This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ Module Name: Legacy8259.h\r
+\r
+ @par Revision Reference:\r
+ This protocol is defined in Framework for EFI Compatibility Support Module spec\r
+ Version 0.96\r
+\r
+**/\r
+\r
+#ifndef _EFI_LEGACY_8259_H\r
+#define _EFI_LEGACY_8259_H\r
+\r
+#define EFI_LEGACY_8259_PROTOCOL_GUID \\r
+ { \\r
+ 0x38321dba, 0x4fe0, 0x4e17, {0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1 } \\r
+ }\r
+\r
+typedef struct _EFI_LEGACY_8259_PROTOCOL EFI_LEGACY_8259_PROTOCOL;\r
+\r
+typedef enum {\r
+ Efi8259Irq0,\r
+ Efi8259Irq1,\r
+ Efi8259Irq2,\r
+ Efi8259Irq3,\r
+ Efi8259Irq4,\r
+ Efi8259Irq5,\r
+ Efi8259Irq6,\r
+ Efi8259Irq7,\r
+ Efi8259Irq8,\r
+ Efi8259Irq9,\r
+ Efi8259Irq10,\r
+ Efi8259Irq11,\r
+ Efi8259Irq12,\r
+ Efi8259Irq13,\r
+ Efi8259Irq14,\r
+ Efi8259Irq15,\r
+ Efi8259IrqMax\r
+} EFI_8259_IRQ;\r
+\r
+typedef enum {\r
+ Efi8259LegacyMode,\r
+ Efi8259ProtectedMode,\r
+ Efi8259MaxMode\r
+} EFI_8259_MODE;\r
+\r
+/**\r
+ Get the 8259 interrupt masks for Irq0 - Irq15. A different mask exists for\r
+ the legacy mode mask and the protected mode mask. The base address for the 8259\r
+ is different for legacy and protected mode, so two masks are required.\r
+\r
+ @param This Protocol instance pointer.\r
+ @param MasterBase The base vector for the Master PIC in the 8259 controller\r
+ @param Slavebase The base vector for the Master PIC in the 8259 controller\r
+\r
+ @retval EFI_SUCCESS The new bases were programmed\r
+ @retval EFI_DEVICE_ERROR A device erro occured programming the vector bases\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_8259_SET_VECTOR_BASE) (\r
+ IN EFI_LEGACY_8259_PROTOCOL *This,\r
+ IN UINT8 MasterBase,\r
+ IN UINT8 SlaveBase\r
+ )\r
+;\r
+\r
+/**\r
+ Get the 8259 interrupt masks for Irq0 - Irq15. A different mask exists for\r
+ the legacy mode mask and the protected mode mask. The base address for the 8259\r
+ is different for legacy and protected mode, so two masks are required.\r
+\r
+ @param This Protocol instance pointer.\r
+ @param LegacyMask Bit 0 is Irq0 - Bit 15 is Irq15\r
+ @param LegacyEdgeLevel Bit 0 is Irq0 - Bit 15 is Irq15\r
+ @param ProtectedMask Bit 0 is Irq0 - Bit 15 is Irq15\r
+ @param ProtectedEdgeLevel Bit 0 is Irq0 - Bit 15 is Irq15\r
+\r
+ @retval EFI_SUCCESS 8259 status returned\r
+ @retval EFI_DEVICE_ERROR Error reading 8259\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_8259_GET_MASK) (\r
+ IN EFI_LEGACY_8259_PROTOCOL *This,\r
+ OUT UINT16 *LegacyMask, OPTIONAL\r
+ OUT UINT16 *LegacyEdgeLevel, OPTIONAL\r
+ OUT UINT16 *ProtectedMask, OPTIONAL\r
+ OUT UINT16 *ProtectedEdgeLevel OPTIONAL\r
+ )\r
+;\r
+\r
+/**\r
+ Set the 8259 interrupt masks for Irq0 - Irq15. A different mask exists for\r
+ the legacy mode mask and the protected mode mask. The base address for the 8259\r
+ is different for legacy and protected mode, so two masks are required.\r
+ Also set the edge/level masks.\r
+\r
+ @param This Protocol instance pointer.\r
+ @param LegacyMask Bit 0 is Irq0 - Bit 15 is Irq15\r
+ @param LegacyEdgeLevel Bit 0 is Irq0 - Bit 15 is Irq15\r
+ @param ProtectedMask Bit 0 is Irq0 - Bit 15 is Irq15\r
+ @param ProtectedEdgeLevel Bit 0 is Irq0 - Bit 15 is Irq15\r
+\r
+ @retval EFI_SUCCESS 8259 status returned\r
+ @retval EFI_DEVICE_ERROR Error reading 8259\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_8259_SET_MASK) (\r
+ IN EFI_LEGACY_8259_PROTOCOL *This,\r
+ IN UINT16 *LegacyMask, OPTIONAL\r
+ IN UINT16 *LegacyEdgeLevel, OPTIONAL\r
+ IN UINT16 *ProtectedMask, OPTIONAL\r
+ IN UINT16 *ProtectedEdgeLevel OPTIONAL\r
+ )\r
+;\r
+\r
+/**\r
+ Set the 8259 mode of operation. The base address for the 8259 is different for\r
+ legacy and protected mode. The legacy mode requires the master 8259 to have a\r
+ master base of 0x08 and the slave base of 0x70. The protected mode base locations\r
+ are not defined. Interrupts must be masked by the caller before this function\r
+ is called. The interrupt mask from the current mode is saved. The interrupt \r
+ mask for the new mode is Mask, or if Mask does not exist the previously saved\r
+ mask is used.\r
+\r
+ @param This Protocol instance pointer.\r
+ @param Mode Mode of operation. i.e. real mode or protected mode\r
+ @param Mask Optional interupt mask for the new mode.\r
+ @param EdgeLevel Optional trigger mask for the new mode.\r
+\r
+ @retval EFI_SUCCESS 8259 programmed\r
+ @retval EFI_DEVICE_ERROR Error writting to 8259\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_8259_SET_MODE) (\r
+ IN EFI_LEGACY_8259_PROTOCOL *This,\r
+ IN EFI_8259_MODE Mode,\r
+ IN UINT16 *Mask, OPTIONAL\r
+ IN UINT16 *EdgeLevel OPTIONAL\r
+ )\r
+;\r
+\r
+/**\r
+ Convert from IRQ to processor interrupt vector number.\r
+\r
+ @param This Protocol instance pointer.\r
+ @param Irq 8259 IRQ0 - IRQ15\r
+ @param Vector Processor vector number that matches Irq\r
+\r
+ @retval EFI_SUCCESS The Vector matching Irq is returned\r
+ @retval EFI_INVALID_PARAMETER Irq not valid\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_8259_GET_VECTOR) (\r
+ IN EFI_LEGACY_8259_PROTOCOL *This,\r
+ IN EFI_8259_IRQ Irq,\r
+ OUT UINT8 *Vector\r
+ )\r
+;\r
+\r
+/**\r
+ Enable Irq by unmasking interrupt in 8259\r
+\r
+ @param This Protocol instance pointer.\r
+ @param Irq 8259 IRQ0 - IRQ15\r
+ @param LevelTriggered TRUE if level triggered. FALSE if edge triggered.\r
+\r
+ @retval EFI_SUCCESS Irq enabled on 8259\r
+ @retval EFI_INVALID_PARAMETER Irq not valid\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_8259_ENABLE_IRQ) (\r
+ IN EFI_LEGACY_8259_PROTOCOL *This,\r
+ IN EFI_8259_IRQ Irq,\r
+ IN BOOLEAN LevelTriggered\r
+ )\r
+;\r
+\r
+/**\r
+ Disable Irq by masking interrupt in 8259\r
+\r
+ @param This Protocol instance pointer.\r
+ @param Irq 8259 IRQ0 - IRQ15\r
+\r
+ @retval EFI_SUCCESS Irq disabled on 8259\r
+ @retval EFI_INVALID_PARAMETER Irq not valid\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_8259_DISABLE_IRQ) (\r
+ IN EFI_LEGACY_8259_PROTOCOL *This,\r
+ IN EFI_8259_IRQ Irq\r
+ )\r
+;\r
+\r
+/**\r
+ PciHandle represents a PCI config space of a PCI function. Vector \r
+ represents Interrupt Pin (from PCI config space) and it is the data\r
+ that is programmed into the Interrupt Line (from the PCI config space)\r
+ register.\r
+\r
+ @param This Protocol instance pointer.\r
+ @param PciHandle PCI function to return vector for\r
+ @param Vector Vector for fucntion that matches\r
+\r
+ @retval EFI_SUCCESS A valid Vector is returned\r
+ @retval EFI_INVALID_PARAMETER PciHandle not valid\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_8259_GET_INTERRUPT_LINE) (\r
+ IN EFI_LEGACY_8259_PROTOCOL *This,\r
+ IN EFI_HANDLE PciHandle,\r
+ OUT UINT8 *Vector\r
+ )\r
+;\r
+\r
+/**\r
+ Send an EOI to 8259\r
+\r
+ @param This Protocol instance pointer.\r
+ @param Irq 8259 IRQ0 - IRQ15\r
+\r
+ @retval EFI_SUCCESS EOI successfully sent to 8259\r
+ @retval EFI_INVALID_PARAMETER Irq not valid\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_8259_END_OF_INTERRUPT) (\r
+ IN EFI_LEGACY_8259_PROTOCOL *This,\r
+ IN EFI_8259_IRQ Irq\r
+ )\r
+;\r
+\r
+/**\r
+ @par Protocol Description:\r
+ Abstracts the 8259 and APIC hardware control between EFI usage and \r
+ Compatibility16 usage.\r
+\r
+ @param SetVectorBase\r
+ Sets the vector bases for master and slave PICs. \r
+\r
+ @param GetMask\r
+ Gets IRQ and edge/level masks for 16-bit real mode and 32-bit protected mode. \r
+\r
+ @param SetMask\r
+ Sets the IRQ and edge\level masks for 16-bit real mode and 32-bit protected mode.\r
+\r
+ @param SetMode\r
+ Sets PIC mode to 16-bit real mode or 32-bit protected mode.\r
+\r
+ @param GetVector\r
+ Gets the base vector assigned to an IRQ.\r
+\r
+ @param EnableIrq\r
+ Enables an IRQ. \r
+\r
+ @param DisableIrq\r
+ Disables an IRQ.\r
+\r
+ @param GetInterruptLine\r
+ Gets an IRQ that is assigned to a PCI device. \r
+\r
+ @param EndOfInterrupt\r
+ Issues the end of interrupt command. \r
+\r
+**/\r
+struct _EFI_LEGACY_8259_PROTOCOL {\r
+ EFI_LEGACY_8259_SET_VECTOR_BASE SetVectorBase;\r
+ EFI_LEGACY_8259_GET_MASK GetMask;\r
+ EFI_LEGACY_8259_SET_MASK SetMask;\r
+ EFI_LEGACY_8259_SET_MODE SetMode;\r
+ EFI_LEGACY_8259_GET_VECTOR GetVector;\r
+ EFI_LEGACY_8259_ENABLE_IRQ EnableIrq;\r
+ EFI_LEGACY_8259_DISABLE_IRQ DisableIrq;\r
+ EFI_LEGACY_8259_GET_INTERRUPT_LINE GetInterruptLine;\r
+ EFI_LEGACY_8259_END_OF_INTERRUPT EndOfInterrupt;\r
+};\r
+\r
+extern EFI_GUID gEfiLegacy8259ProtocolGuid;\r
+\r
+#endif\r
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