/** @file\r
- Template for Metronome Architecture Protocol driver of the ARM flavor\r
+ Handle OMAP35xx interrupt controller \r
\r
- Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
\r
- All rights reserved. This program and the accompanying materials\r
+ This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
#include <Library/UefiLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/IoLib.h>\r
+#include <Library/ArmLib.h>\r
\r
#include <Protocol/Cpu.h>\r
#include <Protocol/HardwareInterrupt.h>\r
MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);\r
MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);\r
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+\r
+ // Add code here to disable all FIQs as debugger may have turned one on\r
}\r
\r
/**\r
return EFI_UNSUPPORTED;\r
} \r
\r
+ if ((MmioRead32 (INTCPS_ILR(Source)) & INTCPS_ILR_FIQ) == INTCPS_ILR_FIQ) {\r
+ // This vector has been programmed as FIQ so we can't use it for IRQ\r
+ // EFI does not use FIQ, but the debugger can use it to check for \r
+ // ctrl-c. So this ASSERT means you have a conflict with the debug agent\r
+ ASSERT (FALSE);\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ \r
if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
**/\r
EFI_STATUS\r
EFIAPI\r
-DisableInterruptSource(\r
+DisableInterruptSource (\r
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
IN HARDWARE_INTERRUPT_SOURCE Source\r
)\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Signal to the hardware that the End Of Intrrupt state \r
+ has been reached.\r
+\r
+ @param This Instance pointer for this protocol\r
+ @param Source Hardware source of the interrupt\r
+\r
+ @retval EFI_SUCCESS Source interrupt EOI'ed.\r
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+EndOfInterrupt (\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source\r
+ )\r
+{\r
+ MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+ ArmDataSyncronizationBarrier ();\r
+ return EFI_SUCCESS;\r
+}\r
\r
\r
/**\r
UINT32 Vector;\r
HARDWARE_INTERRUPT_HANDLER InterruptHandler;\r
\r
- Vector = MmioRead32(INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;\r
+ Vector = MmioRead32 (INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;\r
\r
// Needed to prevent infinite nesting when Time Driver lowers TPL\r
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
-\r
+ ArmDataSyncronizationBarrier ();\r
+ \r
InterruptHandler = gRegisteredInterruptHandlers[Vector];\r
if (InterruptHandler != NULL) {\r
// Call the registered interrupt handler.\r
- InterruptHandler(Vector, SystemContext);\r
+ InterruptHandler (Vector, SystemContext);\r
}\r
\r
// Needed to clear after running the handler\r
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+ ArmDataSyncronizationBarrier ();\r
}\r
\r
//\r
RegisterInterruptSource,\r
EnableInterruptSource,\r
DisableInterruptSource,\r
- GetInterruptSourceState\r
+ GetInterruptSourceState,\r
+ EndOfInterrupt\r
};\r
\r
//\r
//\r
// Get the cpu protocol that this driver requires.\r
//\r
- Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
+ Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
ASSERT_EFI_ERROR(Status);\r
\r
//\r
// Unregister the default exception handler.\r
//\r
- Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);\r
+ Status = Cpu->RegisterInterruptHandler (Cpu, EXCEPT_ARM_IRQ, NULL);\r
ASSERT_EFI_ERROR(Status);\r
\r
//\r
// Register to receive interrupts\r
//\r
- Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);\r
+ Status = Cpu->RegisterInterruptHandler (Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);\r
ASSERT_EFI_ERROR(Status);\r
}\r
\r
MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);\r
MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);\r
MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);\r
- MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+ MmioOr32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
\r
Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,\r
&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,\r