/** @file
- Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
- All rights reserved. This program and the accompanying materials
+ This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
**/
#include "PciEmulation.h"
-#include <Omap3530/Omap3530.h>
-EFI_CPU_ARCH_PROTOCOL *gCpu;
EMBEDDED_EXTERNAL_DEVICE *gTPS65950;
#define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44
EFI_STATUS Status;
UINT8 Data = 0;
+ // Take USB host out of force-standby mode
+ MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
+ | UHH_SYSCONFIG_CLOCKACTIVITY_ON
+ | UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
+ | UHH_SYSCONFIG_ENAWAKEUP_ENABLE
+ | UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);
+ MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
+ | UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
+ | UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
+ | UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE
+ | UHH_HOSTCONFIG_ENA_INCR16_ENABLE
+ | UHH_HOSTCONFIG_ENA_INCR8_ENABLE
+ | UHH_HOSTCONFIG_ENA_INCR4_ENABLE
+ | UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON
+ | UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE);
+
+ // USB reset (GPIO 147 - Port 5 pin 19) output high
+ MmioAnd32(GPIO5_BASE + GPIO_OE, ~BIT19);
+ MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
+
// Get the Power IC protocol.
Status = gBS->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
ASSERT_EFI_ERROR(Status);
Status = gTPS65950->Write(gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
ASSERT_EFI_ERROR(Status);
-
- // USB reset (GPIO 147 - Port 5 pin 19) output low
- MmioAnd32 (GPIO5_BASE + GPIO_OE, ~BIT19);
- MmioWrite32 (GPIO5_BASE + GPIO_CLEARDATAOUT, BIT19);
-
- // Turn on functional & interface clocks to the USBHOST power domain
- MmioOr32 (CM_FCLKEN_USBHOST, CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE | CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE);
- MmioOr32 (CM_ICLKEN_USBHOST, CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE);
- // Wait for clock to become active
- while (0 == (MmioRead32 (CM_CLKSTST_USBHOST) & 1));
-
-
-
- // Take USB host out of force-standby mode
- MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
- | UHH_SYSCONFIG_CLOCKACTIVITY_ON
- | UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
- | UHH_SYSCONFIG_ENAWAKEUP_ENABLE
- | UHH_SYSCONFIG_SOFTRESET
- );
- while ((MmioRead32 (UHH_SYSSTATUS) & UHH_SYSSTATUS_RESETDONE) != UHH_SYSSTATUS_RESETDONE);
-
- MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_CLOCKACTIVITY_ON
- | UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
- | UHH_SYSCONFIG_ENAWAKEUP_ENABLE
- );
-
-
- MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_ENA_INCR16_ENABLE
- | UHH_HOSTCONFIG_ENA_INCR8_ENABLE
- | UHH_HOSTCONFIG_ENA_INCR4_ENABLE
- );
-
- // USB reset output high
- MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
-
}
+
EFI_STATUS
PciIoPollMem (
IN EFI_PCI_IO_PROTOCOL *This,
OUT VOID **Mapping
)
{
- MAP_INFO_INSTANCE *Map;
- EFI_STATUS Status;
-
- if ( HostAddress == NULL || NumberOfBytes == NULL ||
- DeviceAddress == NULL || Mapping == NULL ) {
-
- return EFI_INVALID_PARAMETER;
- }
-
-
- if (Operation >= EfiPciOperationMaximum) {
+ DMA_MAP_OPERATION DmaOperation;
+
+ if (Operation == EfiPciIoOperationBusMasterRead) {
+ DmaOperation = MapOperationBusMasterRead;
+ } else if (Operation == EfiPciIoOperationBusMasterWrite) {
+ DmaOperation = MapOperationBusMasterWrite;
+ } else if (Operation == EfiPciIoOperationBusMasterCommonBuffer) {
+ DmaOperation = MapOperationBusMasterCommonBuffer;
+ } else {
return EFI_INVALID_PARAMETER;
}
-
- *DeviceAddress = ConvertToPhysicalAddress (HostAddress);
-
- // Data cache flush (HostAddress, NumberOfBytes);
-
- // Remember range so we can flush on the other side
- Status = gBS->AllocatePool (EfiBootServicesData, sizeof (PCI_DMA_MAP), (VOID **) &Map);
- if (EFI_ERROR(Status)) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- *Mapping = Map;
-
- Map->HostAddress = (UINTN)HostAddress;
- Map->DeviceAddress = *DeviceAddress;
- Map->NumberOfBytes = *NumberOfBytes;
- Map->Operation = Operation;
-
- // EfiCpuFlushTypeWriteBack, EfiCpuFlushTypeInvalidate
- gCpu->FlushDataCache (gCpu, (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress, *NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate);
-
- return EFI_SUCCESS;
+ return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);
}
EFI_STATUS
IN VOID *Mapping
)
{
- PCI_DMA_MAP *Map;
-
- if (Mapping == NULL) {
- ASSERT (FALSE);
- return EFI_INVALID_PARAMETER;
- }
-
- Map = (PCI_DMA_MAP *)Mapping;
- if (Map->Operation == EfiPciOperationBusMasterWrite) {
- //
- // Make sure we read buffer from uncached memory and not the cache
- //
- gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);
- }
-
- FreePool (Map);
-
- return EFI_SUCCESS;
+ return DmaUnmap (Mapping);
}
EFI_STATUS
)
{
if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {
+ // Check this
return EFI_UNSUPPORTED;
}
- if (HostAddress == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
- //
- // We used uncached memory to keep coherency
- //
- if (MemoryType == EfiBootServicesData) {
- *HostAddress = UncachedAllocatePages (Pages);
- } else if (MemoryType != EfiRuntimeServicesData) {
- *HostAddress = UncachedAllocateRuntimePages (Pages);
- } else {
- return EFI_INVALID_PARAMETER;
- }
-
- return EFI_SUCCESS;
+ return DmaAllocateBuffer (MemoryType, Pages, HostAddress);
}
+
EFI_STATUS
PciIoFreeBuffer (
IN EFI_PCI_IO_PROTOCOL *This,
IN VOID *HostAddress
)
{
- if (HostAddress == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- UncachedFreePages (HostAddress, Pages);
- return EFI_SUCCESS;
+ return DmaFreeBuffer (Pages, HostAddress);
}
UINT8 PhysicalPorts;
UINTN Count;
- // Get the Cpu protocol for later use
- Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);
- ASSERT_EFI_ERROR(Status);
//Configure USB host for OMAP3530.
ConfigureUSBHost();
// Find out the capability register length and number of physical ports.
CapabilityLength = MmioRead8(Private->RootBridge.MemoryStart);
- PhysicalPorts = (MmioRead32(Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F;
+ PhysicalPorts = (MmioRead32 (Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F;
// Calculate the total size of the USB registers.
Private->RootBridge.MemorySize = CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1));
// Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates
// host controller implementation includes port power control.
for (Count = 0; Count < PhysicalPorts; Count++) {
- MmioOr32((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000);
+ MmioOr32 ((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000);
}
// Create fake PCI config space.
projects / mirror_edk2.git / blobdiff