/** @file\r
Contains root level name space objects for the platform\r
- \r
- Copyright (c) 2008, Intel Corporation<BR> All rights\r
- reserved. This program and the accompanying materials are\r
+\r
+ Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials are\r
licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
- \r
+\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
-**/ \r
+**/\r
\r
-DefinitionBlock ("Dsdt.aml", "DSDT", 1, "INTEL ", "OVMF ", 3) {\r
+DefinitionBlock ("Dsdt.aml", "DSDT", 1, "INTEL ", "OVMF ", 4) {\r
//\r
// System Sleep States\r
//\r
- Name (\_S0, Package () {5, 0, 0, 0})\r
- Name (\_S4, Package () {1, 0, 0, 0})\r
- Name (\_S5, Package () {0, 0, 0, 0})\r
+ // We build S3 and S4 with GetSuspendStates() in\r
+ // "OvmfPkg/AcpiPlatformDxe/Qemu.c".\r
+ //\r
+ Name (\_S0, Package () {5, 0, 0, 0}) // Working\r
+ Name (\_S5, Package () {0, 0, 0, 0}) // Soft Off\r
\r
//\r
// System Bus\r
//\r
// BUS, I/O, and MMIO resources\r
//\r
- Name (_CRS, ResourceTemplate () {\r
+ Name (CRES, ResourceTemplate () {\r
WORDBusNumber ( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses\r
ResourceProducer, // bit 0 of general flags is 1\r
MinFixed, // Range is fixed\r
ResourceProducer, // bit 0 of general flags is 0\r
MinFixed, // Range is fixed\r
MaxFixed, // Range is fixed\r
- PosDecode, \r
+ PosDecode,\r
EntireRange,\r
0x0000, // Granularity\r
0x0000, // Min\r
ResourceProducer, // bit 0 of general flags is 0\r
MinFixed, // Range is fixed\r
MaxFixed, // Range is fixed\r
- PosDecode, \r
+ PosDecode,\r
EntireRange,\r
0x0000, // Granularity\r
0x0D00, // Min\r
0x00020000 // Range Length\r
)\r
\r
- DWORDMEMORY ( // Descriptor for linear frame buffer video RAM\r
+ DWORDMEMORY ( // Descriptor for 32-bit MMIO\r
ResourceProducer, // bit 0 of general flags is 0\r
PosDecode,\r
MinFixed, // Range is fixed\r
MaxFixed, // Range is Fixed\r
- Cacheable,\r
+ NonCacheable,\r
ReadWrite,\r
0x00000000, // Granularity\r
0xF8000000, // Min\r
0xFFFBFFFF, // Max\r
0x00000000, // Translation\r
- 0x07FC0000 // Range Length\r
+ 0x07FC0000, // Range Length\r
+ , // ResourceSourceIndex\r
+ , // ResourceSource\r
+ PW32 // DescriptorName\r
)\r
})\r
\r
+ Name (CR64, ResourceTemplate () {\r
+ QWordMemory ( // Descriptor for 64-bit MMIO\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ PosDecode,\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is Fixed\r
+ Cacheable,\r
+ ReadWrite,\r
+ 0x00000000, // Granularity\r
+ 0x8000000000, // Min\r
+ 0xFFFFFFFFFF, // Max\r
+ 0x00000000, // Translation\r
+ 0x8000000000, // Range Length\r
+ , // ResourceSourceIndex\r
+ , // ResourceSource\r
+ PW64 // DescriptorName\r
+ )\r
+ })\r
+\r
+ Method (_CRS, 0, Serialized) {\r
+ //\r
+ // see the FIRMWARE_DATA structure in "OvmfPkg/AcpiPlatformDxe/Qemu.c"\r
+ //\r
+ External (FWDT, OpRegionObj)\r
+ Field(FWDT, QWordAcc, NoLock, Preserve) {\r
+ P0S, 64, // PciWindow32.Base\r
+ P0E, 64, // PciWindow32.End\r
+ P0L, 64, // PciWindow32.Length\r
+ P1S, 64, // PciWindow64.Base\r
+ P1E, 64, // PciWindow64.End\r
+ P1L, 64 // PciWindow64.Length\r
+ }\r
+ Field(FWDT, DWordAcc, NoLock, Preserve) {\r
+ P0SL, 32, // PciWindow32.Base, low 32 bits\r
+ P0SH, 32, // PciWindow32.Base, high 32 bits\r
+ P0EL, 32, // PciWindow32.End, low 32 bits\r
+ P0EH, 32, // PciWindow32.End, high 32 bits\r
+ P0LL, 32, // PciWindow32.Length, low 32 bits\r
+ P0LH, 32, // PciWindow32.Length, high 32 bits\r
+ P1SL, 32, // PciWindow64.Base, low 32 bits\r
+ P1SH, 32, // PciWindow64.Base, high 32 bits\r
+ P1EL, 32, // PciWindow64.End, low 32 bits\r
+ P1EH, 32, // PciWindow64.End, high 32 bits\r
+ P1LL, 32, // PciWindow64.Length, low 32 bits\r
+ P1LH, 32 // PciWindow64.Length, high 32 bits\r
+ }\r
+\r
+ //\r
+ // fixup 32-bit PCI IO window\r
+ //\r
+ CreateDWordField (CRES, \_SB.PCI0.PW32._MIN, PS32)\r
+ CreateDWordField (CRES, \_SB.PCI0.PW32._MAX, PE32)\r
+ CreateDWordField (CRES, \_SB.PCI0.PW32._LEN, PL32)\r
+ Store (P0SL, PS32)\r
+ Store (P0EL, PE32)\r
+ Store (P0LL, PL32)\r
+\r
+ If (LAnd (LEqual (P1SL, 0x00), LEqual (P1SH, 0x00))) {\r
+ Return (CRES)\r
+ } Else {\r
+ //\r
+ // fixup 64-bit PCI IO window\r
+ //\r
+ CreateQWordField (CR64, \_SB.PCI0.PW64._MIN, PS64)\r
+ CreateQWordField (CR64, \_SB.PCI0.PW64._MAX, PE64)\r
+ CreateQWordField (CR64, \_SB.PCI0.PW64._LEN, PL64)\r
+ Store (P1S, PS64)\r
+ Store (P1E, PE64)\r
+ Store (P1L, PL64)\r
+\r
+ //\r
+ // add window and return result\r
+ //\r
+ ConcatenateResTemplate (CRES, CR64, Local0)\r
+ Return (Local0)\r
+ }\r
+ }\r
+\r
//\r
// PCI Interrupt Routing Table - PIC Mode Only\r
//\r
Return (\r
Package () {\r
//\r
- // Bus 0, Device 1\r
+ // Bus 0; Devices 0 to 15\r
+ //\r
+ Package () {0x0000FFFF, 0x00, \_SB.PCI0.LPC.LNKD, 0x00},\r
+ Package () {0x0000FFFF, 0x01, \_SB.PCI0.LPC.LNKA, 0x00},\r
+ Package () {0x0000FFFF, 0x02, \_SB.PCI0.LPC.LNKB, 0x00},\r
+ Package () {0x0000FFFF, 0x03, \_SB.PCI0.LPC.LNKC, 0x00},\r
+\r
+ //\r
+ // Bus 0, Device 1, Pin 0 (INTA) is special; it corresponds to the\r
+ // internally generated SCI (System Control Interrupt), which is\r
+ // always routed to GSI 9. By setting the third (= Source) field to\r
+ // zero, we could use the fourth (= Source Index) field to hardwire\r
+ // the pin to GSI 9 directly.\r
+ //\r
+ // That way however, in accordance with the ACPI spec's description\r
+ // of SCI, the interrupt would be treated as "active low,\r
+ // shareable, level", and that doesn't match qemu.\r
+ //\r
+ // In QemuInstallAcpiMadtTable() [OvmfPkg/AcpiPlatformDxe/Qemu.c]\r
+ // we install an Interrupt Override Structure for the identity\r
+ // mapped IRQ#9 / GSI 9 (the corresponding bit being set in\r
+ // Pcd8259LegacyModeEdgeLevel), which describes the correct\r
+ // polarity (active high). As a consequence, some OS'en (eg. Linux)\r
+ // override the default (active low) polarity originating from the\r
+ // _PRT; others (eg. FreeBSD) don't. Therefore we need a separate\r
+ // link device just to specify a polarity that matches the MADT.\r
//\r
- Package () {0x0001FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},\r
+ Package () {0x0001FFFF, 0x00, \_SB.PCI0.LPC.LNKS, 0x00},\r
+\r
Package () {0x0001FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},\r
Package () {0x0001FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},\r
Package () {0x0001FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},\r
- //\r
- // Bus 0, Device 3\r
- //\r
- Package () {0x0003FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},\r
- Package () {0x0003FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},\r
- Package () {0x0003FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},\r
- Package () {0x0003FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},\r
+\r
+ Package () {0x0002FFFF, 0x00, \_SB.PCI0.LPC.LNKB, 0x00},\r
+ Package () {0x0002FFFF, 0x01, \_SB.PCI0.LPC.LNKC, 0x00},\r
+ Package () {0x0002FFFF, 0x02, \_SB.PCI0.LPC.LNKD, 0x00},\r
+ Package () {0x0002FFFF, 0x03, \_SB.PCI0.LPC.LNKA, 0x00},\r
+\r
+ Package () {0x0003FFFF, 0x00, \_SB.PCI0.LPC.LNKC, 0x00},\r
+ Package () {0x0003FFFF, 0x01, \_SB.PCI0.LPC.LNKD, 0x00},\r
+ Package () {0x0003FFFF, 0x02, \_SB.PCI0.LPC.LNKA, 0x00},\r
+ Package () {0x0003FFFF, 0x03, \_SB.PCI0.LPC.LNKB, 0x00},\r
+\r
+ Package () {0x0004FFFF, 0x00, \_SB.PCI0.LPC.LNKD, 0x00},\r
+ Package () {0x0004FFFF, 0x01, \_SB.PCI0.LPC.LNKA, 0x00},\r
+ Package () {0x0004FFFF, 0x02, \_SB.PCI0.LPC.LNKB, 0x00},\r
+ Package () {0x0004FFFF, 0x03, \_SB.PCI0.LPC.LNKC, 0x00},\r
+\r
+ Package () {0x0005FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},\r
+ Package () {0x0005FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},\r
+ Package () {0x0005FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},\r
+ Package () {0x0005FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},\r
+\r
+ Package () {0x0006FFFF, 0x00, \_SB.PCI0.LPC.LNKB, 0x00},\r
+ Package () {0x0006FFFF, 0x01, \_SB.PCI0.LPC.LNKC, 0x00},\r
+ Package () {0x0006FFFF, 0x02, \_SB.PCI0.LPC.LNKD, 0x00},\r
+ Package () {0x0006FFFF, 0x03, \_SB.PCI0.LPC.LNKA, 0x00},\r
+\r
+ Package () {0x0007FFFF, 0x00, \_SB.PCI0.LPC.LNKC, 0x00},\r
+ Package () {0x0007FFFF, 0x01, \_SB.PCI0.LPC.LNKD, 0x00},\r
+ Package () {0x0007FFFF, 0x02, \_SB.PCI0.LPC.LNKA, 0x00},\r
+ Package () {0x0007FFFF, 0x03, \_SB.PCI0.LPC.LNKB, 0x00},\r
+\r
+ Package () {0x0008FFFF, 0x00, \_SB.PCI0.LPC.LNKD, 0x00},\r
+ Package () {0x0008FFFF, 0x01, \_SB.PCI0.LPC.LNKA, 0x00},\r
+ Package () {0x0008FFFF, 0x02, \_SB.PCI0.LPC.LNKB, 0x00},\r
+ Package () {0x0008FFFF, 0x03, \_SB.PCI0.LPC.LNKC, 0x00},\r
+\r
+ Package () {0x0009FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},\r
+ Package () {0x0009FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},\r
+ Package () {0x0009FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},\r
+ Package () {0x0009FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},\r
+\r
+ Package () {0x000AFFFF, 0x00, \_SB.PCI0.LPC.LNKB, 0x00},\r
+ Package () {0x000AFFFF, 0x01, \_SB.PCI0.LPC.LNKC, 0x00},\r
+ Package () {0x000AFFFF, 0x02, \_SB.PCI0.LPC.LNKD, 0x00},\r
+ Package () {0x000AFFFF, 0x03, \_SB.PCI0.LPC.LNKA, 0x00},\r
+\r
+ Package () {0x000BFFFF, 0x00, \_SB.PCI0.LPC.LNKC, 0x00},\r
+ Package () {0x000BFFFF, 0x01, \_SB.PCI0.LPC.LNKD, 0x00},\r
+ Package () {0x000BFFFF, 0x02, \_SB.PCI0.LPC.LNKA, 0x00},\r
+ Package () {0x000BFFFF, 0x03, \_SB.PCI0.LPC.LNKB, 0x00},\r
+\r
+ Package () {0x000CFFFF, 0x00, \_SB.PCI0.LPC.LNKD, 0x00},\r
+ Package () {0x000CFFFF, 0x01, \_SB.PCI0.LPC.LNKA, 0x00},\r
+ Package () {0x000CFFFF, 0x02, \_SB.PCI0.LPC.LNKB, 0x00},\r
+ Package () {0x000CFFFF, 0x03, \_SB.PCI0.LPC.LNKC, 0x00},\r
+\r
+ Package () {0x000DFFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},\r
+ Package () {0x000DFFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},\r
+ Package () {0x000DFFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},\r
+ Package () {0x000DFFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},\r
+\r
+ Package () {0x000EFFFF, 0x00, \_SB.PCI0.LPC.LNKB, 0x00},\r
+ Package () {0x000EFFFF, 0x01, \_SB.PCI0.LPC.LNKC, 0x00},\r
+ Package () {0x000EFFFF, 0x02, \_SB.PCI0.LPC.LNKD, 0x00},\r
+ Package () {0x000EFFFF, 0x03, \_SB.PCI0.LPC.LNKA, 0x00},\r
+\r
+ Package () {0x000FFFFF, 0x00, \_SB.PCI0.LPC.LNKC, 0x00},\r
+ Package () {0x000FFFFF, 0x01, \_SB.PCI0.LPC.LNKD, 0x00},\r
+ Package () {0x000FFFFF, 0x02, \_SB.PCI0.LPC.LNKA, 0x00},\r
+ Package () {0x000FFFFF, 0x03, \_SB.PCI0.LPC.LNKB, 0x00}\r
}\r
)\r
}\r
\r
//\r
// PCI to ISA Bridge (Bus 0, Device 1, Function 0)\r
+ // "Low Pin Count"\r
//\r
Device (LPC) {\r
Name (_ADR, 0x00010000)\r
\r
//\r
- // PCI Interrupt Routing Configuration Registers\r
+ // The SCI cannot be rerouted or disabled with PIRQRC[A:D]; we only\r
+ // need this link device in order to specify the polarity.\r
+ //\r
+ Device (LNKS) {\r
+ Name (_HID, EISAID("PNP0C0F"))\r
+ Name (_UID, 0)\r
+\r
+ Name (_STA, 0xB) // 0x1: device present\r
+ // 0x2: enabled and decoding resources\r
+ // 0x8: functioning properly\r
+\r
+ Method (_SRS, 1, NotSerialized) { /* no-op */ }\r
+ Method (_DIS, 0, NotSerialized) { /* no-op */ }\r
+\r
+ Name (_PRS, ResourceTemplate () {\r
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { 9 }\r
+ //\r
+ // list of IRQs occupied thus far: 9\r
+ //\r
+ })\r
+ Method (_CRS, 0, NotSerialized) { Return (_PRS) }\r
+ }\r
+\r
+ //\r
+ // PCI Interrupt Routing Configuration Registers, PIRQRC[A:D]\r
//\r
OperationRegion (PRR0, PCI_Config, 0x60, 0x04)\r
Field (PRR0, ANYACC, NOLOCK, PRESERVE) {\r
\r
//\r
// _STA method for LNKA, LNKB, LNKC, LNKD\r
+ // Arg0[in]: value of PIRA / PIRB / PIRC / PIRD\r
//\r
Method (PSTA, 1, NotSerialized) {\r
- If (And (Arg0, 0x80)) {\r
- Return (0x9)\r
+ If (And (Arg0, 0x80)) { // disable-bit set?\r
+ Return (0x9) // "device present" | "functioning properly"\r
} Else {\r
- Return (0xB)\r
+ Return (0xB) // same | "enabled and decoding resources"\r
}\r
}\r
\r
- //\r
- // _DIS method for LNKA, LNKB, LNKC, LNKD\r
- //\r
- Method (PDIS, 1, NotSerialized) {\r
- Or (Arg0, 0x80, Arg0)\r
- }\r
-\r
//\r
// _CRS method for LNKA, LNKB, LNKC, LNKD\r
+ // Arg0[in]: value of PIRA / PIRB / PIRC / PIRD\r
//\r
- Method (PCRS, 1, NotSerialized) {\r
- Name (BUF0, ResourceTemplate () {IRQ (Level, ActiveLow, Shared){0}})\r
+ Method (PCRS, 1, Serialized) {\r
//\r
- // Define references to buffer elements\r
+ // create temporary buffer with an Extended Interrupt Descriptor\r
+ // whose single vector defaults to zero\r
//\r
- CreateWordField (BUF0, 0x01, IRQW) // IRQ low\r
+ Name (BUF0, ResourceTemplate () {\r
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared){0}\r
+ }\r
+ )\r
+\r
//\r
- // Write current settings into IRQ descriptor\r
+ // define reference to first interrupt vector in buffer\r
//\r
- If (And (Arg0, 0x80)) {\r
- Store (Zero, Local0)\r
- } Else {\r
- Store (One, Local0)\r
- }\r
+ CreateDWordField (BUF0, 0x05, IRQW)\r
+\r
//\r
- // Shift 1 by value in register 70\r
+ // If the disable-bit is clear, overwrite the default zero vector\r
+ // with the value in Arg0 (ie. PIRQRC[A:D]). Reserved bits are read\r
+ // as 0.\r
//\r
- ShiftLeft (Local0, And (Arg0, 0x0F), IRQW) // Save in buffer\r
- Return (BUF0) // Return Buf0 \r
+ If (LNot (And (Arg0, 0x80))) {\r
+ Store (Arg0, IRQW)\r
+ }\r
+ Return (BUF0)\r
}\r
\r
//\r
// _PRS resource for LNKA, LNKB, LNKC, LNKD\r
//\r
Name (PPRS, ResourceTemplate () {\r
- IRQ (Level, ActiveLow, Shared) {3, 4, 5, 7, 9, 10, 11, 12, 14, 15}\r
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) {5, 10, 11}\r
+ //\r
+ // list of IRQs occupied thus far: 9, 5, 10, 11\r
+ //\r
})\r
\r
- //\r
- // _SRS method for LNKA, LNKB, LNKC, LNKD\r
- //\r
- Method (PSRS, 2, NotSerialized) {\r
- CreateWordField (Arg1, 0x01, IRQW) // IRQ low\r
- FindSetRightBit (IRQW, Local0) // Set IRQ\r
- If (LNotEqual (IRQW, Zero)) {\r
- And (Local0, 0x7F, Local0)\r
- Decrement (Local0)\r
- } Else {\r
- Or (Local0, 0x80, Local0)\r
- }\r
- Store (Local0, Arg0)\r
- }\r
-\r
//\r
// PCI IRQ Link A\r
//\r
Name (_UID, 1)\r
\r
Method (_STA, 0, NotSerialized) { Return (PSTA (PIRA)) }\r
- Method (_DIS, 0, NotSerialized) { PDIS (PIRA) }\r
+ Method (_DIS, 0, NotSerialized) {\r
+ Or (PIRA, 0x80, PIRA) // set disable-bit\r
+ }\r
Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRA)) }\r
Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
- Method (_SRS, 1, NotSerialized) { PSRS (PIRA, Arg0) } \r
+ Method (_SRS, 1, NotSerialized) {\r
+ CreateDWordField (Arg0, 0x05, IRQW)\r
+ Store (IRQW, PIRA)\r
+ }\r
}\r
\r
//\r
Name (_UID, 2)\r
\r
Method (_STA, 0, NotSerialized) { Return (PSTA (PIRB)) }\r
- Method (_DIS, 0, NotSerialized) { PDIS (PIRB) }\r
+ Method (_DIS, 0, NotSerialized) {\r
+ Or (PIRB, 0x80, PIRB) // set disable-bit\r
+ }\r
Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRB)) }\r
Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
- Method (_SRS, 1, NotSerialized) { PSRS (PIRB, Arg0) } \r
+ Method (_SRS, 1, NotSerialized) {\r
+ CreateDWordField (Arg0, 0x05, IRQW)\r
+ Store (IRQW, PIRB)\r
+ }\r
}\r
\r
//\r
Name (_UID, 3)\r
\r
Method (_STA, 0, NotSerialized) { Return (PSTA (PIRC)) }\r
- Method (_DIS, 0, NotSerialized) { PDIS (PIRC) }\r
+ Method (_DIS, 0, NotSerialized) {\r
+ Or (PIRC, 0x80, PIRC) // set disable-bit\r
+ }\r
Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRC)) }\r
Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
- Method (_SRS, 1, NotSerialized) { PSRS (PIRC, Arg0) } \r
+ Method (_SRS, 1, NotSerialized) {\r
+ CreateDWordField (Arg0, 0x05, IRQW)\r
+ Store (IRQW, PIRC)\r
+ }\r
}\r
\r
//\r
//\r
Device (LNKD) {\r
Name (_HID, EISAID("PNP0C0F"))\r
- Name (_UID, 1)\r
+ Name (_UID, 4)\r
\r
Method (_STA, 0, NotSerialized) { Return (PSTA (PIRD)) }\r
- Method (_DIS, 0, NotSerialized) { PDIS (PIRD) }\r
+ Method (_DIS, 0, NotSerialized) {\r
+ Or (PIRD, 0x80, PIRD) // set disable-bit\r
+ }\r
Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRD)) }\r
Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
- Method (_SRS, 1, NotSerialized) { PSRS (PIRD, Arg0) } \r
+ Method (_SRS, 1, NotSerialized) {\r
+ CreateDWordField (Arg0, 0x05, IRQW)\r
+ Store (IRQW, PIRD)\r
+ }\r
}\r
- \r
+\r
//\r
// Programmable Interrupt Controller (PIC)\r
//\r
IO (Decode16, 0x0A0, 0x0A0, 0x00, 0x02)\r
IO (Decode16, 0x4D0, 0x4D0, 0x00, 0x02)\r
IRQNoFlags () {2}\r
+ //\r
+ // list of IRQs occupied thus far: 9, 5, 10, 11, 2\r
+ //\r
})\r
}\r
\r
//\r
- // ISA DMA \r
+ // ISA DMA\r
//\r
Device (DMAC) {\r
- Name (_HID, EISAID ("PNP0200")) \r
+ Name (_HID, EISAID ("PNP0200"))\r
Name (_CRS, ResourceTemplate () {\r
IO (Decode16, 0x00, 0x00, 0, 0x10)\r
IO (Decode16, 0x81, 0x81, 0, 0x03)\r
Name(_CRS, ResourceTemplate () {\r
IO (Decode16, 0x40, 0x40, 0x00, 0x04)\r
IRQNoFlags () {0}\r
+ //\r
+ // list of IRQs occupied thus far: 9, 5, 10, 11, 2, 0\r
+ //\r
})\r
}\r
\r
Name (_CRS, ResourceTemplate () {\r
IO (Decode16, 0x70, 0x70, 0x00, 0x02)\r
IRQNoFlags () {8}\r
+ //\r
+ // list of IRQs occupied thus far: 9, 5, 10, 11, 2, 0, 8\r
+ //\r
})\r
}\r
\r
Name (_CRS, ResourceTemplate () {\r
IO (Decode16, 0xF0, 0xF0, 0x00, 0x10)\r
IRQNoFlags () {13}\r
+ //\r
+ // list of IRQs occupied thus far: 9, 5, 10, 11, 2, 0, 8, 13\r
+ //\r
})\r
}\r
\r
IO (Decode16, 0x278, 0x278, 0x00, 0x08)\r
IO (Decode16, 0x370, 0x370, 0x00, 0x02)\r
IO (Decode16, 0x378, 0x378, 0x00, 0x08)\r
- IO (Decode16, 0x400, 0x400, 0x00, 0x40) // PMBLK1\r
+ IO (Decode16, FixedPcdGet16 (PcdDebugIoPort), FixedPcdGet16 (PcdDebugIoPort), 0x00, 0x01)\r
IO (Decode16, 0x440, 0x440, 0x00, 0x10)\r
IO (Decode16, 0x678, 0x678, 0x00, 0x08)\r
IO (Decode16, 0x778, 0x778, 0x00, 0x08)\r
- Memory32Fixed (ReadOnly, 0xFEC00000, 0x1000) // IO APIC\r
- Memory32Fixed (ReadOnly, 0xFEE00000, 0x1000)\r
+ IO (Decode16, 0xafe0, 0xafe0, 0x00, 0x04) // QEMU GPE0 BLK\r
+ IO (Decode16, 0xb000, 0xb000, 0x00, 0x40) // PMBLK1\r
+ Memory32Fixed (ReadOnly, 0xFEC00000, 0x1000) // IO APIC\r
+ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) // LAPIC\r
})\r
}\r
\r
//\r
// PS/2 Keyboard and PC/AT Enhanced Keyboard 101/102\r
//\r
- Device (PS2K) { \r
+ Device (PS2K) {\r
Name (_HID, EISAID ("PNP0303"))\r
Name (_CID, EISAID ("PNP030B"))\r
Name(_CRS,ResourceTemplate() {\r
IO (Decode16, 0x60, 0x60, 0x00, 0x01)\r
IO (Decode16, 0x64, 0x64, 0x00, 0x01)\r
IRQNoFlags () {1}\r
+ //\r
+ // list of IRQs occupied thus far: 9, 5, 10, 11, 2, 0, 8, 13, 1\r
+ //\r
})\r
}\r
\r
Name (_CID, EISAID ("PNP0F13"))\r
Name (_CRS, ResourceTemplate() {\r
IRQNoFlags () {12}\r
+ //\r
+ // list of IRQs occupied thus far:\r
+ // 9, 5, 10, 11, 2, 0, 8, 13, 1, 12\r
+ //\r
})\r
}\r
\r
Name(_CRS,ResourceTemplate() {\r
IO (Decode16, 0x3F8, 0x3F8, 0x01, 0x08)\r
IRQ (Edge, ActiveHigh, Exclusive, ) {4}\r
+ //\r
+ // list of IRQs occupied thus far:\r
+ // 9, 5, 10, 11, 2, 0, 8, 13, 1, 12, 4\r
+ //\r
})\r
}\r
\r
Name(_CRS,ResourceTemplate() {\r
IO (Decode16, 0x2F8, 0x2F8, 0x01, 0x08)\r
IRQ (Edge, ActiveHigh, Exclusive, ) {3}\r
+ //\r
+ // list of IRQs occupied thus far:\r
+ // 9, 5, 10, 11, 2, 0, 8, 13, 1, 12, 4, 3\r
+ //\r
})\r
}\r
\r
IO (Decode16, 0x3F0, 0x3F0, 0x01, 0x06)\r
IO (Decode16, 0x3F7, 0x3F7, 0x01, 0x01)\r
IRQNoFlags () {6}\r
+ //\r
+ // list of IRQs occupied thus far:\r
+ // 9, 5, 10, 11, 2, 0, 8, 13, 1, 12, 4, 3, 6\r
+ //\r
DMA (Compatibility, NotBusMaster, Transfer8) {2}\r
})\r
}\r
+\r
+ //\r
+ // parallel port -- no DMA for now\r
+ //\r
+ Device (PAR1) {\r
+ Name (_HID, EISAID ("PNP0400"))\r
+ Name (_DDN, "LPT1")\r
+ Name (_UID, 0x01)\r
+ Name(_CRS, ResourceTemplate() {\r
+ IO (Decode16, 0x0378, 0x0378, 0x00, 0x08)\r
+ IRQNoFlags () {7}\r
+ //\r
+ // list of IRQs occupied thus far:\r
+ // 9, 5, 10, 11, 2, 0, 8, 13, 1, 12, 4, 3, 6, 7\r
+ // in order:\r
+ // 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13\r
+ //\r
+ })\r
+ }\r
}\r
}\r
}\r
}\r
-\r
projects / mirror_edk2.git / blobdiff