/** @file\r
Contains root level name space objects for the platform\r
- \r
+\r
Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials are\r
licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
- \r
+\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
-**/ \r
+**/\r
\r
DefinitionBlock ("Dsdt.aml", "DSDT", 1, "INTEL ", "OVMF ", 3) {\r
//\r
//\r
// BUS, I/O, and MMIO resources\r
//\r
- Name (_CRS, ResourceTemplate () {\r
+ Name (CRES, ResourceTemplate () {\r
WORDBusNumber ( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses\r
ResourceProducer, // bit 0 of general flags is 1\r
MinFixed, // Range is fixed\r
ResourceProducer, // bit 0 of general flags is 0\r
MinFixed, // Range is fixed\r
MaxFixed, // Range is fixed\r
- PosDecode, \r
+ PosDecode,\r
EntireRange,\r
0x0000, // Granularity\r
0x0000, // Min\r
ResourceProducer, // bit 0 of general flags is 0\r
MinFixed, // Range is fixed\r
MaxFixed, // Range is fixed\r
- PosDecode, \r
+ PosDecode,\r
EntireRange,\r
0x0000, // Granularity\r
0x0D00, // Min\r
0x00020000 // Range Length\r
)\r
\r
- DWORDMEMORY ( // Descriptor for linear frame buffer video RAM\r
+ DWORDMEMORY ( // Descriptor for 32-bit MMIO\r
ResourceProducer, // bit 0 of general flags is 0\r
PosDecode,\r
MinFixed, // Range is fixed\r
MaxFixed, // Range is Fixed\r
- Cacheable,\r
+ NonCacheable,\r
ReadWrite,\r
0x00000000, // Granularity\r
0xF8000000, // Min\r
0xFFFBFFFF, // Max\r
0x00000000, // Translation\r
- 0x07FC0000 // Range Length\r
+ 0x07FC0000, // Range Length\r
+ , // ResourceSourceIndex\r
+ , // ResourceSource\r
+ PW32 // DescriptorName\r
)\r
})\r
\r
+ Name (CR64, ResourceTemplate () {\r
+ QWordMemory ( // Descriptor for 64-bit MMIO\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ PosDecode,\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is Fixed\r
+ Cacheable,\r
+ ReadWrite,\r
+ 0x00000000, // Granularity\r
+ 0x8000000000, // Min\r
+ 0xFFFFFFFFFF, // Max\r
+ 0x00000000, // Translation\r
+ 0x8000000000, // Range Length\r
+ , // ResourceSourceIndex\r
+ , // ResourceSource\r
+ PW64 // DescriptorName\r
+ )\r
+ })\r
+\r
+ Method (_CRS, 0) {\r
+ //\r
+ // see the FIRMWARE_DATA structure in "OvmfPkg/AcpiPlatformDxe/Qemu.c"\r
+ //\r
+ External (FWDT, OpRegionObj)\r
+ Field(FWDT, QWordAcc, NoLock, Preserve) {\r
+ P0S, 64, // PciWindow32.Base\r
+ P0E, 64, // PciWindow32.End\r
+ P0L, 64, // PciWindow32.Length\r
+ P1S, 64, // PciWindow64.Base\r
+ P1E, 64, // PciWindow64.End\r
+ P1L, 64 // PciWindow64.Length\r
+ }\r
+ Field(FWDT, DWordAcc, NoLock, Preserve) {\r
+ P0SL, 32, // PciWindow32.Base, low 32 bits\r
+ P0SH, 32, // PciWindow32.Base, high 32 bits\r
+ P0EL, 32, // PciWindow32.End, low 32 bits\r
+ P0EH, 32, // PciWindow32.End, high 32 bits\r
+ P0LL, 32, // PciWindow32.Length, low 32 bits\r
+ P0LH, 32, // PciWindow32.Length, high 32 bits\r
+ P1SL, 32, // PciWindow64.Base, low 32 bits\r
+ P1SH, 32, // PciWindow64.Base, high 32 bits\r
+ P1EL, 32, // PciWindow64.End, low 32 bits\r
+ P1EH, 32, // PciWindow64.End, high 32 bits\r
+ P1LL, 32, // PciWindow64.Length, low 32 bits\r
+ P1LH, 32 // PciWindow64.Length, high 32 bits\r
+ }\r
+\r
+ //\r
+ // fixup 32-bit PCI IO window\r
+ //\r
+ CreateDWordField (CRES, \_SB.PCI0.PW32._MIN, PS32)\r
+ CreateDWordField (CRES, \_SB.PCI0.PW32._MAX, PE32)\r
+ CreateDWordField (CRES, \_SB.PCI0.PW32._LEN, PL32)\r
+ Store (P0SL, PS32)\r
+ Store (P0EL, PE32)\r
+ Store (P0LL, PL32)\r
+\r
+ If (LAnd (LEqual (P1SL, 0x00), LEqual (P1SH, 0x00))) {\r
+ Return (CRES)\r
+ } Else {\r
+ //\r
+ // fixup 64-bit PCI IO window\r
+ //\r
+ CreateQWordField (CR64, \_SB.PCI0.PW64._MIN, PS64)\r
+ CreateQWordField (CR64, \_SB.PCI0.PW64._MAX, PE64)\r
+ CreateQWordField (CR64, \_SB.PCI0.PW64._LEN, PL64)\r
+ Store (P1S, PS64)\r
+ Store (P1E, PE64)\r
+ Store (P1L, PL64)\r
+\r
+ //\r
+ // add window and return result\r
+ //\r
+ ConcatenateResTemplate (CRES, CR64, Local0)\r
+ Return (Local0)\r
+ }\r
+ }\r
+\r
//\r
// PCI Interrupt Routing Table - PIC Mode Only\r
//\r
}\r
}\r
\r
- //\r
- // _DIS method for LNKA, LNKB, LNKC, LNKD\r
- //\r
- Method (PDIS, 1, NotSerialized) {\r
- Or (Arg0, 0x80, Arg0)\r
- }\r
-\r
//\r
// _CRS method for LNKA, LNKB, LNKC, LNKD\r
//\r
Method (PCRS, 1, NotSerialized) {\r
- Name (BUF0, ResourceTemplate () {IRQ (Level, ActiveLow, Shared){0}})\r
//\r
- // Define references to buffer elements\r
+ // create temporary buffer with an Extended Interrupt Descriptor\r
+ // whose single vector defaults to zero\r
//\r
- CreateWordField (BUF0, 0x01, IRQW) // IRQ low\r
+ Name (BUF0, ResourceTemplate () {\r
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared){0}\r
+ }\r
+ )\r
+\r
//\r
- // Write current settings into IRQ descriptor\r
+ // define reference to first interrupt vector in buffer\r
//\r
- If (And (Arg0, 0x80)) {\r
- Store (Zero, Local0)\r
- } Else {\r
- Store (One, Local0)\r
- }\r
+ CreateDWordField (BUF0, 0x05, IRQW)\r
+\r
//\r
- // Shift 1 by value in register 70\r
+ // If the disable-bit is clear, overwrite the default zero vector\r
+ // with the value in Arg0 (ie. PIRQRC[A:D]). Reserved bits are read\r
+ // as 0.\r
//\r
- ShiftLeft (Local0, And (Arg0, 0x0F), IRQW) // Save in buffer\r
- Return (BUF0) // Return Buf0 \r
+ If (LNot (And (Arg0, 0x80))) {\r
+ Store (Arg0, IRQW)\r
+ }\r
+ Return (BUF0)\r
}\r
\r
//\r
// _PRS resource for LNKA, LNKB, LNKC, LNKD\r
//\r
Name (PPRS, ResourceTemplate () {\r
- IRQ (Level, ActiveLow, Shared) {3, 4, 5, 7, 9, 10, 11, 12, 14, 15}\r
- })\r
-\r
- //\r
- // _SRS method for LNKA, LNKB, LNKC, LNKD\r
- //\r
- Method (PSRS, 2, NotSerialized) {\r
- CreateWordField (Arg1, 0x01, IRQW) // IRQ low\r
- FindSetRightBit (IRQW, Local0) // Set IRQ\r
- If (LNotEqual (IRQW, Zero)) {\r
- And (Local0, 0x7F, Local0)\r
- Decrement (Local0)\r
- } Else {\r
- Or (Local0, 0x80, Local0)\r
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) {\r
+ 3, 4, 5, 7, 9, 10, 11, 12, 14, 15\r
}\r
- Store (Local0, Arg0)\r
- }\r
+ })\r
\r
//\r
// PCI IRQ Link A\r
Name (_UID, 1)\r
\r
Method (_STA, 0, NotSerialized) { Return (PSTA (PIRA)) }\r
- Method (_DIS, 0, NotSerialized) { PDIS (PIRA) }\r
+ Method (_DIS, 0, NotSerialized) {\r
+ Or (PIRA, 0x80, PIRA) // set disable-bit\r
+ }\r
Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRA)) }\r
Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
- Method (_SRS, 1, NotSerialized) { PSRS (PIRA, Arg0) } \r
+ Method (_SRS, 1, NotSerialized) {\r
+ CreateDWordField (Arg0, 0x05, IRQW)\r
+ Store (IRQW, PIRA)\r
+ }\r
}\r
\r
//\r
Name (_UID, 2)\r
\r
Method (_STA, 0, NotSerialized) { Return (PSTA (PIRB)) }\r
- Method (_DIS, 0, NotSerialized) { PDIS (PIRB) }\r
+ Method (_DIS, 0, NotSerialized) {\r
+ Or (PIRB, 0x80, PIRB) // set disable-bit\r
+ }\r
Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRB)) }\r
Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
- Method (_SRS, 1, NotSerialized) { PSRS (PIRB, Arg0) } \r
+ Method (_SRS, 1, NotSerialized) {\r
+ CreateDWordField (Arg0, 0x05, IRQW)\r
+ Store (IRQW, PIRB)\r
+ }\r
}\r
\r
//\r
Name (_UID, 3)\r
\r
Method (_STA, 0, NotSerialized) { Return (PSTA (PIRC)) }\r
- Method (_DIS, 0, NotSerialized) { PDIS (PIRC) }\r
+ Method (_DIS, 0, NotSerialized) {\r
+ Or (PIRC, 0x80, PIRC) // set disable-bit\r
+ }\r
Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRC)) }\r
Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
- Method (_SRS, 1, NotSerialized) { PSRS (PIRC, Arg0) } \r
+ Method (_SRS, 1, NotSerialized) {\r
+ CreateDWordField (Arg0, 0x05, IRQW)\r
+ Store (IRQW, PIRC)\r
+ }\r
}\r
\r
//\r
Name (_UID, 1)\r
\r
Method (_STA, 0, NotSerialized) { Return (PSTA (PIRD)) }\r
- Method (_DIS, 0, NotSerialized) { PDIS (PIRD) }\r
+ Method (_DIS, 0, NotSerialized) {\r
+ Or (PIRD, 0x80, PIRD) // set disable-bit\r
+ }\r
Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRD)) }\r
Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
- Method (_SRS, 1, NotSerialized) { PSRS (PIRD, Arg0) } \r
+ Method (_SRS, 1, NotSerialized) {\r
+ CreateDWordField (Arg0, 0x05, IRQW)\r
+ Store (IRQW, PIRD)\r
+ }\r
}\r
- \r
+\r
//\r
// Programmable Interrupt Controller (PIC)\r
//\r
}\r
\r
//\r
- // ISA DMA \r
+ // ISA DMA\r
//\r
Device (DMAC) {\r
- Name (_HID, EISAID ("PNP0200")) \r
+ Name (_HID, EISAID ("PNP0200"))\r
Name (_CRS, ResourceTemplate () {\r
IO (Decode16, 0x00, 0x00, 0, 0x10)\r
IO (Decode16, 0x81, 0x81, 0, 0x03)\r
IO (Decode16, 0x278, 0x278, 0x00, 0x08)\r
IO (Decode16, 0x370, 0x370, 0x00, 0x02)\r
IO (Decode16, 0x378, 0x378, 0x00, 0x08)\r
+ IO (Decode16, 0x402, 0x402, 0x00, 0x01) // QEMU debug console, should use FixedPcdGet16 (PcdDebugIoPort)\r
IO (Decode16, 0x440, 0x440, 0x00, 0x10)\r
IO (Decode16, 0x678, 0x678, 0x00, 0x08)\r
IO (Decode16, 0x778, 0x778, 0x00, 0x08)\r
- IO (Decode16, 0xafe0, 0xafe0, 0x00, 0x04) // QEMU GPE0 BLK\r
- IO (Decode16, 0xb000, 0xb000, 0x00, 0x40) // PMBLK1\r
- Memory32Fixed (ReadOnly, 0xFEC00000, 0x1000) // IO APIC\r
- Memory32Fixed (ReadOnly, 0xFEE00000, 0x1000)\r
+ IO (Decode16, 0xafe0, 0xafe0, 0x00, 0x04) // QEMU GPE0 BLK\r
+ IO (Decode16, 0xb000, 0xb000, 0x00, 0x40) // PMBLK1\r
+ Memory32Fixed (ReadOnly, 0xFEC00000, 0x1000) // IO APIC\r
+ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) // LAPIC\r
})\r
}\r
\r
//\r
// PS/2 Keyboard and PC/AT Enhanced Keyboard 101/102\r
//\r
- Device (PS2K) { \r
+ Device (PS2K) {\r
Name (_HID, EISAID ("PNP0303"))\r
Name (_CID, EISAID ("PNP030B"))\r
Name(_CRS,ResourceTemplate() {\r
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