/** @file\r
FACP Table\r
\r
- Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials are\r
licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include "Platform.h"\r
\r
EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {\r
- EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
- sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
- EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
- 0, // to make sum of entire table == 0\r
- EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field\r
- EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)\r
- EFI_ACPI_OEM_REVISION, // OEM revision number\r
- EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID\r
- EFI_ACPI_CREATOR_REVISION, // ASL compiler revision number\r
+ {\r
+ EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
+ sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
+ EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
+ 0, // to make sum of entire table == 0\r
+ {EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field\r
+ EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)\r
+ EFI_ACPI_OEM_REVISION, // OEM revision number\r
+ EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID\r
+ EFI_ACPI_CREATOR_REVISION // ASL compiler revision number\r
+ },\r
0, // Physical addesss of FACS\r
0, // Physical address of DSDT\r
INT_MODEL, // System Interrupt Model\r
ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI\r
ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI\r
S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state\r
- 0xE2, // PState control\r
+ 0, // PState control\r
PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk\r
PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk\r
PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk\r
GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk\r
GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk\r
GPE1_BASE, // offset in gpe model where gpe1 events start\r
- 0xE3, // _CST support\r
+ 0, // _CST support\r
P_LVL2_LAT, // worst case HW latency to enter/exit C2 state\r
P_LVL3_LAT, // worst case HW latency to enter/exit C3 state\r
FLUSH_SIZE, // Size of area read to flush caches\r
DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM\r
MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM\r
CENTURY, // index to century in RTC CMOS RAM\r
- 0x03, // Boot architecture flag\r
+ 0x00, // Boot architecture flag\r
0x00, // Boot architecture flag\r
RESERVED, // reserved\r
FLAG\r