#include "Platform.h"\r
#include "Cmos.h"\r
\r
-UINT8 mPhysMemAddressWidth;\r
+UINT8 mPhysMemAddressWidth;\r
\r
-STATIC UINT32 mS3AcpiReservedMemoryBase;\r
-STATIC UINT32 mS3AcpiReservedMemorySize;\r
+STATIC UINT32 mS3AcpiReservedMemoryBase;\r
+STATIC UINT32 mS3AcpiReservedMemorySize;\r
\r
-STATIC UINT16 mQ35TsegMbytes;\r
+STATIC UINT16 mQ35TsegMbytes;\r
\r
-BOOLEAN mQ35SmramAtDefaultSmbase = FALSE;\r
+BOOLEAN mQ35SmramAtDefaultSmbase = FALSE;\r
\r
VOID\r
Q35TsegMbytesInitialization (\r
VOID\r
)\r
{\r
- UINT16 ExtendedTsegMbytes;\r
- RETURN_STATUS PcdStatus;\r
+ UINT16 ExtendedTsegMbytes;\r
+ RETURN_STATUS PcdStatus;\r
\r
if (mHostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r
DEBUG ((\r
mQ35TsegMbytes = ExtendedTsegMbytes;\r
}\r
\r
-\r
UINT32\r
GetSystemMemorySizeBelow4gb (\r
VOID\r
)\r
{\r
- UINT8 Cmos0x34;\r
- UINT8 Cmos0x35;\r
+ UINT8 Cmos0x34;\r
+ UINT8 Cmos0x35;\r
\r
//\r
// CMOS 0x34/0x35 specifies the system memory above 16 MB.\r
// into the calculation to get the total memory size.\r
//\r
\r
- Cmos0x34 = (UINT8) CmosRead8 (0x34);\r
- Cmos0x35 = (UINT8) CmosRead8 (0x35);\r
+ Cmos0x34 = (UINT8)CmosRead8 (0x34);\r
+ Cmos0x35 = (UINT8)CmosRead8 (0x35);\r
\r
- return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r
+ return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r
}\r
\r
-\r
STATIC\r
UINT64\r
GetSystemMemorySizeAbove4gb (\r
)\r
{\r
- UINT32 Size;\r
- UINTN CmosIndex;\r
+ UINT32 Size;\r
+ UINTN CmosIndex;\r
\r
//\r
// CMOS 0x5b-0x5d specifies the system memory above 4GB MB.\r
\r
Size = 0;\r
for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {\r
- Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);\r
+ Size = (UINT32)(Size << 8) + (UINT32)CmosRead8 (CmosIndex);\r
}\r
\r
return LShiftU64 (Size, 16);\r
}\r
\r
-\r
/**\r
Return the highest address that DXE could possibly use, plus one.\r
**/\r
VOID\r
)\r
{\r
- UINT64 FirstNonAddress;\r
- UINT64 Pci64Base, Pci64Size;\r
- RETURN_STATUS PcdStatus;\r
+ UINT64 FirstNonAddress;\r
+ UINT64 Pci64Base, Pci64Size;\r
+ RETURN_STATUS PcdStatus;\r
\r
FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();\r
\r
// resources to 32-bit anyway. See DegradeResource() in\r
// "PciResourceSupport.c".\r
//\r
-#ifdef MDE_CPU_IA32\r
+ #ifdef MDE_CPU_IA32\r
if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
return FirstNonAddress;\r
}\r
-#endif\r
+\r
+ #endif\r
\r
//\r
// Otherwise, in order to calculate the highest address plus one, we must\r
\r
if (Pci64Size == 0) {\r
if (mBootMode != BOOT_ON_S3_RESUME) {\r
- DEBUG ((DEBUG_INFO, "%a: disabling 64-bit PCI host aperture\n",\r
- __FUNCTION__));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: disabling 64-bit PCI host aperture\n",\r
+ __FUNCTION__\r
+ ));\r
PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
\r
- DEBUG ((DEBUG_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r
- __FUNCTION__, Pci64Base, Pci64Size));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r
+ __FUNCTION__,\r
+ Pci64Base,\r
+ Pci64Size\r
+ ));\r
}\r
\r
//\r
return FirstNonAddress;\r
}\r
\r
-\r
/**\r
Initialize the mPhysMemAddressWidth variable, based on guest RAM size.\r
**/\r
VOID\r
)\r
{\r
- UINT64 FirstNonAddress;\r
+ UINT64 FirstNonAddress;\r
\r
//\r
// As guest-physical memory size grows, the permanent PEI RAM requirements\r
if (mPhysMemAddressWidth <= 36) {\r
mPhysMemAddressWidth = 36;\r
}\r
+\r
ASSERT (mPhysMemAddressWidth <= 48);\r
}\r
\r
-\r
/**\r
Calculate the cap for the permanent PEI memory.\r
**/\r
VOID\r
)\r
{\r
- BOOLEAN Page1GSupport;\r
- UINT32 RegEax;\r
- UINT32 RegEdx;\r
- UINT32 Pml4Entries;\r
- UINT32 PdpEntries;\r
- UINTN TotalPages;\r
+ BOOLEAN Page1GSupport;\r
+ UINT32 RegEax;\r
+ UINT32 RegEdx;\r
+ UINT32 Pml4Entries;\r
+ UINT32 PdpEntries;\r
+ UINTN TotalPages;\r
\r
//\r
// If DXE is 32-bit, then just return the traditional 64 MB cap.\r
//\r
-#ifdef MDE_CPU_IA32\r
+ #ifdef MDE_CPU_IA32\r
if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
return SIZE_64MB;\r
}\r
-#endif\r
+\r
+ #endif\r
\r
//\r
// Dependent on physical address width, PEI memory allocations can be\r
\r
if (mPhysMemAddressWidth <= 39) {\r
Pml4Entries = 1;\r
- PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r
+ PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r
ASSERT (PdpEntries <= 0x200);\r
} else {\r
Pml4Entries = 1 << (mPhysMemAddressWidth - 39);\r
}\r
\r
TotalPages = Page1GSupport ? Pml4Entries + 1 :\r
- (PdpEntries + 1) * Pml4Entries + 1;\r
+ (PdpEntries + 1) * Pml4Entries + 1;\r
ASSERT (TotalPages <= 0x40201);\r
\r
//\r
return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r
}\r
\r
-\r
/**\r
Publish PEI core memory\r
\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PHYSICAL_ADDRESS MemoryBase;\r
- UINT64 MemorySize;\r
- UINT32 LowerMemorySize;\r
- UINT32 PeiMemoryCap;\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS MemoryBase;\r
+ UINT64 MemorySize;\r
+ UINT32 LowerMemorySize;\r
+ UINT32 PeiMemoryCap;\r
\r
LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r
if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
//\r
if (mS3Supported) {\r
mS3AcpiReservedMemorySize = SIZE_512KB +\r
- mMaxCpuCount *\r
- PcdGet32 (PcdCpuApStackSize);\r
+ mMaxCpuCount *\r
+ PcdGet32 (PcdCpuApStackSize);\r
mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;\r
- LowerMemorySize = mS3AcpiReservedMemoryBase;\r
+ LowerMemorySize = mS3AcpiReservedMemoryBase;\r
}\r
\r
if (mBootMode == BOOT_ON_S3_RESUME) {\r
MemorySize = mS3AcpiReservedMemorySize;\r
} else {\r
PeiMemoryCap = GetPeiMemoryCap ();\r
- DEBUG ((DEBUG_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
- __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
+ __FUNCTION__,\r
+ mPhysMemAddressWidth,\r
+ PeiMemoryCap >> 10\r
+ ));\r
\r
//\r
// Determine the range of memory to use during PEI\r
// shouldn't overlap with that HOB.\r
//\r
MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?\r
- PcdGet32 (PcdOvmfDecompressionScratchEnd) :\r
- PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r
+ PcdGet32 (PcdOvmfDecompressionScratchEnd) :\r
+ PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r
MemorySize = LowerMemorySize - MemoryBase;\r
if (MemorySize > PeiMemoryCap) {\r
MemoryBase = LowerMemorySize - PeiMemoryCap;\r
//\r
// Publish this memory to the PEI Core\r
//\r
- Status = PublishSystemMemory(MemoryBase, MemorySize);\r
+ Status = PublishSystemMemory (MemoryBase, MemorySize);\r
ASSERT_EFI_ERROR (Status);\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Peform Memory Detection for QEMU / KVM\r
\r
VOID\r
)\r
{\r
- UINT64 LowerMemorySize;\r
- UINT64 UpperMemorySize;\r
- MTRR_SETTINGS MtrrSettings;\r
- EFI_STATUS Status;\r
+ UINT64 LowerMemorySize;\r
+ UINT64 UpperMemorySize;\r
+ MTRR_SETTINGS MtrrSettings;\r
+ EFI_STATUS Status;\r
\r
DEBUG ((DEBUG_INFO, "%a called\n", __FUNCTION__));\r
\r
AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r
\r
if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
- UINT32 TsegSize;\r
+ UINT32 TsegSize;\r
\r
TsegSize = mQ35TsegMbytes * SIZE_1MB;\r
AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);\r
- AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize,\r
- TRUE);\r
+ AddReservedMemoryBaseSizeHob (\r
+ LowerMemorySize - TsegSize,\r
+ TsegSize,\r
+ TRUE\r
+ );\r
} else {\r
AddMemoryRangeHob (BASE_1MB, LowerMemorySize);\r
}\r
//\r
// Set memory range from 640KB to 1MB to uncacheable\r
//\r
- Status = MtrrSetMemoryAttribute (BASE_512KB + BASE_128KB,\r
- BASE_1MB - (BASE_512KB + BASE_128KB), CacheUncacheable);\r
+ Status = MtrrSetMemoryAttribute (\r
+ BASE_512KB + BASE_128KB,\r
+ BASE_1MB - (BASE_512KB + BASE_128KB),\r
+ CacheUncacheable\r
+ );\r
ASSERT_EFI_ERROR (Status);\r
\r
//\r
// Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB as\r
// uncacheable\r
//\r
- Status = MtrrSetMemoryAttribute (LowerMemorySize,\r
- SIZE_4GB - LowerMemorySize, CacheUncacheable);\r
+ Status = MtrrSetMemoryAttribute (\r
+ LowerMemorySize,\r
+ SIZE_4GB - LowerMemorySize,\r
+ CacheUncacheable\r
+ );\r
ASSERT_EFI_ERROR (Status);\r
}\r
}\r
{\r
QemuInitializeRam ();\r
\r
- if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {\r
+ if (mS3Supported && (mBootMode != BOOT_ON_S3_RESUME)) {\r
//\r
// This is the memory range that will be used for PEI on S3 resume\r
//\r
EfiACPIMemoryNVS\r
);\r
\r
-#ifdef MDE_CPU_X64\r
+ #ifdef MDE_CPU_X64\r
//\r
// Reserve the initial page tables built by the reset vector code.\r
//\r
// resume, it must be reserved as ACPI NVS.\r
//\r
BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecPageTablesBase),\r
- (UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize),\r
+ (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecPageTablesBase),\r
+ (UINT64)(UINTN)PcdGet32 (PcdOvmfSecPageTablesSize),\r
EfiACPIMemoryNVS\r
);\r
-#endif\r
+ #endif\r
}\r
\r
if (mBootMode != BOOT_ON_S3_RESUME) {\r
// such that they would overlap the LockBox storage.\r
//\r
ZeroMem (\r
- (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r
- (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)\r
+ (VOID *)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),\r
+ (UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize)\r
);\r
BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r
- (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),\r
+ (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),\r
+ (UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize),\r
mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData\r
);\r
}\r
\r
if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
- UINT32 TsegSize;\r
+ UINT32 TsegSize;\r
\r
//\r
// Make sure the TSEG area that we reported as a reserved memory resource\r
//\r
TsegSize = mQ35TsegMbytes * SIZE_1MB;\r
BuildMemoryAllocationHob (\r
- GetSystemMemorySizeBelow4gb() - TsegSize,\r
+ GetSystemMemorySizeBelow4gb () - TsegSize,\r
TsegSize,\r
EfiReservedMemoryType\r
);\r
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