#include "LegacyBiosInterface.h"\r
#include <IndustryStandard/Pci30.h>\r
\r
-#define PCI_START_ADDRESS(x) (((x) + 0x7ff) & ~0x7ff)\r
+#define PCI_START_ADDRESS(x) (((x) + 0x7ff) & ~0x7ff)\r
\r
#define MAX_BRIDGE_INDEX 0x20\r
typedef struct {\r
- UINTN PciSegment;\r
- UINTN PciBus;\r
- UINTN PciDevice;\r
- UINTN PciFunction;\r
- UINT8 PrimaryBus;\r
- UINT8 SecondaryBus;\r
- UINT8 SubordinateBus;\r
+ UINTN PciSegment;\r
+ UINTN PciBus;\r
+ UINTN PciDevice;\r
+ UINTN PciFunction;\r
+ UINT8 PrimaryBus;\r
+ UINT8 SecondaryBus;\r
+ UINT8 SubordinateBus;\r
} BRIDGE_TABLE;\r
\r
-#define ROM_MAX_ENTRIES 24\r
-BRIDGE_TABLE Bridges[MAX_BRIDGE_INDEX];\r
-UINTN SortedBridgeIndex[MAX_BRIDGE_INDEX];\r
-UINTN NumberOfBridges;\r
+#define ROM_MAX_ENTRIES 24\r
+BRIDGE_TABLE Bridges[MAX_BRIDGE_INDEX];\r
+UINTN SortedBridgeIndex[MAX_BRIDGE_INDEX];\r
+UINTN NumberOfBridges;\r
LEGACY_PNP_EXPANSION_HEADER *mBasePnpPtr;\r
-UINT16 mBbsRomSegment;\r
-UINTN mHandleCount;\r
-EFI_HANDLE mVgaHandle;\r
-BOOLEAN mIgnoreBbsUpdateFlag;\r
-BOOLEAN mVgaInstallationInProgress = FALSE;\r
-UINT32 mRomCount = 0x00;\r
-ROM_INSTANCE_ENTRY mRomEntry[ROM_MAX_ENTRIES];\r
-EDKII_IOMMU_PROTOCOL *mIoMmu;\r
+UINT16 mBbsRomSegment;\r
+UINTN mHandleCount;\r
+EFI_HANDLE mVgaHandle;\r
+BOOLEAN mIgnoreBbsUpdateFlag;\r
+BOOLEAN mVgaInstallationInProgress = FALSE;\r
+UINT32 mRomCount = 0x00;\r
+ROM_INSTANCE_ENTRY mRomEntry[ROM_MAX_ENTRIES];\r
+EDKII_IOMMU_PROTOCOL *mIoMmu;\r
\r
/**\r
Query shadowed legacy ROM parameters registered by RomShadow() previously.\r
**/\r
EFI_STATUS\r
GetShadowedRomParameters (\r
- IN EFI_HANDLE PciHandle,\r
- OUT UINT8 *DiskStart OPTIONAL,\r
- OUT UINT8 *DiskEnd OPTIONAL,\r
- OUT VOID **RomShadowAddress OPTIONAL,\r
- OUT UINTN *ShadowedSize OPTIONAL\r
+ IN EFI_HANDLE PciHandle,\r
+ OUT UINT8 *DiskStart OPTIONAL,\r
+ OUT UINT8 *DiskEnd OPTIONAL,\r
+ OUT VOID **RomShadowAddress OPTIONAL,\r
+ OUT UINTN *ShadowedSize OPTIONAL\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- UINTN Index;\r
- UINTN PciSegment;\r
- UINTN PciBus;\r
- UINTN PciDevice;\r
- UINTN PciFunction;\r
+ EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ UINTN Index;\r
+ UINTN PciSegment;\r
+ UINTN PciBus;\r
+ UINTN PciDevice;\r
+ UINTN PciFunction;\r
\r
//\r
// Get the PCI I/O Protocol on PciHandle\r
Status = gBS->HandleProtocol (\r
PciHandle,\r
&gEfiPciIoProtocolGuid,\r
- (VOID **) &PciIo\r
+ (VOID **)&PciIo\r
);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
&PciFunction\r
);\r
\r
- for(Index = 0; Index < mRomCount; Index++) {\r
+ for (Index = 0; Index < mRomCount; Index++) {\r
if ((mRomEntry[Index].PciSegment == PciSegment) &&\r
(mRomEntry[Index].PciBus == PciBus) &&\r
(mRomEntry[Index].PciDevice == PciDevice) &&\r
- (mRomEntry[Index].PciFunction == PciFunction)) {\r
+ (mRomEntry[Index].PciFunction == PciFunction))\r
+ {\r
break;\r
}\r
}\r
**/\r
EFI_STATUS\r
RomShadow (\r
- IN EFI_HANDLE PciHandle,\r
- IN UINT32 ShadowAddress,\r
- IN UINT32 ShadowedSize,\r
- IN UINT8 DiskStart,\r
- IN UINT8 DiskEnd\r
+ IN EFI_HANDLE PciHandle,\r
+ IN UINT32 ShadowAddress,\r
+ IN UINT32 ShadowedSize,\r
+ IN UINT8 DiskStart,\r
+ IN UINT8 DiskEnd\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
+ EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
\r
//\r
// See if there is room to register another option ROM\r
if (mRomCount >= ROM_MAX_ENTRIES) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
//\r
// Get the PCI I/O Protocol on PciHandle\r
//\r
Status = gBS->HandleProtocol (\r
PciHandle,\r
&gEfiPciIoProtocolGuid,\r
- (VOID **) &PciIo\r
+ (VOID **)&PciIo\r
);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Get the location of the PCI device\r
//\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Return EFI_SUCCESS if PciHandle has had a legacy BIOS ROM shadowed. This\r
information represents every call to RomShadow ()\r
**/\r
EFI_STATUS\r
IsLegacyRom (\r
- IN EFI_HANDLE PciHandle\r
+ IN EFI_HANDLE PciHandle\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- UINTN Index;\r
- UINTN Segment;\r
- UINTN Bus;\r
- UINTN Device;\r
- UINTN Function;\r
+ EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ UINTN Index;\r
+ UINTN Segment;\r
+ UINTN Bus;\r
+ UINTN Device;\r
+ UINTN Function;\r
\r
//\r
// Get the PCI I/O Protocol on PciHandle\r
Status = gBS->HandleProtocol (\r
PciHandle,\r
&gEfiPciIoProtocolGuid,\r
- (VOID **) &PciIo\r
+ (VOID **)&PciIo\r
);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Get the location of the PCI device\r
//\r
// See if the option ROM from PciHandle has been previously posted\r
//\r
for (Index = 0; Index < mRomCount; Index++) {\r
- if (mRomEntry[Index].PciSegment == Segment &&\r
- mRomEntry[Index].PciBus == Bus &&\r
- mRomEntry[Index].PciDevice == Device &&\r
- mRomEntry[Index].PciFunction == Function\r
- ) {\r
+ if ((mRomEntry[Index].PciSegment == Segment) &&\r
+ (mRomEntry[Index].PciBus == Bus) &&\r
+ (mRomEntry[Index].PciDevice == Device) &&\r
+ (mRomEntry[Index].PciFunction == Function)\r
+ )\r
+ {\r
return EFI_SUCCESS;\r
}\r
}\r
**/\r
EFI_STATUS\r
GetPciLegacyRom (\r
- IN UINT16 Csm16Revision,\r
- IN UINT16 VendorId,\r
- IN UINT16 DeviceId,\r
- IN OUT VOID **Rom,\r
- IN OUT UINTN *ImageSize,\r
- OUT UINTN *MaxRuntimeImageLength OPTIONAL,\r
- OUT UINT8 *OpRomRevision OPTIONAL,\r
- OUT VOID **ConfigUtilityCodeHeader OPTIONAL\r
+ IN UINT16 Csm16Revision,\r
+ IN UINT16 VendorId,\r
+ IN UINT16 DeviceId,\r
+ IN OUT VOID **Rom,\r
+ IN OUT UINTN *ImageSize,\r
+ OUT UINTN *MaxRuntimeImageLength OPTIONAL,\r
+ OUT UINT8 *OpRomRevision OPTIONAL,\r
+ OUT VOID **ConfigUtilityCodeHeader OPTIONAL\r
)\r
{\r
BOOLEAN Match;\r
VOID *BackupImage;\r
VOID *BestImage;\r
\r
-\r
if (*ImageSize < sizeof (EFI_PCI_ROM_HEADER)) {\r
return EFI_NOT_FOUND;\r
}\r
BackupImage = NULL;\r
RomHeader.Raw = *Rom;\r
while (RomHeader.Generic->Signature == PCI_EXPANSION_ROM_HEADER_SIGNATURE) {\r
- if (RomHeader.Generic->PcirOffset == 0 ||\r
- (RomHeader.Generic->PcirOffset & 3) !=0 ||\r
- *ImageSize < RomHeader.Raw - (UINT8 *) *Rom + RomHeader.Generic->PcirOffset + sizeof (PCI_DATA_STRUCTURE)) {\r
+ if ((RomHeader.Generic->PcirOffset == 0) ||\r
+ ((RomHeader.Generic->PcirOffset & 3) != 0) ||\r
+ (*ImageSize < RomHeader.Raw - (UINT8 *)*Rom + RomHeader.Generic->PcirOffset + sizeof (PCI_DATA_STRUCTURE)))\r
+ {\r
break;\r
}\r
\r
- Pcir = (PCI_3_0_DATA_STRUCTURE *) (RomHeader.Raw + RomHeader.Generic->PcirOffset);\r
+ Pcir = (PCI_3_0_DATA_STRUCTURE *)(RomHeader.Raw + RomHeader.Generic->PcirOffset);\r
//\r
// Check signature in the PCI Data Structure.\r
//\r
if (Pcir->DeviceId == DeviceId) {\r
Match = TRUE;\r
} else if ((Pcir->Revision >= 3) && (Pcir->DeviceListOffset != 0)) {\r
- DeviceIdList = (UINT16 *)(((UINT8 *) Pcir) + Pcir->DeviceListOffset);\r
+ DeviceIdList = (UINT16 *)(((UINT8 *)Pcir) + Pcir->DeviceListOffset);\r
//\r
// Checking the device list\r
//\r
Match = TRUE;\r
break;\r
}\r
- DeviceIdList ++;\r
+\r
+ DeviceIdList++;\r
}\r
}\r
}\r
// case 1.1: meets OpRom 3.0\r
// Perfect!!!\r
//\r
- BestImage = RomHeader.Raw;\r
+ BestImage = RomHeader.Raw;\r
break;\r
} else {\r
//\r
// case 2.2: meets OpRom 2.x\r
// Perfect!!!\r
//\r
- BestImage = RomHeader.Raw;\r
+ BestImage = RomHeader.Raw;\r
break;\r
}\r
}\r
if (BackupImage == NULL) {\r
return EFI_NOT_FOUND;\r
}\r
+\r
//\r
// The versions of CSM16 and OpRom don't match exactly\r
//\r
BestImage = BackupImage;\r
}\r
+\r
RomHeader.Raw = BestImage;\r
- Pcir = (PCI_3_0_DATA_STRUCTURE *) (RomHeader.Raw + RomHeader.Generic->PcirOffset);\r
- *Rom = BestImage;\r
- *ImageSize = Pcir->ImageLength * 512;\r
+ Pcir = (PCI_3_0_DATA_STRUCTURE *)(RomHeader.Raw + RomHeader.Generic->PcirOffset);\r
+ *Rom = BestImage;\r
+ *ImageSize = Pcir->ImageLength * 512;\r
\r
if (MaxRuntimeImageLength != NULL) {\r
if (Pcir->Revision < 3) {\r
**/\r
EFI_STATUS\r
CreateBridgeTable (\r
- IN EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable,\r
- IN UINTN RoutingTableEntries\r
+ IN EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable,\r
+ IN UINTN RoutingTableEntries\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN HandleCount;\r
- EFI_HANDLE *HandleBuffer;\r
- UINTN BridgeIndex;\r
- UINTN Index;\r
- UINTN Index1;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- PCI_TYPE01 PciConfigHeader;\r
- BRIDGE_TABLE SlotBridges[MAX_BRIDGE_INDEX];\r
- UINTN SlotBridgeIndex;\r
-\r
- BridgeIndex = 0x00;\r
+ EFI_STATUS Status;\r
+ UINTN HandleCount;\r
+ EFI_HANDLE *HandleBuffer;\r
+ UINTN BridgeIndex;\r
+ UINTN Index;\r
+ UINTN Index1;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ PCI_TYPE01 PciConfigHeader;\r
+ BRIDGE_TABLE SlotBridges[MAX_BRIDGE_INDEX];\r
+ UINTN SlotBridgeIndex;\r
+\r
+ BridgeIndex = 0x00;\r
SlotBridgeIndex = 0x00;\r
\r
//\r
if (EFI_ERROR (Status)) {\r
return EFI_NOT_FOUND;\r
}\r
+\r
for (Index = 0; Index < HandleCount; Index++) {\r
Status = gBS->HandleProtocol (\r
HandleBuffer[Index],\r
&gEfiPciIoProtocolGuid,\r
- (VOID **) &PciIo\r
+ (VOID **)&PciIo\r
);\r
if (EFI_ERROR (Status)) {\r
continue;\r
&Bridges[BridgeIndex].PciFunction\r
);\r
\r
- Bridges[BridgeIndex].PrimaryBus = PciConfigHeader.Bridge.PrimaryBus;\r
+ Bridges[BridgeIndex].PrimaryBus = PciConfigHeader.Bridge.PrimaryBus;\r
\r
- Bridges[BridgeIndex].SecondaryBus = PciConfigHeader.Bridge.SecondaryBus;\r
+ Bridges[BridgeIndex].SecondaryBus = PciConfigHeader.Bridge.SecondaryBus;\r
\r
Bridges[BridgeIndex].SubordinateBus = PciConfigHeader.Bridge.SubordinateBus;\r
\r
- for (Index1 = 0; Index1 < RoutingTableEntries; Index1++){\r
+ for (Index1 = 0; Index1 < RoutingTableEntries; Index1++) {\r
//\r
// Test whether we have found the Bridge in the slot, must be the one that directly interfaced to the board\r
// Once we find one, store it in the SlotBridges[]\r
//\r
- if ((RoutingTable[Index1].Slot != 0) && (Bridges[BridgeIndex].PrimaryBus == RoutingTable[Index1].Bus)\r
- && ((Bridges[BridgeIndex].PciDevice << 3) == RoutingTable[Index1].Device)) {\r
+ if ( (RoutingTable[Index1].Slot != 0) && (Bridges[BridgeIndex].PrimaryBus == RoutingTable[Index1].Bus)\r
+ && ((Bridges[BridgeIndex].PciDevice << 3) == RoutingTable[Index1].Device))\r
+ {\r
CopyMem (&SlotBridges[SlotBridgeIndex], &Bridges[BridgeIndex], sizeof (BRIDGE_TABLE));\r
SlotBridgeIndex++;\r
\r
//\r
// Pack up Bridges by removing those useless ones\r
//\r
- for (Index = 0; Index < BridgeIndex;){\r
+ for (Index = 0; Index < BridgeIndex;) {\r
for (Index1 = 0; Index1 < SlotBridgeIndex; Index1++) {\r
if (((Bridges[Index].PciBus == SlotBridges[Index1].PrimaryBus) && (Bridges[Index].PciDevice == SlotBridges[Index1].PciDevice)) ||\r
- ((Bridges[Index].PciBus >= SlotBridges[Index1].SecondaryBus) && (Bridges[Index].PciBus <= SlotBridges[Index1].SubordinateBus))) {\r
+ ((Bridges[Index].PciBus >= SlotBridges[Index1].SecondaryBus) && (Bridges[Index].PciBus <= SlotBridges[Index1].SubordinateBus)))\r
+ {\r
//\r
// We have found one that meets our criteria\r
//\r
// This one doesn't meet criteria, pack it\r
//\r
if (Index1 >= SlotBridgeIndex) {\r
- for (Index1 = Index; BridgeIndex > 1 && Index1 < BridgeIndex - 1 ; Index1++) {\r
+ for (Index1 = Index; BridgeIndex > 1 && Index1 < BridgeIndex - 1; Index1++) {\r
CopyMem (&Bridges[Index1], &Bridges[Index1 + 1], sizeof (BRIDGE_TABLE));\r
}\r
\r
\r
if ((Bridges[Index].SecondaryBus == Bridges[Index1].SecondaryBus) &&\r
(Bridges[Index].SubordinateBus > Bridges[Index1].SubordinateBus)\r
- ) {\r
+ )\r
+ {\r
SortedBridgeIndex[Index] = Index1;\r
SortedBridgeIndex[Index1] = Index;\r
}\r
}\r
}\r
}\r
+\r
FreePool (HandleBuffer);\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Find base Bridge for device.\r
\r
**/\r
EFI_STATUS\r
GetBaseBus (\r
- IN LEGACY_BIOS_INSTANCE *Private,\r
- IN UINTN PciBus,\r
- IN UINTN PciDevice,\r
- IN EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable,\r
- IN UINTN RoutingTableEntries\r
+ IN LEGACY_BIOS_INSTANCE *Private,\r
+ IN UINTN PciBus,\r
+ IN UINTN PciDevice,\r
+ IN EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable,\r
+ IN UINTN RoutingTableEntries\r
)\r
{\r
- UINTN Index;\r
+ UINTN Index;\r
+\r
for (Index = 0; Index < RoutingTableEntries; Index++) {\r
if ((RoutingTable[Index].Bus == PciBus) && (RoutingTable[Index].Device == (PciDevice << 3))) {\r
return EFI_SUCCESS;\r
**/\r
EFI_STATUS\r
TranslateBusPirq (\r
- IN LEGACY_BIOS_INSTANCE *Private,\r
- IN OUT UINTN *PciBus,\r
- IN OUT UINTN *PciDevice,\r
- IN OUT UINTN *PciFunction,\r
- IN OUT UINT8 *PirqIndex\r
+ IN LEGACY_BIOS_INSTANCE *Private,\r
+ IN OUT UINTN *PciBus,\r
+ IN OUT UINTN *PciDevice,\r
+ IN OUT UINTN *PciFunction,\r
+ IN OUT UINT8 *PirqIndex\r
)\r
{\r
/*\r
Rotate (B,C,D,A) by 1 giving C,D,A,B. Translated PIRQ is C.\r
\r
*/\r
- UINTN LocalBus;\r
- UINTN LocalDevice;\r
- UINTN BaseBus;\r
- UINTN BaseDevice;\r
- UINTN BaseFunction;\r
- UINT8 LocalPirqIndex;\r
- BOOLEAN BaseIndexFlag;\r
- UINTN BridgeIndex;\r
- UINTN SBridgeIndex;\r
- BaseIndexFlag = FALSE;\r
- BridgeIndex = 0x00;\r
-\r
- LocalPirqIndex = *PirqIndex;\r
- LocalBus = *PciBus;\r
- LocalDevice = *PciDevice;\r
- BaseBus = *PciBus;\r
- BaseDevice = *PciDevice;\r
- BaseFunction = *PciFunction;\r
+ UINTN LocalBus;\r
+ UINTN LocalDevice;\r
+ UINTN BaseBus;\r
+ UINTN BaseDevice;\r
+ UINTN BaseFunction;\r
+ UINT8 LocalPirqIndex;\r
+ BOOLEAN BaseIndexFlag;\r
+ UINTN BridgeIndex;\r
+ UINTN SBridgeIndex;\r
+\r
+ BaseIndexFlag = FALSE;\r
+ BridgeIndex = 0x00;\r
+\r
+ LocalPirqIndex = *PirqIndex;\r
+ LocalBus = *PciBus;\r
+ LocalDevice = *PciDevice;\r
+ BaseBus = *PciBus;\r
+ BaseDevice = *PciDevice;\r
+ BaseFunction = *PciFunction;\r
\r
//\r
// LocalPirqIndex list PIRQs in rotated fashion\r
BaseFunction = Bridges[SBridgeIndex].PciFunction;\r
BaseIndexFlag = TRUE;\r
} else {\r
- LocalPirqIndex = (UINT8) ((LocalPirqIndex + (UINT8)Bridges[SBridgeIndex].PciDevice)%4);\r
+ LocalPirqIndex = (UINT8)((LocalPirqIndex + (UINT8)Bridges[SBridgeIndex].PciDevice)%4);\r
}\r
\r
//\r
// Check if at device. If not get new PCI location & PIRQ\r
//\r
- if (Bridges[SBridgeIndex].SecondaryBus == (UINT8) LocalBus) {\r
+ if (Bridges[SBridgeIndex].SecondaryBus == (UINT8)LocalBus) {\r
//\r
// Translate PIRQ\r
//\r
- LocalPirqIndex = (UINT8) ((LocalPirqIndex + (UINT8) (LocalDevice)) % 4);\r
+ LocalPirqIndex = (UINT8)((LocalPirqIndex + (UINT8)(LocalDevice)) % 4);\r
break;\r
}\r
}\r
//\r
// In case we fail to find the Bridge just above us, this is some potential error and we want to warn the user\r
//\r
- if(BridgeIndex >= NumberOfBridges){\r
+ if (BridgeIndex >= NumberOfBridges) {\r
DEBUG ((DEBUG_ERROR, "Cannot Find IRQ Routing for Bus %d, Device %d, Function %d\n", *PciBus, *PciDevice, *PciFunction));\r
}\r
\r
- *PirqIndex = LocalPirqIndex;\r
- *PciBus = BaseBus;\r
- *PciDevice = BaseDevice;\r
- *PciFunction = BaseFunction;\r
+ *PirqIndex = LocalPirqIndex;\r
+ *PciBus = BaseBus;\r
+ *PciDevice = BaseDevice;\r
+ *PciFunction = BaseFunction;\r
\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Copy the $PIR table as required.\r
\r
**/\r
VOID\r
CopyPirqTable (\r
- IN LEGACY_BIOS_INSTANCE *Private,\r
- IN EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable,\r
- IN UINTN RoutingTableEntries,\r
- IN EFI_LEGACY_PIRQ_TABLE_HEADER *PirqTable,\r
- IN UINTN PirqTableSize\r
+ IN LEGACY_BIOS_INSTANCE *Private,\r
+ IN EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable,\r
+ IN UINTN RoutingTableEntries,\r
+ IN EFI_LEGACY_PIRQ_TABLE_HEADER *PirqTable,\r
+ IN UINTN PirqTableSize\r
)\r
{\r
- EFI_IA32_REGISTER_SET Regs;\r
- UINT32 Granularity;\r
+ EFI_IA32_REGISTER_SET Regs;\r
+ UINT32 Granularity;\r
\r
//\r
// Copy $PIR table, if it exists.\r
//\r
if (PirqTable != NULL) {\r
Private->LegacyRegion->UnLock (\r
- Private->LegacyRegion,\r
- 0xE0000,\r
- 0x20000,\r
- &Granularity\r
- );\r
-\r
- Private->InternalIrqRoutingTable = RoutingTable;\r
- Private->NumberIrqRoutingEntries = (UINT16) (RoutingTableEntries);\r
+ Private->LegacyRegion,\r
+ 0xE0000,\r
+ 0x20000,\r
+ &Granularity\r
+ );\r
+\r
+ Private->InternalIrqRoutingTable = RoutingTable;\r
+ Private->NumberIrqRoutingEntries = (UINT16)(RoutingTableEntries);\r
ZeroMem (&Regs, sizeof (EFI_IA32_REGISTER_SET));\r
\r
Regs.X.AX = Legacy16GetTableAddress;\r
- Regs.X.CX = (UINT16) PirqTableSize;\r
+ Regs.X.CX = (UINT16)PirqTableSize;\r
//\r
// Allocate at F segment according to PCI IRQ Routing Table Specification\r
//\r
- Regs.X.BX = (UINT16) 0x1;\r
+ Regs.X.BX = (UINT16)0x1;\r
//\r
// 16-byte boundary alignment requirement according to\r
// PCI IRQ Routing Table Specification\r
//\r
Regs.X.DX = 0x10;\r
Private->LegacyBios.FarCall86 (\r
- &Private->LegacyBios,\r
- Private->Legacy16CallSegment,\r
- Private->Legacy16CallOffset,\r
- &Regs,\r
- NULL,\r
- 0\r
- );\r
+ &Private->LegacyBios,\r
+ Private->Legacy16CallSegment,\r
+ Private->Legacy16CallOffset,\r
+ &Regs,\r
+ NULL,\r
+ 0\r
+ );\r
\r
- Private->Legacy16Table->IrqRoutingTablePointer = (UINT32) (Regs.X.DS * 16 + Regs.X.BX);\r
+ Private->Legacy16Table->IrqRoutingTablePointer = (UINT32)(Regs.X.DS * 16 + Regs.X.BX);\r
if (Regs.X.AX != 0) {\r
DEBUG ((DEBUG_ERROR, "PIRQ table length insufficient - %x\n", PirqTableSize));\r
} else {\r
DEBUG ((DEBUG_INFO, "PIRQ table in legacy region - %x\n", Private->Legacy16Table->IrqRoutingTablePointer));\r
Private->Legacy16Table->IrqRoutingTableLength = (UINT32)PirqTableSize;\r
CopyMem (\r
- (VOID *) (UINTN)Private->Legacy16Table->IrqRoutingTablePointer,\r
+ (VOID *)(UINTN)Private->Legacy16Table->IrqRoutingTablePointer,\r
PirqTable,\r
PirqTableSize\r
);\r
**/\r
VOID\r
InstallLegacyIrqHandler (\r
- IN LEGACY_BIOS_INSTANCE *Private,\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT8 PciIrq,\r
- IN PCI_TYPE00 *PciConfigHeader\r
+ IN LEGACY_BIOS_INSTANCE *Private,\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT8 PciIrq,\r
+ IN PCI_TYPE00 *PciConfigHeader\r
)\r
{\r
EFI_IA32_REGISTER_SET Regs;\r
NULL\r
);\r
\r
- LegMask = (UINT16) (LegMask | (UINT16) (1 << PciIrq));\r
+ LegMask = (UINT16)(LegMask | (UINT16)(1 << PciIrq));\r
\r
Legacy8259->SetMask (\r
Legacy8259,\r
);\r
\r
PciIo->GetLocation (\r
- PciIo,\r
- &PciSegment,\r
- &PciBus,\r
- &PciDevice,\r
- &PciFunction\r
- );\r
- Private->IntThunk->PciHandler.PciBus = (UINT8) PciBus;\r
- Private->IntThunk->PciHandler.PciDeviceFun = (UINT8) ((PciDevice << 3) + PciFunction);\r
- Private->IntThunk->PciHandler.PciSegment = (UINT8) PciSegment;\r
- Private->IntThunk->PciHandler.PciClass = PciConfigHeader->Hdr.ClassCode[2];\r
- Private->IntThunk->PciHandler.PciSubclass = PciConfigHeader->Hdr.ClassCode[1];\r
- Private->IntThunk->PciHandler.PciInterface = PciConfigHeader->Hdr.ClassCode[0];\r
+ PciIo,\r
+ &PciSegment,\r
+ &PciBus,\r
+ &PciDevice,\r
+ &PciFunction\r
+ );\r
+ Private->IntThunk->PciHandler.PciBus = (UINT8)PciBus;\r
+ Private->IntThunk->PciHandler.PciDeviceFun = (UINT8)((PciDevice << 3) + PciFunction);\r
+ Private->IntThunk->PciHandler.PciSegment = (UINT8)PciSegment;\r
+ Private->IntThunk->PciHandler.PciClass = PciConfigHeader->Hdr.ClassCode[2];\r
+ Private->IntThunk->PciHandler.PciSubclass = PciConfigHeader->Hdr.ClassCode[1];\r
+ Private->IntThunk->PciHandler.PciInterface = PciConfigHeader->Hdr.ClassCode[0];\r
\r
//\r
// Use native mode base address registers in two cases:\r
// in native mode OR\r
// 2. PCI device Sub Class Code is not IDE\r
//\r
- Private->IntThunk->PciHandler.PrimaryBusMaster = (UINT16)(PciConfigHeader->Device.Bar[4] & 0xfffc);\r
+ Private->IntThunk->PciHandler.PrimaryBusMaster = (UINT16)(PciConfigHeader->Device.Bar[4] & 0xfffc);\r
if (((PciConfigHeader->Hdr.ClassCode[0] & 0x01) != 0) || (PciConfigHeader->Hdr.ClassCode[1] != PCI_CLASS_MASS_STORAGE_IDE)) {\r
- Private->IntThunk->PciHandler.PrimaryIrq = PciIrq;\r
- Private->IntThunk->PciHandler.PrimaryBase = (UINT16) (PciConfigHeader->Device.Bar[0] & 0xfffc);\r
- Private->IntThunk->PciHandler.PrimaryControl = (UINT16) ((PciConfigHeader->Device.Bar[1] & 0xfffc) + 2);\r
+ Private->IntThunk->PciHandler.PrimaryIrq = PciIrq;\r
+ Private->IntThunk->PciHandler.PrimaryBase = (UINT16)(PciConfigHeader->Device.Bar[0] & 0xfffc);\r
+ Private->IntThunk->PciHandler.PrimaryControl = (UINT16)((PciConfigHeader->Device.Bar[1] & 0xfffc) + 2);\r
} else {\r
- Private->IntThunk->PciHandler.PrimaryIrq = 14;\r
- Private->IntThunk->PciHandler.PrimaryBase = 0x1f0;\r
- Private->IntThunk->PciHandler.PrimaryControl = 0x3f6;\r
+ Private->IntThunk->PciHandler.PrimaryIrq = 14;\r
+ Private->IntThunk->PciHandler.PrimaryBase = 0x1f0;\r
+ Private->IntThunk->PciHandler.PrimaryControl = 0x3f6;\r
}\r
+\r
//\r
// Secondary controller data\r
//\r
if (Private->IntThunk->PciHandler.PrimaryBusMaster != 0) {\r
- Private->IntThunk->PciHandler.SecondaryBusMaster = (UINT16) ((PciConfigHeader->Device.Bar[4] & 0xfffc) + 8);\r
- PrimaryMaster = (UINT16) (Private->IntThunk->PciHandler.PrimaryBusMaster + 2);\r
- SecondaryMaster = (UINT16) (Private->IntThunk->PciHandler.SecondaryBusMaster + 2);\r
+ Private->IntThunk->PciHandler.SecondaryBusMaster = (UINT16)((PciConfigHeader->Device.Bar[4] & 0xfffc) + 8);\r
+ PrimaryMaster = (UINT16)(Private->IntThunk->PciHandler.PrimaryBusMaster + 2);\r
+ SecondaryMaster = (UINT16)(Private->IntThunk->PciHandler.SecondaryBusMaster + 2);\r
\r
//\r
// Clear pending interrupts in Bus Master registers\r
//\r
IoWrite16 (PrimaryMaster, 0x04);\r
IoWrite16 (SecondaryMaster, 0x04);\r
-\r
}\r
\r
//\r
// 2. PCI device Sub Class Code is not IDE\r
//\r
if (((PciConfigHeader->Hdr.ClassCode[0] & 0x04) != 0) || (PciConfigHeader->Hdr.ClassCode[1] != PCI_CLASS_MASS_STORAGE_IDE)) {\r
- Private->IntThunk->PciHandler.SecondaryIrq = PciIrq;\r
- Private->IntThunk->PciHandler.SecondaryBase = (UINT16) (PciConfigHeader->Device.Bar[2] & 0xfffc);\r
- Private->IntThunk->PciHandler.SecondaryControl = (UINT16) ((PciConfigHeader->Device.Bar[3] & 0xfffc) + 2);\r
+ Private->IntThunk->PciHandler.SecondaryIrq = PciIrq;\r
+ Private->IntThunk->PciHandler.SecondaryBase = (UINT16)(PciConfigHeader->Device.Bar[2] & 0xfffc);\r
+ Private->IntThunk->PciHandler.SecondaryControl = (UINT16)((PciConfigHeader->Device.Bar[3] & 0xfffc) + 2);\r
} else {\r
-\r
- Private->IntThunk->PciHandler.SecondaryIrq = 15;\r
- Private->IntThunk->PciHandler.SecondaryBase = 0x170;\r
- Private->IntThunk->PciHandler.SecondaryControl = 0x376;\r
+ Private->IntThunk->PciHandler.SecondaryIrq = 15;\r
+ Private->IntThunk->PciHandler.SecondaryBase = 0x170;\r
+ Private->IntThunk->PciHandler.SecondaryControl = 0x376;\r
}\r
\r
//\r
);\r
\r
Regs.X.AX = Legacy16InstallPciHandler;\r
- TempData = (UINTN) &Private->IntThunk->PciHandler;\r
- Regs.X.ES = EFI_SEGMENT ((UINT32) TempData);\r
- Regs.X.BX = EFI_OFFSET ((UINT32) TempData);\r
+ TempData = (UINTN)&Private->IntThunk->PciHandler;\r
+ Regs.X.ES = EFI_SEGMENT ((UINT32)TempData);\r
+ Regs.X.BX = EFI_OFFSET ((UINT32)TempData);\r
\r
DumpPciHandle (&Private->IntThunk->PciHandler);\r
\r
Private->LegacyBios.FarCall86 (\r
- &Private->LegacyBios,\r
- Private->Legacy16CallSegment,\r
- Private->Legacy16CallOffset,\r
- &Regs,\r
- NULL,\r
- 0\r
- );\r
+ &Private->LegacyBios,\r
+ Private->Legacy16CallSegment,\r
+ Private->Legacy16CallOffset,\r
+ &Regs,\r
+ NULL,\r
+ 0\r
+ );\r
\r
Private->Cpu->FlushDataCache (Private->Cpu, 0xE0000, 0x20000, EfiCpuFlushTypeWriteBackInvalidate);\r
Private->LegacyRegion->Lock (\r
0x20000,\r
&Granularity\r
);\r
-\r
}\r
\r
-\r
/**\r
Program the interrupt routing register in all the PCI devices. On a PC AT system\r
this register contains the 8259 IRQ vector that matches its PCI interrupt.\r
**/\r
EFI_STATUS\r
PciProgramAllInterruptLineRegisters (\r
- IN LEGACY_BIOS_INSTANCE *Private\r
+ IN LEGACY_BIOS_INSTANCE *Private\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- EFI_LEGACY_8259_PROTOCOL *Legacy8259;\r
- EFI_LEGACY_INTERRUPT_PROTOCOL *LegacyInterrupt;\r
- EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *LegacyBiosPlatform;\r
- UINT8 InterruptPin;\r
- UINTN Index;\r
- UINTN HandleCount;\r
- EFI_HANDLE *HandleBuffer;\r
- UINTN MassStorageHandleCount;\r
- EFI_HANDLE *MassStorageHandleBuffer;\r
- UINTN MassStorageHandleIndex;\r
- UINT8 PciIrq;\r
- UINT16 Command;\r
- UINTN PciSegment;\r
- UINTN PciBus;\r
- UINTN PciDevice;\r
- UINTN PciFunction;\r
- EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable;\r
- UINTN RoutingTableEntries;\r
- UINT16 LegMask;\r
- UINT16 LegEdgeLevel;\r
- PCI_TYPE00 PciConfigHeader;\r
- EFI_LEGACY_PIRQ_TABLE_HEADER *PirqTable;\r
- UINTN PirqTableSize;\r
- UINTN Flags;\r
- HDD_INFO *HddInfo;\r
- UINT64 Supports;\r
+ EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ EFI_LEGACY_8259_PROTOCOL *Legacy8259;\r
+ EFI_LEGACY_INTERRUPT_PROTOCOL *LegacyInterrupt;\r
+ EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *LegacyBiosPlatform;\r
+ UINT8 InterruptPin;\r
+ UINTN Index;\r
+ UINTN HandleCount;\r
+ EFI_HANDLE *HandleBuffer;\r
+ UINTN MassStorageHandleCount;\r
+ EFI_HANDLE *MassStorageHandleBuffer;\r
+ UINTN MassStorageHandleIndex;\r
+ UINT8 PciIrq;\r
+ UINT16 Command;\r
+ UINTN PciSegment;\r
+ UINTN PciBus;\r
+ UINTN PciDevice;\r
+ UINTN PciFunction;\r
+ EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable;\r
+ UINTN RoutingTableEntries;\r
+ UINT16 LegMask;\r
+ UINT16 LegEdgeLevel;\r
+ PCI_TYPE00 PciConfigHeader;\r
+ EFI_LEGACY_PIRQ_TABLE_HEADER *PirqTable;\r
+ UINTN PirqTableSize;\r
+ UINTN Flags;\r
+ HDD_INFO *HddInfo;\r
+ UINT64 Supports;\r
\r
//\r
// Note - This routine use to return immediately if Private->PciInterruptLine\r
// EFI_ALREADY_STARTED. In addition check if PCI device InterruptLine != 0.\r
// If zero then function unprogrammed else skip function.\r
//\r
- Legacy8259 = Private->Legacy8259;\r
- LegacyInterrupt = Private->LegacyInterrupt;\r
- LegacyBiosPlatform = Private->LegacyBiosPlatform;\r
+ Legacy8259 = Private->Legacy8259;\r
+ LegacyInterrupt = Private->LegacyInterrupt;\r
+ LegacyBiosPlatform = Private->LegacyBiosPlatform;\r
\r
LegacyBiosPlatform->GetRoutingTable (\r
Private->LegacyBiosPlatform,\r
- (VOID *) &RoutingTable,\r
+ (VOID *)&RoutingTable,\r
&RoutingTableEntries,\r
- (VOID *) &PirqTable,\r
+ (VOID *)&PirqTable,\r
&PirqTableSize,\r
NULL,\r
NULL\r
if (EFI_ERROR (Status)) {\r
return EFI_NOT_FOUND;\r
}\r
+\r
if (HandleCount == mHandleCount) {\r
FreePool (HandleBuffer);\r
return EFI_ALREADY_STARTED;\r
Status = gBS->HandleProtocol (\r
HandleBuffer[Index],\r
&gEfiPciIoProtocolGuid,\r
- (VOID **) &PciIo\r
+ (VOID **)&PciIo\r
);\r
ASSERT_EFI_ERROR (Status);\r
\r
);\r
if (!EFI_ERROR (Status)) {\r
Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;\r
- Status = PciIo->Attributes (\r
- PciIo,\r
- EfiPciIoAttributeOperationEnable,\r
- Supports,\r
- NULL\r
- );\r
+ Status = PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationEnable,\r
+ Supports,\r
+ NULL\r
+ );\r
}\r
+\r
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x04, 1, &Command);\r
\r
if (EFI_ERROR (Status)) {\r
&InterruptPin\r
);\r
}\r
+\r
//\r
// Translate InterruptPin(0-3) into PIRQ\r
//\r
// since ConnectController may force native mode and we don't\r
// want that for primary IDE controller\r
//\r
- MassStorageHandleCount = 0;\r
+ MassStorageHandleCount = 0;\r
MassStorageHandleBuffer = NULL;\r
LegacyBiosPlatform->GetPlatformHandle (\r
Private->LegacyBiosPlatform,\r
}\r
}\r
}\r
+\r
//\r
// Write InterruptPin and enable 8259.\r
//\r
1,\r
&PciIrq\r
);\r
- Private->IntThunk->EfiToLegacy16BootTable.PciIrqMask = (UINT16) (Private->IntThunk->EfiToLegacy16BootTable.PciIrqMask | (UINT16) (1 << PciIrq));\r
+ Private->IntThunk->EfiToLegacy16BootTable.PciIrqMask = (UINT16)(Private->IntThunk->EfiToLegacy16BootTable.PciIrqMask | (UINT16)(1 << PciIrq));\r
\r
Legacy8259->GetMask (\r
Legacy8259,\r
NULL\r
);\r
\r
- LegMask = (UINT16) (LegMask & (UINT16)~(1 << PciIrq));\r
- LegEdgeLevel = (UINT16) (LegEdgeLevel | (UINT16) (1 << PciIrq));\r
+ LegMask = (UINT16)(LegMask & (UINT16) ~(1 << PciIrq));\r
+ LegEdgeLevel = (UINT16)(LegEdgeLevel | (UINT16)(1 << PciIrq));\r
Legacy8259->SetMask (\r
Legacy8259,\r
&LegMask,\r
);\r
}\r
}\r
+\r
FreePool (HandleBuffer);\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Find & verify PnP Expansion header in ROM image\r
\r
**/\r
EFI_STATUS\r
FindNextPnpExpansionHeader (\r
- IN LEGACY_BIOS_INSTANCE *Private,\r
- IN BOOLEAN FirstHeader,\r
- IN OUT LEGACY_PNP_EXPANSION_HEADER **PnpPtr\r
+ IN LEGACY_BIOS_INSTANCE *Private,\r
+ IN BOOLEAN FirstHeader,\r
+ IN OUT LEGACY_PNP_EXPANSION_HEADER **PnpPtr\r
\r
)\r
{\r
- UINTN TempData;\r
- LEGACY_PNP_EXPANSION_HEADER *LocalPnpPtr;\r
+ UINTN TempData;\r
+ LEGACY_PNP_EXPANSION_HEADER *LocalPnpPtr;\r
+\r
LocalPnpPtr = *PnpPtr;\r
if (FirstHeader == FIRST_INSTANCE) {\r
- mBasePnpPtr = LocalPnpPtr;\r
- mBbsRomSegment = (UINT16) ((UINTN) mBasePnpPtr >> 4);\r
+ mBasePnpPtr = LocalPnpPtr;\r
+ mBbsRomSegment = (UINT16)((UINTN)mBasePnpPtr >> 4);\r
//\r
// Offset 0x1a gives offset to PnP expansion header for the first\r
// instance, there after the structure gives the offset to the next\r
// structure\r
//\r
- LocalPnpPtr = (LEGACY_PNP_EXPANSION_HEADER *) ((UINT8 *) LocalPnpPtr + 0x1a);\r
- TempData = (*((UINT16 *) LocalPnpPtr));\r
+ LocalPnpPtr = (LEGACY_PNP_EXPANSION_HEADER *)((UINT8 *)LocalPnpPtr + 0x1a);\r
+ TempData = (*((UINT16 *)LocalPnpPtr));\r
} else {\r
- TempData = (UINT16) LocalPnpPtr->NextHeader;\r
+ TempData = (UINT16)LocalPnpPtr->NextHeader;\r
}\r
\r
- LocalPnpPtr = (LEGACY_PNP_EXPANSION_HEADER *) (((UINT8 *) mBasePnpPtr + TempData));\r
+ LocalPnpPtr = (LEGACY_PNP_EXPANSION_HEADER *)(((UINT8 *)mBasePnpPtr + TempData));\r
\r
//\r
// Search for PnP table in Shadowed ROM\r
//\r
*PnpPtr = LocalPnpPtr;\r
- if (*(UINT32 *) LocalPnpPtr == SIGNATURE_32 ('$', 'P', 'n', 'P')) {\r
+ if (*(UINT32 *)LocalPnpPtr == SIGNATURE_32 ('$', 'P', 'n', 'P')) {\r
return EFI_SUCCESS;\r
} else {\r
return EFI_NOT_FOUND;\r
}\r
}\r
\r
-\r
/**\r
Update list of Bev or BCV table entries.\r
\r
IN EFI_PCI_IO_PROTOCOL *PciIo\r
)\r
{\r
- VOID *RomEnd;\r
- BBS_TABLE *BbsTable;\r
- UINTN BbsIndex;\r
- EFI_LEGACY_EXPANSION_ROM_HEADER *PciPtr;\r
- LEGACY_PNP_EXPANSION_HEADER *PnpPtr;\r
- BOOLEAN Instance;\r
- EFI_STATUS Status;\r
- UINTN Segment;\r
- UINTN Bus;\r
- UINTN Device;\r
- UINTN Function;\r
- UINT8 Class;\r
- UINT16 DeviceType;\r
- Segment = 0;\r
- Bus = 0;\r
- Device = 0;\r
- Function = 0;\r
- Class = 0;\r
- DeviceType = BBS_UNKNOWN;\r
+ VOID *RomEnd;\r
+ BBS_TABLE *BbsTable;\r
+ UINTN BbsIndex;\r
+ EFI_LEGACY_EXPANSION_ROM_HEADER *PciPtr;\r
+ LEGACY_PNP_EXPANSION_HEADER *PnpPtr;\r
+ BOOLEAN Instance;\r
+ EFI_STATUS Status;\r
+ UINTN Segment;\r
+ UINTN Bus;\r
+ UINTN Device;\r
+ UINTN Function;\r
+ UINT8 Class;\r
+ UINT16 DeviceType;\r
+\r
+ Segment = 0;\r
+ Bus = 0;\r
+ Device = 0;\r
+ Function = 0;\r
+ Class = 0;\r
+ DeviceType = BBS_UNKNOWN;\r
\r
//\r
// Skip floppy and 2*onboard IDE controller entries(Master/Slave per\r
// controller).\r
//\r
- BbsIndex = Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries;\r
+ BbsIndex = Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries;\r
\r
- BbsTable = (BBS_TABLE*)(UINTN) Private->IntThunk->EfiToLegacy16BootTable.BbsTable;\r
- PnpPtr = (LEGACY_PNP_EXPANSION_HEADER *) RomStart;\r
- PciPtr = (EFI_LEGACY_EXPANSION_ROM_HEADER *) RomStart;\r
+ BbsTable = (BBS_TABLE *)(UINTN)Private->IntThunk->EfiToLegacy16BootTable.BbsTable;\r
+ PnpPtr = (LEGACY_PNP_EXPANSION_HEADER *)RomStart;\r
+ PciPtr = (EFI_LEGACY_EXPANSION_ROM_HEADER *)RomStart;\r
\r
- RomEnd = (VOID *) (PciPtr->Size512 * 512 + (UINTN) PciPtr);\r
- Instance = FIRST_INSTANCE;\r
+ RomEnd = (VOID *)(PciPtr->Size512 * 512 + (UINTN)PciPtr);\r
+ Instance = FIRST_INSTANCE;\r
//\r
// OPROMs like PXE may not be tied to a piece of hardware and thus\r
// don't have a PciIo associated with them\r
}\r
\r
while (TRUE) {\r
- Status = FindNextPnpExpansionHeader (Private, Instance, &PnpPtr);\r
- Instance = NOT_FIRST_INSTANCE;\r
+ Status = FindNextPnpExpansionHeader (Private, Instance, &PnpPtr);\r
+ Instance = NOT_FIRST_INSTANCE;\r
if (EFI_ERROR (Status)) {\r
break;\r
}\r
+\r
//\r
// There can be additional $PnP headers within the OPROM.\r
// Example: SCSI can have one per drive.\r
//\r
BbsTable[BbsIndex].BootPriority = BBS_UNPRIORITIZED_ENTRY;\r
BbsTable[BbsIndex].DeviceType = DeviceType;\r
- BbsTable[BbsIndex].Bus = (UINT32) Bus;\r
- BbsTable[BbsIndex].Device = (UINT32) Device;\r
- BbsTable[BbsIndex].Function = (UINT32) Function;\r
+ BbsTable[BbsIndex].Bus = (UINT32)Bus;\r
+ BbsTable[BbsIndex].Device = (UINT32)Device;\r
+ BbsTable[BbsIndex].Function = (UINT32)Function;\r
BbsTable[BbsIndex].StatusFlags.OldPosition = 0;\r
BbsTable[BbsIndex].StatusFlags.Reserved1 = 0;\r
BbsTable[BbsIndex].StatusFlags.Enabled = 0;\r
}\r
\r
if (PnpPtr->Bev != 0) {\r
- BbsTable[BbsIndex].BootHandlerOffset = PnpPtr->Bev;\r
- BbsTable[BbsIndex].DeviceType = BBS_BEV_DEVICE;\r
+ BbsTable[BbsIndex].BootHandlerOffset = PnpPtr->Bev;\r
+ BbsTable[BbsIndex].DeviceType = BBS_BEV_DEVICE;\r
++BbsIndex;\r
}\r
\r
- if ((PnpPtr == (LEGACY_PNP_EXPANSION_HEADER *) PciPtr) || (PnpPtr > (LEGACY_PNP_EXPANSION_HEADER *) RomEnd)) {\r
+ if ((PnpPtr == (LEGACY_PNP_EXPANSION_HEADER *)PciPtr) || (PnpPtr > (LEGACY_PNP_EXPANSION_HEADER *)RomEnd)) {\r
break;\r
}\r
}\r
\r
- BbsTable[BbsIndex].BootPriority = BBS_IGNORE_ENTRY;\r
- Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries = (UINT32) BbsIndex;\r
+ BbsTable[BbsIndex].BootPriority = BBS_IGNORE_ENTRY;\r
+ Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries = (UINT32)BbsIndex;\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Shadow all the PCI legacy ROMs. Use data from the Legacy BIOS Protocol\r
to chose the order. Skip any devices that have already have legacy\r
**/\r
EFI_STATUS\r
PciShadowRoms (\r
- IN LEGACY_BIOS_INSTANCE *Private\r
+ IN LEGACY_BIOS_INSTANCE *Private\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- PCI_TYPE00 Pci;\r
- UINTN Index;\r
- UINTN HandleCount;\r
- EFI_HANDLE *HandleBuffer;\r
- EFI_HANDLE VgaHandle;\r
- EFI_HANDLE FirstHandle;\r
- VOID **RomStart;\r
- UINTN Flags;\r
- PCI_TYPE00 PciConfigHeader;\r
- UINT16 *Command;\r
- UINT64 Supports;\r
+ EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ PCI_TYPE00 Pci;\r
+ UINTN Index;\r
+ UINTN HandleCount;\r
+ EFI_HANDLE *HandleBuffer;\r
+ EFI_HANDLE VgaHandle;\r
+ EFI_HANDLE FirstHandle;\r
+ VOID **RomStart;\r
+ UINTN Flags;\r
+ PCI_TYPE00 PciConfigHeader;\r
+ UINT16 *Command;\r
+ UINT64 Supports;\r
\r
//\r
// Make the VGA device first\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Place the VGA handle as first.\r
//\r
break;\r
}\r
}\r
+\r
//\r
// Allocate memory to save Command WORD from each device. We do this\r
// to restore devices to same state as EFI after switching to legacy.\r
//\r
- Command = (UINT16 *) AllocatePool (\r
- sizeof (UINT16) * (HandleCount + 1)\r
- );\r
+ Command = (UINT16 *)AllocatePool (\r
+ sizeof (UINT16) * (HandleCount + 1)\r
+ );\r
if (NULL == Command) {\r
FreePool (HandleBuffer);\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
//\r
// Disconnect all EFI devices first. This covers cases where alegacy BIOS\r
// may control multiple PCI devices.\r
//\r
for (Index = 0; Index < HandleCount; Index++) {\r
-\r
Status = gBS->HandleProtocol (\r
HandleBuffer[Index],\r
&gEfiPciIoProtocolGuid,\r
- (VOID **) &PciIo\r
+ (VOID **)&PciIo\r
);\r
ASSERT_EFI_ERROR (Status);\r
\r
if (!EFI_ERROR (Status)) {\r
continue;\r
}\r
+\r
//\r
// Stop EFI Drivers with oprom.\r
//\r
NULL\r
);\r
}\r
+\r
//\r
// For every device that has not had a legacy ROM started. Start a legacy ROM.\r
//\r
for (Index = 0; Index < HandleCount; Index++) {\r
-\r
Status = gBS->HandleProtocol (\r
HandleBuffer[Index],\r
&gEfiPciIoProtocolGuid,\r
- (VOID **) &PciIo\r
+ (VOID **)&PciIo\r
);\r
\r
ASSERT_EFI_ERROR (Status);\r
// one will work in legacy mode (OPROM will be given control) and\r
// other Video devices will work in native mode (OS driver will handle these devices).\r
//\r
- if (IS_PCI_DISPLAY (&Pci) && Index != 0) {\r
+ if (IS_PCI_DISPLAY (&Pci) && (Index != 0)) {\r
continue;\r
}\r
+\r
//\r
// Skip any device that already has a legacy ROM run\r
//\r
//\r
// If legacy VBIOS Oprom has not been dispatched before, install legacy VBIOS here.\r
//\r
- if (IS_PCI_DISPLAY (&Pci) && Index == 0) {\r
+ if (IS_PCI_DISPLAY (&Pci) && (Index == 0)) {\r
Status = LegacyBiosInstallVgaRom (Private);\r
//\r
// A return status of EFI_NOT_FOUND is considered valid (No EFI\r
&Flags,\r
NULL,\r
NULL,\r
- (VOID **) &RomStart,\r
+ (VOID **)&RomStart,\r
NULL\r
);\r
if (EFI_ERROR (Status)) {\r
continue;\r
}\r
}\r
+\r
//\r
// Restore Command register so legacy has same devices enabled or disabled\r
// as EFI.\r
);\r
if (!EFI_ERROR (Status)) {\r
Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;\r
- Status = PciIo->Attributes (\r
- PciIo,\r
- EfiPciIoAttributeOperationEnable,\r
- Supports,\r
- NULL\r
- );\r
+ Status = PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationEnable,\r
+ Supports,\r
+ NULL\r
+ );\r
}\r
+\r
if (!EFI_ERROR (Status)) {\r
Command[Index] = 0x1f;\r
}\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Test to see if a legacy PCI ROM exists for this device. Optionally return\r
the Legacy ROM instance for this PCI device.\r
EFI_STATUS\r
EFIAPI\r
LegacyBiosCheckPciRom (\r
- IN EFI_LEGACY_BIOS_PROTOCOL *This,\r
- IN EFI_HANDLE PciHandle,\r
- OUT VOID **RomImage OPTIONAL,\r
- OUT UINTN *RomSize OPTIONAL,\r
- OUT UINTN *Flags\r
+ IN EFI_LEGACY_BIOS_PROTOCOL *This,\r
+ IN EFI_HANDLE PciHandle,\r
+ OUT VOID **RomImage OPTIONAL,\r
+ OUT UINTN *RomSize OPTIONAL,\r
+ OUT UINTN *Flags\r
)\r
{\r
return LegacyBiosCheckPciRomEx (\r
NULL,\r
NULL\r
);\r
-\r
}\r
\r
/**\r
**/\r
EFI_STATUS\r
LegacyBiosCheckPciRomEx (\r
- IN EFI_LEGACY_BIOS_PROTOCOL *This,\r
- IN EFI_HANDLE PciHandle,\r
- OUT VOID **RomImage OPTIONAL,\r
- OUT UINTN *RomSize OPTIONAL,\r
- OUT UINTN *RuntimeImageLength OPTIONAL,\r
- OUT UINTN *Flags OPTIONAL,\r
- OUT UINT8 *OpromRevision OPTIONAL,\r
- OUT VOID **ConfigUtilityCodeHeader OPTIONAL\r
+ IN EFI_LEGACY_BIOS_PROTOCOL *This,\r
+ IN EFI_HANDLE PciHandle,\r
+ OUT VOID **RomImage OPTIONAL,\r
+ OUT UINTN *RomSize OPTIONAL,\r
+ OUT UINTN *RuntimeImageLength OPTIONAL,\r
+ OUT UINTN *Flags OPTIONAL,\r
+ OUT UINT8 *OpromRevision OPTIONAL,\r
+ OUT VOID **ConfigUtilityCodeHeader OPTIONAL\r
)\r
{\r
- EFI_STATUS Status;\r
- LEGACY_BIOS_INSTANCE *Private;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- UINTN LocalRomSize;\r
- VOID *LocalRomImage;\r
- PCI_TYPE00 PciConfigHeader;\r
- VOID *LocalConfigUtilityCodeHeader;\r
+ EFI_STATUS Status;\r
+ LEGACY_BIOS_INSTANCE *Private;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ UINTN LocalRomSize;\r
+ VOID *LocalRomImage;\r
+ PCI_TYPE00 PciConfigHeader;\r
+ VOID *LocalConfigUtilityCodeHeader;\r
\r
LocalConfigUtilityCodeHeader = NULL;\r
- *Flags = NO_ROM;\r
- Status = gBS->HandleProtocol (\r
- PciHandle,\r
- &gEfiPciIoProtocolGuid,\r
- (VOID **) &PciIo\r
- );\r
+ *Flags = NO_ROM;\r
+ Status = gBS->HandleProtocol (\r
+ PciHandle,\r
+ &gEfiPciIoProtocolGuid,\r
+ (VOID **)&PciIo\r
+ );\r
if (EFI_ERROR (Status)) {\r
return EFI_UNSUPPORTED;\r
}\r
*Flags |= (UINTN)(ROM_FOUND | VALID_LEGACY_ROM);\r
return EFI_SUCCESS;\r
}\r
+\r
//\r
// Check for PCI ROM Bar\r
//\r
- LocalRomSize = (UINTN) PciIo->RomSize;\r
+ LocalRomSize = (UINTN)PciIo->RomSize;\r
LocalRomImage = PciIo->RomImage;\r
if (LocalRomSize != 0) {\r
*Flags |= ROM_FOUND;\r
);\r
\r
Private = LEGACY_BIOS_INSTANCE_FROM_THIS (This);\r
- Status = GetPciLegacyRom (\r
- Private->Csm16PciInterfaceVersion,\r
- PciConfigHeader.Hdr.VendorId,\r
- PciConfigHeader.Hdr.DeviceId,\r
- &LocalRomImage,\r
- &LocalRomSize,\r
- RuntimeImageLength,\r
- OpromRevision,\r
- &LocalConfigUtilityCodeHeader\r
- );\r
+ Status = GetPciLegacyRom (\r
+ Private->Csm16PciInterfaceVersion,\r
+ PciConfigHeader.Hdr.VendorId,\r
+ PciConfigHeader.Hdr.DeviceId,\r
+ &LocalRomImage,\r
+ &LocalRomSize,\r
+ RuntimeImageLength,\r
+ OpromRevision,\r
+ &LocalConfigUtilityCodeHeader\r
+ );\r
if (EFI_ERROR (Status)) {\r
return EFI_UNSUPPORTED;\r
}\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_HANDLE *HandleBuffer;\r
- UINTN HandleCount;\r
- EFI_ISA_IO_PROTOCOL *IsaIo;\r
- UINTN Index;\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE *HandleBuffer;\r
+ UINTN HandleCount;\r
+ EFI_ISA_IO_PROTOCOL *IsaIo;\r
+ UINTN Index;\r
\r
//\r
// Get SimpleTextIn and find PS2 controller\r
if (EFI_ERROR (Status)) {\r
return EFI_NOT_FOUND;\r
}\r
+\r
for (Index = 0; Index < HandleCount; Index++) {\r
//\r
// Open the IO Abstraction(s) needed to perform the supported test\r
Status = gBS->OpenProtocol (\r
HandleBuffer[Index],\r
&gEfiIsaIoProtocolGuid,\r
- (VOID **) &IsaIo,\r
+ (VOID **)&IsaIo,\r
NULL,\r
HandleBuffer[Index],\r
EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL\r
// Use the ISA I/O Protocol to see if Controller is the Keyboard\r
// controller\r
//\r
- if (IsaIo->ResourceList->Device.HID != EISA_PNP_ID (0x303) || IsaIo->ResourceList->Device.UID != 0) {\r
+ if ((IsaIo->ResourceList->Device.HID != EISA_PNP_ID (0x303)) || (IsaIo->ResourceList->Device.UID != 0)) {\r
Status = EFI_UNSUPPORTED;\r
}\r
\r
gBS->ConnectController (HandleBuffer[Index], NULL, NULL, FALSE);\r
}\r
}\r
+\r
FreePool (HandleBuffer);\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Load a legacy PC-AT OpROM for VGA controller.\r
\r
**/\r
EFI_STATUS\r
LegacyBiosInstallVgaRom (\r
- IN LEGACY_BIOS_INSTANCE *Private\r
+ IN LEGACY_BIOS_INSTANCE *Private\r
)\r
{\r
EFI_STATUS Status;\r
Status = gBS->HandleProtocol (\r
OpenInfoBuffer[Index].AgentHandle,\r
&gEfiLegacyBiosGuid,\r
- (VOID **) &Interface\r
+ (VOID **)&Interface\r
);\r
if (!EFI_ERROR (Status)) {\r
//\r
return Status;\r
}\r
}\r
+\r
//\r
// Find all the Thunk Driver\r
//\r
HandleBuffer = NULL;\r
- Status = gBS->LocateHandleBuffer (\r
- ByProtocol,\r
- &gEfiLegacyBiosGuid,\r
- NULL,\r
- &HandleCount,\r
- &HandleBuffer\r
- );\r
+ Status = gBS->LocateHandleBuffer (\r
+ ByProtocol,\r
+ &gEfiLegacyBiosGuid,\r
+ NULL,\r
+ &HandleCount,\r
+ &HandleBuffer\r
+ );\r
ASSERT_EFI_ERROR (Status);\r
- ConnectHandleBuffer = (EFI_HANDLE *) AllocatePool (sizeof (EFI_HANDLE) * (HandleCount + 1));\r
+ ConnectHandleBuffer = (EFI_HANDLE *)AllocatePool (sizeof (EFI_HANDLE) * (HandleCount + 1));\r
ASSERT (ConnectHandleBuffer != NULL);\r
\r
CopyMem (\r
Status = gBS->HandleProtocol (\r
VgaHandle,\r
&gEfiPciIoProtocolGuid,\r
- (VOID **) &PciIo\r
+ (VOID **)&PciIo\r
);\r
ASSERT_EFI_ERROR (Status);\r
PciIo->Pci.Read (\r
FreePool (ConnectHandleBuffer);\r
\r
if (EFI_ERROR (Status)) {\r
-\r
Private->VgaInstalled = FALSE;\r
\r
//\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Load a legacy PC-AT OpROM.\r
\r
EFI_STATUS\r
EFIAPI\r
LegacyBiosInstallRom (\r
- IN EFI_LEGACY_BIOS_PROTOCOL *This,\r
- IN LEGACY_BIOS_INSTANCE *Private,\r
- IN EFI_HANDLE PciHandle,\r
- IN UINT8 OpromRevision,\r
- IN VOID *RomImage,\r
- IN UINTN ImageSize,\r
- IN OUT UINTN *RuntimeImageLength,\r
- OUT UINT8 *DiskStart OPTIONAL,\r
- OUT UINT8 *DiskEnd OPTIONAL,\r
- OUT VOID **RomShadowAddress OPTIONAL\r
+ IN EFI_LEGACY_BIOS_PROTOCOL *This,\r
+ IN LEGACY_BIOS_INSTANCE *Private,\r
+ IN EFI_HANDLE PciHandle,\r
+ IN UINT8 OpromRevision,\r
+ IN VOID *RomImage,\r
+ IN UINTN ImageSize,\r
+ IN OUT UINTN *RuntimeImageLength,\r
+ OUT UINT8 *DiskStart OPTIONAL,\r
+ OUT UINT8 *DiskEnd OPTIONAL,\r
+ OUT VOID **RomShadowAddress OPTIONAL\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_STATUS PciEnableStatus;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- UINT8 LocalDiskStart;\r
- UINT8 LocalDiskEnd;\r
- UINTN Segment;\r
- UINTN Bus;\r
- UINTN Device;\r
- UINTN Function;\r
- EFI_IA32_REGISTER_SET Regs;\r
- UINT8 VideoMode;\r
- UINT8 OldVideoMode;\r
- EFI_TIME BootTime;\r
- UINT32 *BdaPtr;\r
- UINT32 LocalTime;\r
- UINT32 StartBbsIndex;\r
- UINT32 EndBbsIndex;\r
- UINT32 MaxRomAddr;\r
- UINTN TempData;\r
- UINTN InitAddress;\r
- UINTN RuntimeAddress;\r
- EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
- UINT32 Granularity;\r
+ EFI_STATUS Status;\r
+ EFI_STATUS PciEnableStatus;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ UINT8 LocalDiskStart;\r
+ UINT8 LocalDiskEnd;\r
+ UINTN Segment;\r
+ UINTN Bus;\r
+ UINTN Device;\r
+ UINTN Function;\r
+ EFI_IA32_REGISTER_SET Regs;\r
+ UINT8 VideoMode;\r
+ UINT8 OldVideoMode;\r
+ EFI_TIME BootTime;\r
+ UINT32 *BdaPtr;\r
+ UINT32 LocalTime;\r
+ UINT32 StartBbsIndex;\r
+ UINT32 EndBbsIndex;\r
+ UINT32 MaxRomAddr;\r
+ UINTN TempData;\r
+ UINTN InitAddress;\r
+ UINTN RuntimeAddress;\r
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
+ UINT32 Granularity;\r
\r
PciIo = NULL;\r
LocalDiskStart = 0;\r
PhysicalAddress = 0;\r
MaxRomAddr = PcdGet32 (PcdEndOpromShadowAddress);\r
\r
- if ((Private->Legacy16Table->TableLength >= OFFSET_OF(EFI_COMPATIBILITY16_TABLE, HiPermanentMemoryAddress)) &&\r
+ if ((Private->Legacy16Table->TableLength >= OFFSET_OF (EFI_COMPATIBILITY16_TABLE, HiPermanentMemoryAddress)) &&\r
(Private->Legacy16Table->UmaAddress != 0) &&\r
(Private->Legacy16Table->UmaSize != 0) &&\r
- (MaxRomAddr > (Private->Legacy16Table->UmaAddress))) {\r
+ (MaxRomAddr > (Private->Legacy16Table->UmaAddress)))\r
+ {\r
MaxRomAddr = Private->Legacy16Table->UmaAddress;\r
}\r
\r
-\r
PciProgramAllInterruptLineRegisters (Private);\r
\r
if ((OpromRevision >= 3) && (Private->Csm16PciInterfaceVersion >= 0x0300)) {\r
// first test if there is enough space for its INIT code\r
//\r
PhysicalAddress = CONVENTIONAL_MEMORY_TOP;\r
- Status = gBS->AllocatePages (\r
- AllocateMaxAddress,\r
- EfiBootServicesCode,\r
- EFI_SIZE_TO_PAGES (ImageSize),\r
- &PhysicalAddress\r
- );\r
+ Status = gBS->AllocatePages (\r
+ AllocateMaxAddress,\r
+ EfiBootServicesCode,\r
+ EFI_SIZE_TO_PAGES (ImageSize),\r
+ &PhysicalAddress\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "return LegacyBiosInstallRom(%d): EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", DEBUG_LINE_NUMBER));\r
);\r
return EFI_OUT_OF_RESOURCES;\r
}\r
- InitAddress = (UINTN) PhysicalAddress;\r
+\r
+ InitAddress = (UINTN)PhysicalAddress;\r
//\r
// then test if there is enough space for its RT code\r
//\r
// CSM16 2.x meets PCI 2.x/3.0 OpROM\r
// test if there is enough space for its INIT code\r
//\r
- InitAddress = PCI_START_ADDRESS (Private->OptionRom);\r
+ InitAddress = PCI_START_ADDRESS (Private->OptionRom);\r
if (InitAddress + ImageSize > MaxRomAddr) {\r
DEBUG ((DEBUG_ERROR, "return LegacyBiosInstallRom(%d): EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", DEBUG_LINE_NUMBER));\r
//\r
\r
Private->LegacyRegion->UnLock (\r
Private->LegacyRegion,\r
- (UINT32) RuntimeAddress,\r
- (UINT32) ImageSize,\r
+ (UINT32)RuntimeAddress,\r
+ (UINT32)ImageSize,\r
&Granularity\r
);\r
\r
DEBUG ((DEBUG_INFO, " Shadowing OpROM init/runtime/isize = %x/%x/%x\n", InitAddress, RuntimeAddress, ImageSize));\r
\r
- CopyMem ((VOID *) InitAddress, RomImage, ImageSize);\r
+ CopyMem ((VOID *)InitAddress, RomImage, ImageSize);\r
\r
//\r
// Read the highest disk number "installed: and assume a new disk will\r
// 3. Onboard IDE controllers will change 40:75\r
//\r
ACCESS_PAGE0_CODE (\r
- LocalDiskStart = (UINT8) ((*(UINT8 *) ((UINTN) 0x475)) + 0x80);\r
+ LocalDiskStart = (UINT8)((*(UINT8 *)((UINTN)0x475)) + 0x80);\r
if ((Private->Disk4075 + 0x80) < LocalDiskStart) {\r
- //\r
- // Update table since onboard IDE drives found\r
- //\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciSegment = 0xff;\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciBus = 0xff;\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciDevice = 0xff;\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciFunction = 0xff;\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].StartDriveNumber = (UINT8) (Private->Disk4075 + 0x80);\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].EndDriveNumber = LocalDiskStart;\r
- Private->LegacyEfiHddTableIndex ++;\r
- Private->Disk4075 = (UINT8) (LocalDiskStart & 0x7f);\r
- Private->DiskEnd = LocalDiskStart;\r
- }\r
+ //\r
+ // Update table since onboard IDE drives found\r
+ //\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciSegment = 0xff;\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciBus = 0xff;\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciDevice = 0xff;\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciFunction = 0xff;\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].StartDriveNumber = (UINT8)(Private->Disk4075 + 0x80);\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].EndDriveNumber = LocalDiskStart;\r
+ Private->LegacyEfiHddTableIndex++;\r
+ Private->Disk4075 = (UINT8)(LocalDiskStart & 0x7f);\r
+ Private->DiskEnd = LocalDiskStart;\r
+ }\r
\r
if (PciHandle != mVgaHandle) {\r
+ EnablePs2Keyboard ();\r
\r
- EnablePs2Keyboard ();\r
+ //\r
+ // Store current mode settings since PrepareToScanRom may change mode.\r
+ //\r
+ VideoMode = *(UINT8 *)((UINTN)(0x400 + BDA_VIDEO_MODE));\r
+ }\r
\r
- //\r
- // Store current mode settings since PrepareToScanRom may change mode.\r
- //\r
- VideoMode = *(UINT8 *) ((UINTN) (0x400 + BDA_VIDEO_MODE));\r
- }\r
- );\r
+ );\r
\r
//\r
// Notify the platform that we are about to scan the ROM\r
//\r
ACCESS_PAGE0_CODE (\r
LocalTime = (LocalTime * 182) / 10;\r
- BdaPtr = (UINT32 *) ((UINTN) 0x46C);\r
+ BdaPtr = (UINT32 *)((UINTN)0x46C);\r
*BdaPtr = LocalTime;\r
- );\r
+ );\r
\r
//\r
// Pass in handoff data\r
PciEnableStatus = EFI_UNSUPPORTED;\r
ZeroMem (&Regs, sizeof (Regs));\r
if (PciHandle != NULL) {\r
-\r
Status = gBS->HandleProtocol (\r
PciHandle,\r
&gEfiPciIoProtocolGuid,\r
- (VOID **) &PciIo\r
+ (VOID **)&PciIo\r
);\r
ASSERT_EFI_ERROR (Status);\r
\r
DEBUG ((DEBUG_INFO, "Shadowing OpROM on the PCI device %x/%x/%x\n", Bus, Device, Function));\r
}\r
\r
- mIgnoreBbsUpdateFlag = FALSE;\r
- Regs.X.AX = Legacy16DispatchOprom;\r
+ mIgnoreBbsUpdateFlag = FALSE;\r
+ Regs.X.AX = Legacy16DispatchOprom;\r
\r
//\r
// Generate DispatchOpRomTable data\r
//\r
Private->IntThunk->DispatchOpromTable.PnPInstallationCheckSegment = Private->Legacy16Table->PnPInstallationCheckSegment;\r
Private->IntThunk->DispatchOpromTable.PnPInstallationCheckOffset = Private->Legacy16Table->PnPInstallationCheckOffset;\r
- Private->IntThunk->DispatchOpromTable.OpromSegment = (UINT16) (InitAddress >> 4);\r
- Private->IntThunk->DispatchOpromTable.PciBus = (UINT8) Bus;\r
- Private->IntThunk->DispatchOpromTable.PciDeviceFunction = (UINT8) ((Device << 3) | Function);\r
- Private->IntThunk->DispatchOpromTable.NumberBbsEntries = (UINT8) Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries;\r
- Private->IntThunk->DispatchOpromTable.BbsTablePointer = (UINT32) (UINTN) Private->BbsTablePtr;\r
+ Private->IntThunk->DispatchOpromTable.OpromSegment = (UINT16)(InitAddress >> 4);\r
+ Private->IntThunk->DispatchOpromTable.PciBus = (UINT8)Bus;\r
+ Private->IntThunk->DispatchOpromTable.PciDeviceFunction = (UINT8)((Device << 3) | Function);\r
+ Private->IntThunk->DispatchOpromTable.NumberBbsEntries = (UINT8)Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries;\r
+ Private->IntThunk->DispatchOpromTable.BbsTablePointer = (UINT32)(UINTN)Private->BbsTablePtr;\r
Private->IntThunk->DispatchOpromTable.RuntimeSegment = (UINT16)((OpromRevision < 3) ? 0xffff : (RuntimeAddress >> 4));\r
- TempData = (UINTN) &Private->IntThunk->DispatchOpromTable;\r
- Regs.X.ES = EFI_SEGMENT ((UINT32) TempData);\r
- Regs.X.BX = EFI_OFFSET ((UINT32) TempData);\r
+ TempData = (UINTN)&Private->IntThunk->DispatchOpromTable;\r
+ Regs.X.ES = EFI_SEGMENT ((UINT32)TempData);\r
+ Regs.X.BX = EFI_OFFSET ((UINT32)TempData);\r
//\r
// Skip dispatching ROM for those PCI devices that can not be enabled by PciIo->Attributes\r
// Otherwise, it may cause the system to hang in some cases\r
if (!EFI_ERROR (PciEnableStatus)) {\r
DEBUG ((DEBUG_INFO, " Legacy16DispatchOprom - %02x/%02x/%02x\n", Bus, Device, Function));\r
Private->LegacyBios.FarCall86 (\r
- &Private->LegacyBios,\r
- Private->Legacy16CallSegment,\r
- Private->Legacy16CallOffset,\r
- &Regs,\r
- NULL,\r
- 0\r
- );\r
+ &Private->LegacyBios,\r
+ Private->Legacy16CallSegment,\r
+ Private->Legacy16CallOffset,\r
+ &Regs,\r
+ NULL,\r
+ 0\r
+ );\r
} else {\r
Regs.X.BX = 0;\r
}\r
\r
- if (Private->IntThunk->DispatchOpromTable.NumberBbsEntries != (UINT8) Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries) {\r
- Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries = (UINT8) Private->IntThunk->DispatchOpromTable.NumberBbsEntries;\r
- mIgnoreBbsUpdateFlag = TRUE;\r
+ if (Private->IntThunk->DispatchOpromTable.NumberBbsEntries != (UINT8)Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries) {\r
+ Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries = (UINT8)Private->IntThunk->DispatchOpromTable.NumberBbsEntries;\r
+ mIgnoreBbsUpdateFlag = TRUE;\r
}\r
+\r
//\r
// Check if non-BBS compliant drives found\r
//\r
if (Regs.X.BX != 0) {\r
- LocalDiskEnd = (UINT8) (LocalDiskStart + Regs.H.BL);\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciSegment = (UINT8) Segment;\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciBus = (UINT8) Bus;\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciDevice = (UINT8) Device;\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciFunction = (UINT8) Function;\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].StartDriveNumber = Private->DiskEnd;\r
- Private->DiskEnd = LocalDiskEnd;\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].EndDriveNumber = Private->DiskEnd;\r
- Private->LegacyEfiHddTableIndex += 1;\r
+ LocalDiskEnd = (UINT8)(LocalDiskStart + Regs.H.BL);\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciSegment = (UINT8)Segment;\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciBus = (UINT8)Bus;\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciDevice = (UINT8)Device;\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciFunction = (UINT8)Function;\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].StartDriveNumber = Private->DiskEnd;\r
+ Private->DiskEnd = LocalDiskEnd;\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].EndDriveNumber = Private->DiskEnd;\r
+ Private->LegacyEfiHddTableIndex += 1;\r
}\r
+\r
//\r
// Skip video mode set, if installing VGA\r
//\r
//\r
// Set mode settings since PrepareToScanRom may change mode\r
//\r
- ACCESS_PAGE0_CODE ({\r
- OldVideoMode = *(UINT8 *) ((UINTN) (0x400 + BDA_VIDEO_MODE));\r
- });\r
+ ACCESS_PAGE0_CODE (\r
+ {\r
+ OldVideoMode = *(UINT8 *)((UINTN)(0x400 + BDA_VIDEO_MODE));\r
+ }\r
+ );\r
\r
if (VideoMode != OldVideoMode) {\r
//\r
Private->LegacyBios.Int86 (&Private->LegacyBios, 0x10, &Regs);\r
}\r
}\r
+\r
//\r
// Regs.X.AX from the adapter initializion is ignored since some adapters\r
// do not follow the standard of setting AX = 0 on success.\r
//\r
// The ROM could have updated its size so we need to read again.\r
//\r
- if (((EFI_LEGACY_EXPANSION_ROM_HEADER *) RuntimeAddress)->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {\r
+ if (((EFI_LEGACY_EXPANSION_ROM_HEADER *)RuntimeAddress)->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {\r
//\r
// Now we check the signature (0xaa55) to judge whether the run-time code is truly generated by INIT function.\r
// If signature is not valid, that means the INIT function didn't copy the run-time code to RuntimeAddress.\r
//\r
*RuntimeImageLength = 0;\r
} else {\r
- *RuntimeImageLength = ((EFI_LEGACY_EXPANSION_ROM_HEADER *) RuntimeAddress)->Size512 * 512;\r
+ *RuntimeImageLength = ((EFI_LEGACY_EXPANSION_ROM_HEADER *)RuntimeAddress)->Size512 * 512;\r
}\r
\r
DEBUG ((DEBUG_INFO, " fsize = %x\n", *RuntimeImageLength));\r
//\r
// Make area from end of shadowed rom to end of original rom all ffs\r
//\r
- gBS->SetMem ((VOID *) (InitAddress + *RuntimeImageLength), ImageSize - *RuntimeImageLength, 0xff);\r
+ gBS->SetMem ((VOID *)(InitAddress + *RuntimeImageLength), ImageSize - *RuntimeImageLength, 0xff);\r
}\r
}\r
\r
ACCESS_PAGE0_CODE (\r
- LocalDiskEnd = (UINT8) ((*(UINT8 *) ((UINTN) 0x475)) + 0x80);\r
- );\r
+ LocalDiskEnd = (UINT8)((*(UINT8 *)((UINTN)0x475)) + 0x80);\r
+ );\r
\r
//\r
// Allow platform to perform any required actions after the\r
TempData = RuntimeAddress;\r
UpdateBevBcvTable (\r
Private,\r
- (EFI_LEGACY_EXPANSION_ROM_HEADER *) TempData,\r
+ (EFI_LEGACY_EXPANSION_ROM_HEADER *)TempData,\r
PciIo\r
);\r
- EndBbsIndex = Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries;\r
- LocalDiskEnd = (UINT8) (LocalDiskStart + (UINT8) (EndBbsIndex - StartBbsIndex));\r
+ EndBbsIndex = Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries;\r
+ LocalDiskEnd = (UINT8)(LocalDiskStart + (UINT8)(EndBbsIndex - StartBbsIndex));\r
if (LocalDiskEnd != LocalDiskStart) {\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciSegment = (UINT8) Segment;\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciBus = (UINT8) Bus;\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciDevice = (UINT8) Device;\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciFunction = (UINT8) Function;\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].StartDriveNumber = Private->DiskEnd;\r
- Private->DiskEnd = LocalDiskEnd;\r
- Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].EndDriveNumber = Private->DiskEnd;\r
- Private->LegacyEfiHddTableIndex += 1;\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciSegment = (UINT8)Segment;\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciBus = (UINT8)Bus;\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciDevice = (UINT8)Device;\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciFunction = (UINT8)Function;\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].StartDriveNumber = Private->DiskEnd;\r
+ Private->DiskEnd = LocalDiskEnd;\r
+ Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].EndDriveNumber = Private->DiskEnd;\r
+ Private->LegacyEfiHddTableIndex += 1;\r
}\r
}\r
+\r
//\r
// Mark PCI device as having a legacy BIOS ROM loaded.\r
//\r
RomShadow (\r
PciHandle,\r
- (UINT32) RuntimeAddress,\r
- (UINT32) *RuntimeImageLength,\r
+ (UINT32)RuntimeAddress,\r
+ (UINT32)*RuntimeImageLength,\r
LocalDiskStart,\r
LocalDiskEnd\r
);\r
// Stuff caller's OPTIONAL return parameters.\r
//\r
if (RomShadowAddress != NULL) {\r
- *RomShadowAddress = (VOID *) RuntimeAddress;\r
+ *RomShadowAddress = (VOID *)RuntimeAddress;\r
}\r
\r
if (DiskStart != NULL) {\r
*DiskEnd = LocalDiskEnd;\r
}\r
\r
- Private->OptionRom = (UINT32) (RuntimeAddress + *RuntimeImageLength);\r
+ Private->OptionRom = (UINT32)(RuntimeAddress + *RuntimeImageLength);\r
\r
Status = EFI_SUCCESS;\r
\r
**/\r
EFI_STATUS\r
IoMmuGrantAccess (\r
- IN EFI_HANDLE PciHandle,\r
- IN EFI_PHYSICAL_ADDRESS HostAddress,\r
- IN UINTN NumberOfBytes\r
+ IN EFI_HANDLE PciHandle,\r
+ IN EFI_PHYSICAL_ADDRESS HostAddress,\r
+ IN UINTN NumberOfBytes\r
)\r
{\r
- EFI_PHYSICAL_ADDRESS DeviceAddress;\r
- VOID *Mapping;\r
- EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS DeviceAddress;\r
+ VOID *Mapping;\r
+ EFI_STATUS Status;\r
\r
if (PciHandle == NULL) {\r
return EFI_UNSUPPORTED;\r
if (mIoMmu == NULL) {\r
gBS->LocateProtocol (&gEdkiiIoMmuProtocolGuid, NULL, (VOID **)&mIoMmu);\r
}\r
+\r
if (mIoMmu != NULL) {\r
Status = mIoMmu->Map (\r
mIoMmu,\r
&DeviceAddress,\r
&Mapping\r
);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "LegacyPci - IoMmuMap - %r\n", Status));\r
} else {\r
ASSERT (DeviceAddress == HostAddress);\r
Mapping,\r
EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE\r
);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "LegacyPci - IoMmuSetAttribute - %r\n", Status));\r
}\r
}\r
}\r
+\r
return Status;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
LegacyBiosInstallPciRom (\r
- IN EFI_LEGACY_BIOS_PROTOCOL * This,\r
- IN EFI_HANDLE PciHandle,\r
- IN VOID **RomImage,\r
- OUT UINTN *Flags,\r
- OUT UINT8 *DiskStart OPTIONAL,\r
- OUT UINT8 *DiskEnd OPTIONAL,\r
- OUT VOID **RomShadowAddress OPTIONAL,\r
- OUT UINT32 *RomShadowedSize OPTIONAL\r
+ IN EFI_LEGACY_BIOS_PROTOCOL *This,\r
+ IN EFI_HANDLE PciHandle,\r
+ IN VOID **RomImage,\r
+ OUT UINTN *Flags,\r
+ OUT UINT8 *DiskStart OPTIONAL,\r
+ OUT UINT8 *DiskEnd OPTIONAL,\r
+ OUT VOID **RomShadowAddress OPTIONAL,\r
+ OUT UINT32 *RomShadowedSize OPTIONAL\r
)\r
{\r
- EFI_STATUS Status;\r
- LEGACY_BIOS_INSTANCE *Private;\r
- VOID *LocalRomImage;\r
- UINTN ImageSize;\r
- UINTN RuntimeImageLength;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- PCI_TYPE01 PciConfigHeader;\r
- UINTN HandleCount;\r
- EFI_HANDLE *HandleBuffer;\r
- UINTN PciSegment;\r
- UINTN PciBus;\r
- UINTN PciDevice;\r
- UINTN PciFunction;\r
- UINTN LastBus;\r
- UINTN Index;\r
- UINT8 OpromRevision;\r
- UINT32 Granularity;\r
- PCI_3_0_DATA_STRUCTURE *Pcir;\r
+ EFI_STATUS Status;\r
+ LEGACY_BIOS_INSTANCE *Private;\r
+ VOID *LocalRomImage;\r
+ UINTN ImageSize;\r
+ UINTN RuntimeImageLength;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ PCI_TYPE01 PciConfigHeader;\r
+ UINTN HandleCount;\r
+ EFI_HANDLE *HandleBuffer;\r
+ UINTN PciSegment;\r
+ UINTN PciBus;\r
+ UINTN PciDevice;\r
+ UINTN PciFunction;\r
+ UINTN LastBus;\r
+ UINTN Index;\r
+ UINT8 OpromRevision;\r
+ UINT32 Granularity;\r
+ PCI_3_0_DATA_STRUCTURE *Pcir;\r
\r
OpromRevision = 0;\r
\r
Status = gBS->HandleProtocol (\r
HandleBuffer[Index],\r
&gEfiPciIoProtocolGuid,\r
- (VOID **) &PciIo\r
+ (VOID **)&PciIo\r
);\r
if (EFI_ERROR (Status)) {\r
continue;\r
0x20000,\r
&Granularity\r
);\r
- Private->Legacy16Table->LastPciBus = (UINT8) LastBus;\r
+ Private->Legacy16Table->LastPciBus = (UINT8)LastBus;\r
Private->LegacyRegion->Lock (\r
Private->LegacyRegion,\r
0xE0000,\r
Status = gBS->HandleProtocol (\r
PciHandle,\r
&gEfiPciIoProtocolGuid,\r
- (VOID **) &PciIo\r
+ (VOID **)&PciIo\r
);\r
\r
if (!EFI_ERROR (Status)) {\r
// if video installed & OPROM is video return\r
//\r
if (\r
- (\r
- ((PciConfigHeader.Hdr.ClassCode[2] == PCI_CLASS_OLD) &&\r
- (PciConfigHeader.Hdr.ClassCode[1] == PCI_CLASS_OLD_VGA))\r
- ||\r
- ((PciConfigHeader.Hdr.ClassCode[2] == PCI_CLASS_DISPLAY) &&\r
- (PciConfigHeader.Hdr.ClassCode[1] == PCI_CLASS_DISPLAY_VGA))\r
- )\r
- &&\r
- (!Private->VgaInstalled)\r
- ) {\r
+ (\r
+ ((PciConfigHeader.Hdr.ClassCode[2] == PCI_CLASS_OLD) &&\r
+ (PciConfigHeader.Hdr.ClassCode[1] == PCI_CLASS_OLD_VGA))\r
+ ||\r
+ ((PciConfigHeader.Hdr.ClassCode[2] == PCI_CLASS_DISPLAY) &&\r
+ (PciConfigHeader.Hdr.ClassCode[1] == PCI_CLASS_DISPLAY_VGA))\r
+ )\r
+ &&\r
+ (!Private->VgaInstalled)\r
+ )\r
+ {\r
mVgaInstallationInProgress = TRUE;\r
\r
//\r
//\r
}\r
}\r
+\r
//\r
// To run any legacy image, the VGA needs to be installed first.\r
// if installing the video, then don't need the thunk as already installed.\r
// A return status of EFI_NOT_FOUND is considered valid (No EFI\r
// driver is controlling video.\r
//\r
- mVgaInstallationInProgress = TRUE;\r
- Status = LegacyBiosInstallVgaRom (Private);\r
+ mVgaInstallationInProgress = TRUE;\r
+ Status = LegacyBiosInstallVgaRom (Private);\r
if (EFI_ERROR (Status)) {\r
if (Status != EFI_NOT_FOUND) {\r
mVgaInstallationInProgress = FALSE;\r
}\r
}\r
}\r
+\r
//\r
// See if the option ROM for PciHandle has already been executed\r
//\r
DiskStart,\r
DiskEnd,\r
RomShadowAddress,\r
- (UINTN *) RomShadowedSize\r
+ (UINTN *)RomShadowedSize\r
);\r
return EFI_SUCCESS;\r
}\r
// A return status of EFI_NOT_FOUND is considered valid (No EFI\r
// driver is controlling video.\r
//\r
- mVgaInstallationInProgress = TRUE;\r
- Status = LegacyBiosInstallVgaRom (Private);\r
+ mVgaInstallationInProgress = TRUE;\r
+ Status = LegacyBiosInstallVgaRom (Private);\r
if (EFI_ERROR (Status)) {\r
if (Status != EFI_NOT_FOUND) {\r
mVgaInstallationInProgress = FALSE;\r
}\r
\r
LocalRomImage = *RomImage;\r
- if (((PCI_EXPANSION_ROM_HEADER *) LocalRomImage)->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE ||\r
- ((PCI_EXPANSION_ROM_HEADER *) LocalRomImage)->PcirOffset == 0 ||\r
- (((PCI_EXPANSION_ROM_HEADER *) LocalRomImage)->PcirOffset & 3 ) != 0) {\r
+ if ((((PCI_EXPANSION_ROM_HEADER *)LocalRomImage)->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) ||\r
+ (((PCI_EXPANSION_ROM_HEADER *)LocalRomImage)->PcirOffset == 0) ||\r
+ ((((PCI_EXPANSION_ROM_HEADER *)LocalRomImage)->PcirOffset & 3) != 0))\r
+ {\r
mVgaInstallationInProgress = FALSE;\r
return EFI_UNSUPPORTED;\r
}\r
\r
Pcir = (PCI_3_0_DATA_STRUCTURE *)\r
- ((UINT8 *) LocalRomImage + ((PCI_EXPANSION_ROM_HEADER *) LocalRomImage)->PcirOffset);\r
+ ((UINT8 *)LocalRomImage + ((PCI_EXPANSION_ROM_HEADER *)LocalRomImage)->PcirOffset);\r
\r
if ((Pcir->Signature != PCI_DATA_STRUCTURE_SIGNATURE) || (Pcir->CodeType != PCI_CODE_TYPE_PCAT_IMAGE)) {\r
mVgaInstallationInProgress = FALSE;\r
} else {\r
OpromRevision = 0;\r
}\r
+\r
if (Pcir->Revision < 3) {\r
RuntimeImageLength = 0;\r
} else {\r
//\r
ASSERT (Private->TraceIndex < 0x200);\r
Private->Trace[Private->TraceIndex] = LEGACY_PCI_TRACE_000;\r
- Private->TraceIndex ++;\r
- Private->TraceIndex = (UINT16) (Private->TraceIndex % 0x200);\r
- Status = LegacyBiosInstallRom (\r
- This,\r
- Private,\r
- PciHandle,\r
- OpromRevision,\r
- LocalRomImage,\r
- ImageSize,\r
- &RuntimeImageLength,\r
- DiskStart,\r
- DiskEnd,\r
- RomShadowAddress\r
- );\r
+ Private->TraceIndex++;\r
+ Private->TraceIndex = (UINT16)(Private->TraceIndex % 0x200);\r
+ Status = LegacyBiosInstallRom (\r
+ This,\r
+ Private,\r
+ PciHandle,\r
+ OpromRevision,\r
+ LocalRomImage,\r
+ ImageSize,\r
+ &RuntimeImageLength,\r
+ DiskStart,\r
+ DiskEnd,\r
+ RomShadowAddress\r
+ );\r
if (RomShadowedSize != NULL) {\r
- *RomShadowedSize = (UINT32) RuntimeImageLength;\r
+ *RomShadowedSize = (UINT32)RuntimeImageLength;\r
}\r
\r
mVgaInstallationInProgress = FALSE;\r
projects / mirror_edk2.git / blobdiff