// interupts other than the Timer interrupt that was disabled above can not be\r
// handled properly from real mode.\r
//\r
- DEBUG_CODE (\r
+ DEBUG_CODE_BEGIN ();\r
UINTN Vector;\r
UINTN Count;\r
\r
DEBUG ((DEBUG_ERROR, "ERROR: More than one HW interrupt active with CSM enabled\n"));\r
}\r
ASSERT (Count < 2);\r
- );\r
+ DEBUG_CODE_END ();\r
\r
//\r
// If the Timer AP has enabled the 8254 timer IRQ and the current 8254 timer\r
// EBDA base address, if the current EBDA base address is smaller, it indicates\r
// PcdEbdaReservedMemorySize should be adjusted to larger for more OPROMs.\r
//\r
- DEBUG_CODE (\r
+ DEBUG_CODE_BEGIN ();\r
{\r
UINTN EbdaBaseAddress;\r
UINTN ReservedEbdaBaseAddress;\r
ASSERT (ReservedEbdaBaseAddress <= EbdaBaseAddress);\r
);\r
}\r
- );\r
+ DEBUG_CODE_END ();\r
\r
//\r
// Restore interrupt of debug timer\r