//\r
#pragma pack (1)\r
typedef struct {\r
- UINT32 Type;\r
- UINT64 ChildBase;\r
- UINT64 CpuBase;\r
- UINT64 Size;\r
+ UINT32 Type;\r
+ UINT64 ChildBase;\r
+ UINT64 CpuBase;\r
+ UINT64 Size;\r
} DTB_PCI_HOST_RANGE_RECORD;\r
#pragma pack ()\r
\r
-#define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31\r
-#define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30\r
-#define DTB_PCI_HOST_RANGE_ALIASED BIT29\r
-#define DTB_PCI_HOST_RANGE_MMIO32 BIT25\r
-#define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24)\r
-#define DTB_PCI_HOST_RANGE_IO BIT24\r
-#define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)\r
+#define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31\r
+#define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30\r
+#define DTB_PCI_HOST_RANGE_ALIASED BIT29\r
+#define DTB_PCI_HOST_RANGE_MMIO32 BIT25\r
+#define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24)\r
+#define DTB_PCI_HOST_RANGE_IO BIT24\r
+#define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)\r
\r
STATIC\r
EFI_STATUS\r
MapGcdMmioSpace (\r
- IN UINT64 Base,\r
- IN UINT64 Size\r
+ IN UINT64 Base,\r
+ IN UINT64 Size\r
)\r
{\r
- EFI_STATUS Status;\r
-\r
- Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo, Base, Size,\r
- EFI_MEMORY_UC);\r
+ EFI_STATUS Status;\r
+\r
+ Status = gDS->AddMemorySpace (\r
+ EfiGcdMemoryTypeMemoryMappedIo,\r
+ Base,\r
+ Size,\r
+ EFI_MEMORY_UC\r
+ );\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR,\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
"%a: failed to add GCD memory space for region [0x%Lx+0x%Lx)\n",\r
- __FUNCTION__, Base, Size));\r
+ __FUNCTION__,\r
+ Base,\r
+ Size\r
+ ));\r
return Status;\r
}\r
\r
Status = gDS->SetMemorySpaceAttributes (Base, Size, EFI_MEMORY_UC);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR,\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
"%a: failed to set memory space attributes for region [0x%Lx+0x%Lx)\n",\r
- __FUNCTION__, Base, Size));\r
+ __FUNCTION__,\r
+ Base,\r
+ Size\r
+ ));\r
}\r
+\r
return Status;\r
}\r
\r
STATIC\r
EFI_STATUS\r
ProcessPciHost (\r
- OUT UINT64 *IoBase,\r
- OUT UINT64 *IoSize,\r
- OUT UINT64 *Mmio32Base,\r
- OUT UINT64 *Mmio32Size,\r
- OUT UINT64 *Mmio64Base,\r
- OUT UINT64 *Mmio64Size,\r
- OUT UINT32 *BusMin,\r
- OUT UINT32 *BusMax\r
+ OUT UINT64 *IoBase,\r
+ OUT UINT64 *IoSize,\r
+ OUT UINT64 *Mmio32Base,\r
+ OUT UINT64 *Mmio32Size,\r
+ OUT UINT64 *Mmio64Base,\r
+ OUT UINT64 *Mmio64Size,\r
+ OUT UINT32 *BusMin,\r
+ OUT UINT32 *BusMax\r
)\r
{\r
- FDT_CLIENT_PROTOCOL *FdtClient;\r
- INT32 Node;\r
- UINT64 ConfigBase, ConfigSize;\r
- CONST VOID *Prop;\r
- UINT32 Len;\r
- UINT32 RecordIdx;\r
- EFI_STATUS Status;\r
- UINT64 IoTranslation;\r
- UINT64 Mmio32Translation;\r
- UINT64 Mmio64Translation;\r
+ FDT_CLIENT_PROTOCOL *FdtClient;\r
+ INT32 Node;\r
+ UINT64 ConfigBase, ConfigSize;\r
+ CONST VOID *Prop;\r
+ UINT32 Len;\r
+ UINT32 RecordIdx;\r
+ EFI_STATUS Status;\r
+ UINT64 IoTranslation;\r
+ UINT64 Mmio32Translation;\r
+ UINT64 Mmio64Translation;\r
\r
//\r
// The following output arguments are initialized only in\r
// order to suppress '-Werror=maybe-uninitialized' warnings\r
// *incorrectly* emitted by some gcc versions.\r
//\r
- *IoBase = 0;\r
+ *IoBase = 0;\r
*Mmio32Base = 0;\r
*Mmio64Base = MAX_UINT64;\r
- *BusMin = 0;\r
- *BusMax = 0;\r
+ *BusMin = 0;\r
+ *BusMax = 0;\r
\r
//\r
// *IoSize, *Mmio##Size and IoTranslation are initialized to zero because the\r
// logic below requires it. However, since they are also affected by the issue\r
// reported above, they are initialized early.\r
//\r
- *IoSize = 0;\r
- *Mmio32Size = 0;\r
- *Mmio64Size = 0;\r
+ *IoSize = 0;\r
+ *Mmio32Size = 0;\r
+ *Mmio64Size = 0;\r
IoTranslation = 0;\r
\r
- Status = gBS->LocateProtocol (&gFdtClientProtocolGuid, NULL,\r
- (VOID **)&FdtClient);\r
+ Status = gBS->LocateProtocol (\r
+ &gFdtClientProtocolGuid,\r
+ NULL,\r
+ (VOID **)&FdtClient\r
+ );\r
ASSERT_EFI_ERROR (Status);\r
\r
- Status = FdtClient->FindCompatibleNode (FdtClient, "pci-host-ecam-generic",\r
- &Node);\r
+ Status = FdtClient->FindCompatibleNode (\r
+ FdtClient,\r
+ "pci-host-ecam-generic",\r
+ &Node\r
+ );\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_INFO,\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
"%a: No 'pci-host-ecam-generic' compatible DT node found\n",\r
- __FUNCTION__));\r
+ __FUNCTION__\r
+ ));\r
return EFI_NOT_FOUND;\r
}\r
\r
// A DT can legally describe multiple PCI host bridges, but we are not\r
// equipped to deal with that. So assert that there is only one.\r
//\r
- Status = FdtClient->FindNextCompatibleNode (FdtClient,\r
- "pci-host-ecam-generic", Node, &Tmp);\r
+ Status = FdtClient->FindNextCompatibleNode (\r
+ FdtClient,\r
+ "pci-host-ecam-generic",\r
+ Node,\r
+ &Tmp\r
+ );\r
ASSERT (Status == EFI_NOT_FOUND);\r
- );\r
+ );\r
\r
Status = FdtClient->GetNodeProperty (FdtClient, Node, "reg", &Prop, &Len);\r
- if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT64)) {\r
- DEBUG ((DEBUG_ERROR, "%a: 'reg' property not found or invalid\n",\r
- __FUNCTION__));\r
+ if (EFI_ERROR (Status) || (Len != 2 * sizeof (UINT64))) {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: 'reg' property not found or invalid\n",\r
+ __FUNCTION__\r
+ ));\r
return EFI_PROTOCOL_ERROR;\r
}\r
\r
//\r
// Fetch the bus range (note: inclusive).\r
//\r
- Status = FdtClient->GetNodeProperty (FdtClient, Node, "bus-range", &Prop,\r
- &Len);\r
- if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT32)) {\r
- DEBUG ((DEBUG_ERROR, "%a: 'bus-range' not found or invalid\n",\r
- __FUNCTION__));\r
+ Status = FdtClient->GetNodeProperty (\r
+ FdtClient,\r
+ Node,\r
+ "bus-range",\r
+ &Prop,\r
+ &Len\r
+ );\r
+ if (EFI_ERROR (Status) || (Len != 2 * sizeof (UINT32))) {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: 'bus-range' not found or invalid\n",\r
+ __FUNCTION__\r
+ ));\r
return EFI_PROTOCOL_ERROR;\r
}\r
+\r
*BusMin = SwapBytes32 (((CONST UINT32 *)Prop)[0]);\r
*BusMax = SwapBytes32 (((CONST UINT32 *)Prop)[1]);\r
\r
// Sanity check: the config space must accommodate all 4K register bytes of\r
// all 8 functions of all 32 devices of all buses.\r
//\r
- if (*BusMax < *BusMin || *BusMax - *BusMin == MAX_UINT32 ||\r
- DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < *BusMax - *BusMin + 1) {\r
- DEBUG ((DEBUG_ERROR, "%a: invalid 'bus-range' and/or 'reg'\n",\r
- __FUNCTION__));\r
+ if ((*BusMax < *BusMin) || (*BusMax - *BusMin == MAX_UINT32) ||\r
+ (DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < *BusMax - *BusMin + 1))\r
+ {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: invalid 'bus-range' and/or 'reg'\n",\r
+ __FUNCTION__\r
+ ));\r
return EFI_PROTOCOL_ERROR;\r
}\r
\r
// Iterate over "ranges".\r
//\r
Status = FdtClient->GetNodeProperty (FdtClient, Node, "ranges", &Prop, &Len);\r
- if (EFI_ERROR (Status) || Len == 0 ||\r
- Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0) {\r
+ if (EFI_ERROR (Status) || (Len == 0) ||\r
+ (Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0))\r
+ {\r
DEBUG ((DEBUG_ERROR, "%a: 'ranges' not found or invalid\n", __FUNCTION__));\r
return EFI_PROTOCOL_ERROR;\r
}\r
\r
for (RecordIdx = 0; RecordIdx < Len / sizeof (DTB_PCI_HOST_RANGE_RECORD);\r
- ++RecordIdx) {\r
- CONST DTB_PCI_HOST_RANGE_RECORD *Record;\r
+ ++RecordIdx)\r
+ {\r
+ CONST DTB_PCI_HOST_RANGE_RECORD *Record;\r
\r
Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx;\r
switch (SwapBytes32 (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK) {\r
- case DTB_PCI_HOST_RANGE_IO:\r
- *IoBase = SwapBytes64 (Record->ChildBase);\r
- *IoSize = SwapBytes64 (Record->Size);\r
- IoTranslation = SwapBytes64 (Record->CpuBase) - *IoBase;\r
-\r
- ASSERT (PcdGet64 (PcdPciIoTranslation) == IoTranslation);\r
- break;\r
-\r
- case DTB_PCI_HOST_RANGE_MMIO32:\r
- *Mmio32Base = SwapBytes64 (Record->ChildBase);\r
- *Mmio32Size = SwapBytes64 (Record->Size);\r
- Mmio32Translation = SwapBytes64 (Record->CpuBase) - *Mmio32Base;\r
-\r
- if (*Mmio32Base > MAX_UINT32 || *Mmio32Size > MAX_UINT32 ||\r
- *Mmio32Base + *Mmio32Size > SIZE_4GB) {\r
- DEBUG ((DEBUG_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__));\r
- return EFI_PROTOCOL_ERROR;\r
- }\r
-\r
- ASSERT (PcdGet64 (PcdPciMmio32Translation) == Mmio32Translation);\r
-\r
- if (Mmio32Translation != 0) {\r
- DEBUG ((DEBUG_ERROR, "%a: unsupported nonzero MMIO32 translation "\r
- "0x%Lx\n", __FUNCTION__, Mmio32Translation));\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- break;\r
-\r
- case DTB_PCI_HOST_RANGE_MMIO64:\r
- *Mmio64Base = SwapBytes64 (Record->ChildBase);\r
- *Mmio64Size = SwapBytes64 (Record->Size);\r
- Mmio64Translation = SwapBytes64 (Record->CpuBase) - *Mmio64Base;\r
-\r
- ASSERT (PcdGet64 (PcdPciMmio64Translation) == Mmio64Translation);\r
-\r
- if (Mmio64Translation != 0) {\r
- DEBUG ((DEBUG_ERROR, "%a: unsupported nonzero MMIO64 translation "\r
- "0x%Lx\n", __FUNCTION__, Mmio64Translation));\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- break;\r
+ case DTB_PCI_HOST_RANGE_IO:\r
+ *IoBase = SwapBytes64 (Record->ChildBase);\r
+ *IoSize = SwapBytes64 (Record->Size);\r
+ IoTranslation = SwapBytes64 (Record->CpuBase) - *IoBase;\r
+\r
+ ASSERT (PcdGet64 (PcdPciIoTranslation) == IoTranslation);\r
+ break;\r
+\r
+ case DTB_PCI_HOST_RANGE_MMIO32:\r
+ *Mmio32Base = SwapBytes64 (Record->ChildBase);\r
+ *Mmio32Size = SwapBytes64 (Record->Size);\r
+ Mmio32Translation = SwapBytes64 (Record->CpuBase) - *Mmio32Base;\r
+\r
+ if ((*Mmio32Base > MAX_UINT32) || (*Mmio32Size > MAX_UINT32) ||\r
+ (*Mmio32Base + *Mmio32Size > SIZE_4GB))\r
+ {\r
+ DEBUG ((DEBUG_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__));\r
+ return EFI_PROTOCOL_ERROR;\r
+ }\r
+\r
+ ASSERT (PcdGet64 (PcdPciMmio32Translation) == Mmio32Translation);\r
+\r
+ if (Mmio32Translation != 0) {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: unsupported nonzero MMIO32 translation "\r
+ "0x%Lx\n",\r
+ __FUNCTION__,\r
+ Mmio32Translation\r
+ ));\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ break;\r
+\r
+ case DTB_PCI_HOST_RANGE_MMIO64:\r
+ *Mmio64Base = SwapBytes64 (Record->ChildBase);\r
+ *Mmio64Size = SwapBytes64 (Record->Size);\r
+ Mmio64Translation = SwapBytes64 (Record->CpuBase) - *Mmio64Base;\r
+\r
+ ASSERT (PcdGet64 (PcdPciMmio64Translation) == Mmio64Translation);\r
+\r
+ if (Mmio64Translation != 0) {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: unsupported nonzero MMIO64 translation "\r
+ "0x%Lx\n",\r
+ __FUNCTION__,\r
+ Mmio64Translation\r
+ ));\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ break;\r
}\r
}\r
- if (*IoSize == 0 || *Mmio32Size == 0) {\r
- DEBUG ((DEBUG_ERROR, "%a: %a space empty\n", __FUNCTION__,\r
- (*IoSize == 0) ? "IO" : "MMIO32"));\r
+\r
+ if ((*IoSize == 0) || (*Mmio32Size == 0)) {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: %a space empty\n",\r
+ __FUNCTION__,\r
+ (*IoSize == 0) ? "IO" : "MMIO32"\r
+ ));\r
return EFI_PROTOCOL_ERROR;\r
}\r
\r
//\r
ASSERT (PcdGet64 (PcdPciExpressBaseAddress) == ConfigBase);\r
\r
- DEBUG ((DEBUG_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "\r
"Io[0x%Lx+0x%Lx)@0x%Lx Mem32[0x%Lx+0x%Lx)@0x0 Mem64[0x%Lx+0x%Lx)@0x0\n",\r
- __FUNCTION__, ConfigBase, ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize,\r
- IoTranslation, *Mmio32Base, *Mmio32Size, *Mmio64Base, *Mmio64Size));\r
+ __FUNCTION__,\r
+ ConfigBase,\r
+ ConfigSize,\r
+ *BusMin,\r
+ *BusMax,\r
+ *IoBase,\r
+ *IoSize,\r
+ IoTranslation,\r
+ *Mmio32Base,\r
+ *Mmio32Size,\r
+ *Mmio64Base,\r
+ *Mmio64Size\r
+ ));\r
\r
// Map the ECAM space in the GCD memory map\r
Status = MapGcdMmioSpace (ConfigBase, ConfigSize);\r
PCI_ROOT_BRIDGE *\r
EFIAPI\r
PciHostBridgeGetRootBridges (\r
- UINTN *Count\r
+ UINTN *Count\r
)\r
{\r
- UINT64 IoBase, IoSize;\r
- UINT64 Mmio32Base, Mmio32Size;\r
- UINT64 Mmio64Base, Mmio64Size;\r
- UINT32 BusMin, BusMax;\r
- EFI_STATUS Status;\r
- UINT64 Attributes;\r
- UINT64 AllocationAttributes;\r
- PCI_ROOT_BRIDGE_APERTURE Io;\r
- PCI_ROOT_BRIDGE_APERTURE Mem;\r
- PCI_ROOT_BRIDGE_APERTURE MemAbove4G;\r
- PCI_ROOT_BRIDGE_APERTURE PMem;\r
- PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;\r
+ UINT64 IoBase, IoSize;\r
+ UINT64 Mmio32Base, Mmio32Size;\r
+ UINT64 Mmio64Base, Mmio64Size;\r
+ UINT32 BusMin, BusMax;\r
+ EFI_STATUS Status;\r
+ UINT64 Attributes;\r
+ UINT64 AllocationAttributes;\r
+ PCI_ROOT_BRIDGE_APERTURE Io;\r
+ PCI_ROOT_BRIDGE_APERTURE Mem;\r
+ PCI_ROOT_BRIDGE_APERTURE MemAbove4G;\r
+ PCI_ROOT_BRIDGE_APERTURE PMem;\r
+ PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;\r
\r
if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {\r
DEBUG ((DEBUG_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));\r
return NULL;\r
}\r
\r
- Status = ProcessPciHost (&IoBase, &IoSize, &Mmio32Base, &Mmio32Size,\r
- &Mmio64Base, &Mmio64Size, &BusMin, &BusMax);\r
+ Status = ProcessPciHost (\r
+ &IoBase,\r
+ &IoSize,\r
+ &Mmio32Base,\r
+ &Mmio32Size,\r
+ &Mmio64Base,\r
+ &Mmio64Size,\r
+ &BusMin,\r
+ &BusMax\r
+ );\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "%a: failed to discover PCI host bridge: %r\n",\r
- __FUNCTION__, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: failed to discover PCI host bridge: %r\n",\r
+ __FUNCTION__,\r
+ Status\r
+ ));\r
*Count = 0;\r
return NULL;\r
}\r
ZeroMem (&PMem, sizeof (PMem));\r
ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));\r
\r
- Attributes = EFI_PCI_ATTRIBUTE_ISA_IO_16 |\r
- EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |\r
- EFI_PCI_ATTRIBUTE_VGA_IO_16 |\r
- EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ Attributes = EFI_PCI_ATTRIBUTE_ISA_IO_16 |\r
+ EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |\r
+ EFI_PCI_ATTRIBUTE_VGA_IO_16 |\r
+ EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
\r
AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;\r
\r
- Io.Base = IoBase;\r
- Io.Limit = IoBase + IoSize - 1;\r
- Mem.Base = Mmio32Base;\r
- Mem.Limit = Mmio32Base + Mmio32Size - 1;\r
+ Io.Base = IoBase;\r
+ Io.Limit = IoBase + IoSize - 1;\r
+ Mem.Base = Mmio32Base;\r
+ Mem.Limit = Mmio32Base + Mmio32Size - 1;\r
\r
if (sizeof (UINTN) == sizeof (UINT64)) {\r
- MemAbove4G.Base = Mmio64Base;\r
- MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1;\r
+ MemAbove4G.Base = Mmio64Base;\r
+ MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1;\r
if (Mmio64Size > 0) {\r
AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;\r
}\r
// BARs unless they are allocated below 4 GB. So ignore the range above\r
// 4 GB in this case.\r
//\r
- MemAbove4G.Base = MAX_UINT64;\r
- MemAbove4G.Limit = 0;\r
+ MemAbove4G.Base = MAX_UINT64;\r
+ MemAbove4G.Limit = 0;\r
}\r
\r
//\r
// No separate ranges for prefetchable and non-prefetchable BARs\r
//\r
- PMem.Base = MAX_UINT64;\r
- PMem.Limit = 0;\r
- PMemAbove4G.Base = MAX_UINT64;\r
- PMemAbove4G.Limit = 0;\r
+ PMem.Base = MAX_UINT64;\r
+ PMem.Limit = 0;\r
+ PMemAbove4G.Base = MAX_UINT64;\r
+ PMemAbove4G.Limit = 0;\r
\r
return PciHostBridgeUtilityGetRootBridges (\r
- Count,\r
- Attributes,\r
- AllocationAttributes,\r
- TRUE,\r
- FALSE,\r
- BusMin,\r
- BusMax,\r
- &Io,\r
- &Mem,\r
- &MemAbove4G,\r
- &PMem,\r
- &PMemAbove4G\r
- );\r
+ Count,\r
+ Attributes,\r
+ AllocationAttributes,\r
+ TRUE,\r
+ FALSE,\r
+ BusMin,\r
+ BusMax,\r
+ &Io,\r
+ &Mem,\r
+ &MemAbove4G,\r
+ &PMem,\r
+ &PMemAbove4G\r
+ );\r
}\r
\r
/**\r
VOID\r
EFIAPI\r
PciHostBridgeFreeRootBridges (\r
- PCI_ROOT_BRIDGE *Bridges,\r
- UINTN Count\r
+ PCI_ROOT_BRIDGE *Bridges,\r
+ UINTN Count\r
)\r
{\r
PciHostBridgeUtilityFreeRootBridges (Bridges, Count);\r
VOID\r
EFIAPI\r
PciHostBridgeResourceConflict (\r
- EFI_HANDLE HostBridgeHandle,\r
- VOID *Configuration\r
+ EFI_HANDLE HostBridgeHandle,\r
+ VOID *Configuration\r
)\r
{\r
PciHostBridgeUtilityResourceConflict (Configuration);\r
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