//\r
// Host Bridge Device ID (DID) value for I440FX\r
//\r
-#define INTEL_82441_DEVICE_ID 0x1237\r
+#define INTEL_82441_DEVICE_ID 0x1237\r
\r
//\r
// B/D/F/Type: 0/0/0/PCI\r
//\r
-#define PMC_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r
+#define PMC_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r
\r
-#define PIIX4_PAM0 0x59\r
-#define PIIX4_PAM1 0x5A\r
-#define PIIX4_PAM2 0x5B\r
-#define PIIX4_PAM3 0x5C\r
-#define PIIX4_PAM4 0x5D\r
-#define PIIX4_PAM5 0x5E\r
-#define PIIX4_PAM6 0x5F\r
+#define PIIX4_PAM0 0x59\r
+#define PIIX4_PAM1 0x5A\r
+#define PIIX4_PAM2 0x5B\r
+#define PIIX4_PAM3 0x5C\r
+#define PIIX4_PAM4 0x5D\r
+#define PIIX4_PAM5 0x5E\r
+#define PIIX4_PAM6 0x5F\r
\r
//\r
// B/D/F/Type: 0/1/3/PCI\r
//\r
-#define POWER_MGMT_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 1, 3, (Offset))\r
+#define POWER_MGMT_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 1, 3, (Offset))\r
\r
-#define PIIX4_PMBA 0x40\r
-#define PIIX4_PMBA_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \\r
+#define PIIX4_PMBA 0x40\r
+#define PIIX4_PMBA_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \\r
BIT10 | BIT9 | BIT8 | BIT7 | BIT6)\r
\r
-#define PIIX4_PMREGMISC 0x80\r
-#define PIIX4_PMREGMISC_PMIOSE BIT0\r
+#define PIIX4_PMREGMISC 0x80\r
+#define PIIX4_PMREGMISC_PMIOSE BIT0\r
\r
//\r
// IO ports\r
//\r
-#define PIIX4_CPU_HOTPLUG_BASE 0xAF00\r
+#define PIIX4_CPU_HOTPLUG_BASE 0xAF00\r
\r
#endif\r