OvmfPkg: Apply uncrustify changes

[mirror_edk2.git] / OvmfPkg / Include / IndustryStandard / PageTable.h

diff --git a/OvmfPkg/Include/IndustryStandard/PageTable.h b/OvmfPkg/Include/IndustryStandard/PageTable.h
index 5e797eeea8ef76dd5573bc6de0e5073f9ab40194..a75b3fcfe7fe0dbcf8aff3d832d5c1b245daaa4e 100644 (file)
--- a/OvmfPkg/Include/IndustryStandard/PageTable.h
+++ b/OvmfPkg/Include/IndustryStandard/PageTable.h
@@ -25,21 +25,21 @@
 \r
 typedef union {\r
   struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory,\r
-                                      //   1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
-                                      //   1 = Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed,\r
-                                      //   1 = Accessed (set by CPU)\r
-    UINT64  Reserved:1;               // Reserved\r
-    UINT64  MustBeZero:2;             // Must Be Zero\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // No Execute bit\r
+    UINT64    Present              : 1;  // 0 = Not present in memory,\r
+                                         //   1 = Present in memory\r
+    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
+    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
+    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching,\r
+                                         //   1 = Write-Through caching\r
+    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
+    UINT64    Accessed             : 1;  // 0 = Not accessed,\r
+                                         //   1 = Accessed (set by CPU)\r
+    UINT64    Reserved             : 1;  // Reserved\r
+    UINT64    MustBeZero           : 2;  // Must Be Zero\r
+    UINT64    Available            : 3;  // Available for use by system software\r
+    UINT64    PageTableBaseAddress : 40; // Page Table Base Address\r
+    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
+    UINT64    Nx                   : 1;  // No Execute bit\r
   } Bits;\r
   UINT64    Uint64;\r
 } PAGE_MAP_AND_DIRECTORY_POINTER;\r
@@ -49,25 +49,25 @@ typedef union {
 //\r
 typedef union {\r
   struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory,\r
-                                      //   1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
-                                      //   1 = Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed,\r
-                                      //   1 = Accessed (set by CPU)\r
-    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by\r
-                                      //   processor on access to page\r
-    UINT64  PAT:1;                    //\r
-    UINT64  Global:1;                 // 0 = Not global page, 1 = global page\r
-                                      //   TLB not cleared on CR3 write\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // 0 = Execute Code,\r
-                                      //   1 = No Code Execution\r
+    UINT64    Present              : 1;  // 0 = Not present in memory,\r
+                                         //   1 = Present in memory\r
+    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
+    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
+    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching,\r
+                                         //   1 = Write-Through caching\r
+    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
+    UINT64    Accessed             : 1;  // 0 = Not accessed,\r
+                                         //   1 = Accessed (set by CPU)\r
+    UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by\r
+                                         //   processor on access to page\r
+    UINT64    PAT                  : 1;  //\r
+    UINT64    Global               : 1;  // 0 = Not global page, 1 = global page\r
+                                         //   TLB not cleared on CR3 write\r
+    UINT64    Available            : 3;  // Available for use by system software\r
+    UINT64    PageTableBaseAddress : 40; // Page Table Base Address\r
+    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
+    UINT64    Nx                   : 1;  // 0 = Execute Code,\r
+                                         //   1 = No Code Execution\r
   } Bits;\r
   UINT64    Uint64;\r
 } PAGE_TABLE_4K_ENTRY;\r
@@ -77,27 +77,27 @@ typedef union {
 //\r
 typedef union {\r
   struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory,\r
-                                      //   1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
-                                      //   1=Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed,\r
-                                      //   1 = Accessed (set by CPU)\r
-    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by\r
-                                      //   processor on access to page\r
-    UINT64  MustBe1:1;                // Must be 1\r
-    UINT64  Global:1;                 // 0 = Not global page, 1 = global page\r
-                                      //   TLB not cleared on CR3 write\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PAT:1;                    //\r
-    UINT64  MustBeZero:8;             // Must be zero;\r
-    UINT64  PageTableBaseAddress:31;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // 0 = Execute Code,\r
-                                      //   1 = No Code Execution\r
+    UINT64    Present              : 1;  // 0 = Not present in memory,\r
+                                         //   1 = Present in memory\r
+    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
+    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
+    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching,\r
+                                         //   1=Write-Through caching\r
+    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
+    UINT64    Accessed             : 1;  // 0 = Not accessed,\r
+                                         //   1 = Accessed (set by CPU)\r
+    UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by\r
+                                         //   processor on access to page\r
+    UINT64    MustBe1              : 1;  // Must be 1\r
+    UINT64    Global               : 1;  // 0 = Not global page, 1 = global page\r
+                                         //   TLB not cleared on CR3 write\r
+    UINT64    Available            : 3;  // Available for use by system software\r
+    UINT64    PAT                  : 1;  //\r
+    UINT64    MustBeZero           : 8;  // Must be zero;\r
+    UINT64    PageTableBaseAddress : 31; // Page Table Base Address\r
+    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
+    UINT64    Nx                   : 1;  // 0 = Execute Code,\r
+                                         //   1 = No Code Execution\r
   } Bits;\r
   UINT64    Uint64;\r
 } PAGE_TABLE_ENTRY;\r
@@ -107,55 +107,55 @@ typedef union {
 //\r
 typedef union {\r
   struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory,\r
-                                      //   1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
-                                      //   1 = Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed,\r
-                                      //   1 = Accessed (set by CPU)\r
-    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by\r
-                                      //   processor on access to page\r
-    UINT64  MustBe1:1;                // Must be 1\r
-    UINT64  Global:1;                 // 0 = Not global page, 1 = global page\r
-                                      //   TLB not cleared on CR3 write\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PAT:1;                    //\r
-    UINT64  MustBeZero:17;            // Must be zero;\r
-    UINT64  PageTableBaseAddress:22;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // 0 = Execute Code,\r
-                                      //   1 = No Code Execution\r
+    UINT64    Present              : 1;  // 0 = Not present in memory,\r
+                                         //   1 = Present in memory\r
+    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
+    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
+    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching,\r
+                                         //   1 = Write-Through caching\r
+    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
+    UINT64    Accessed             : 1;  // 0 = Not accessed,\r
+                                         //   1 = Accessed (set by CPU)\r
+    UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by\r
+                                         //   processor on access to page\r
+    UINT64    MustBe1              : 1;  // Must be 1\r
+    UINT64    Global               : 1;  // 0 = Not global page, 1 = global page\r
+                                         //   TLB not cleared on CR3 write\r
+    UINT64    Available            : 3;  // Available for use by system software\r
+    UINT64    PAT                  : 1;  //\r
+    UINT64    MustBeZero           : 17; // Must be zero;\r
+    UINT64    PageTableBaseAddress : 22; // Page Table Base Address\r
+    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
+    UINT64    Nx                   : 1;  // 0 = Execute Code,\r
+                                         //   1 = No Code Execution\r
   } Bits;\r
   UINT64    Uint64;\r
 } PAGE_TABLE_1G_ENTRY;\r
 \r
 #pragma pack()\r
 \r
-#define IA32_PG_P                   BIT0\r
-#define IA32_PG_RW                  BIT1\r
-#define IA32_PG_PS                  BIT7\r
+#define IA32_PG_P   BIT0\r
+#define IA32_PG_RW  BIT1\r
+#define IA32_PG_PS  BIT7\r
 \r
-#define PAGING_PAE_INDEX_MASK       0x1FF\r
+#define PAGING_PAE_INDEX_MASK  0x1FF\r
 \r
-#define PAGING_4K_ADDRESS_MASK_64   0x000FFFFFFFFFF000ull\r
-#define PAGING_2M_ADDRESS_MASK_64   0x000FFFFFFFE00000ull\r
-#define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
+#define PAGING_4K_ADDRESS_MASK_64  0x000FFFFFFFFFF000ull\r
+#define PAGING_2M_ADDRESS_MASK_64  0x000FFFFFFFE00000ull\r
+#define PAGING_1G_ADDRESS_MASK_64  0x000FFFFFC0000000ull\r
 \r
-#define PAGING_L1_ADDRESS_SHIFT     12\r
-#define PAGING_L2_ADDRESS_SHIFT     21\r
-#define PAGING_L3_ADDRESS_SHIFT     30\r
-#define PAGING_L4_ADDRESS_SHIFT     39\r
+#define PAGING_L1_ADDRESS_SHIFT  12\r
+#define PAGING_L2_ADDRESS_SHIFT  21\r
+#define PAGING_L3_ADDRESS_SHIFT  30\r
+#define PAGING_L4_ADDRESS_SHIFT  39\r
 \r
-#define PAGING_PML4E_NUMBER         4\r
+#define PAGING_PML4E_NUMBER  4\r
 \r
-#define PAGETABLE_ENTRY_MASK        ((1UL << 9) - 1)\r
-#define PML4_OFFSET(x)              ( (x >> 39) & PAGETABLE_ENTRY_MASK)\r
-#define PDP_OFFSET(x)               ( (x >> 30) & PAGETABLE_ENTRY_MASK)\r
-#define PDE_OFFSET(x)               ( (x >> 21) & PAGETABLE_ENTRY_MASK)\r
-#define PTE_OFFSET(x)               ( (x >> 12) & PAGETABLE_ENTRY_MASK)\r
-#define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
+#define PAGETABLE_ENTRY_MASK  ((1UL << 9) - 1)\r
+#define PML4_OFFSET(x)  ( (x >> 39) & PAGETABLE_ENTRY_MASK)\r
+#define PDP_OFFSET(x)   ( (x >> 30) & PAGETABLE_ENTRY_MASK)\r
+#define PDE_OFFSET(x)   ( (x >> 21) & PAGETABLE_ENTRY_MASK)\r
+#define PTE_OFFSET(x)   ( (x >> 12) & PAGETABLE_ENTRY_MASK)\r
+#define PAGING_1G_ADDRESS_MASK_64  0x000FFFFFC0000000ull\r
 \r
 #endif\r