#define MCH_PCIEXBAR_HIGH 0x64\r
#define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0\r
\r
+#define MCH_PAM0 0x90\r
+#define MCH_PAM1 0x91\r
+#define MCH_PAM2 0x92\r
+#define MCH_PAM3 0x93\r
+#define MCH_PAM4 0x94\r
+#define MCH_PAM5 0x95\r
+#define MCH_PAM6 0x96\r
+\r
#define MCH_SMRAM 0x9D\r
#define MCH_SMRAM_D_LCK BIT4\r
#define MCH_SMRAM_G_SMRAME BIT3\r