UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / OvmfPkg / Include / IndustryStandard / Q35MchIch9.h

diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
index 4dc2c39901c13523660e4adf3a446ef82f646b66..db828d31b35db53a1de328aa6091257ce18da84b 100644 (file)
--- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
+++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
@@ -6,68 +6,83 @@
   Copyright (C) 2015, Red Hat, Inc.\r
   Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>\r
 \r
-  This program and the accompanying materials are licensed and made available\r
-  under the terms and conditions of the BSD License which accompanies this\r
-  distribution.   The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
-  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 **/\r
 \r
 #ifndef __Q35_MCH_ICH9_H__\r
 #define __Q35_MCH_ICH9_H__\r
 \r
 #include <Library/PciLib.h>\r
+#include <Uefi/UefiBaseType.h>\r
+#include <Uefi/UefiSpec.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
 \r
 //\r
 // Host Bridge Device ID (DID) value for Q35/MCH\r
 //\r
-#define INTEL_Q35_MCH_DEVICE_ID 0x29C0\r
+#define INTEL_Q35_MCH_DEVICE_ID  0x29C0\r
 \r
 //\r
 // B/D/F/Type: 0/0/0/PCI\r
 //\r
-#define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r
-\r
-#define MCH_GGC               0x52\r
-#define MCH_GGC_IVD             BIT1\r
-\r
-#define MCH_PCIEXBAR_LOW      0x60\r
-#define MCH_PCIEXBAR_LOWMASK    0x0FFFFFFF\r
-#define MCH_PCIEXBAR_BUS_FF     0\r
-#define MCH_PCIEXBAR_EN         BIT0\r
-\r
-#define MCH_PCIEXBAR_HIGH     0x64\r
-#define MCH_PCIEXBAR_HIGHMASK   0xFFFFFFF0\r
-\r
-#define MCH_SMRAM             0x9D\r
-#define MCH_SMRAM_D_LCK         BIT4\r
-#define MCH_SMRAM_G_SMRAME      BIT3\r
+#define DRAMC_REGISTER_Q35(Offset)  PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r
 \r
-#define MCH_ESMRAMC           0x9E\r
-#define MCH_ESMRAMC_H_SMRAME    BIT7\r
-#define MCH_ESMRAMC_E_SMERR     BIT6\r
-#define MCH_ESMRAMC_SM_CACHE    BIT5\r
-#define MCH_ESMRAMC_SM_L1       BIT4\r
-#define MCH_ESMRAMC_SM_L2       BIT3\r
-#define MCH_ESMRAMC_TSEG_8MB    BIT2\r
-#define MCH_ESMRAMC_TSEG_2MB    BIT1\r
-#define MCH_ESMRAMC_TSEG_1MB    0\r
-#define MCH_ESMRAMC_TSEG_MASK   (BIT2 | BIT1)\r
-#define MCH_ESMRAMC_T_EN        BIT0\r
+#define MCH_EXT_TSEG_MB        0x50\r
+#define MCH_EXT_TSEG_MB_QUERY  0xFFFF\r
 \r
-#define MCH_GBSM              0xA4\r
-#define MCH_GBSM_MB_SHIFT       20\r
+#define MCH_GGC      0x52\r
+#define MCH_GGC_IVD  BIT1\r
 \r
-#define MCH_BGSM              0xA8\r
-#define MCH_BGSM_MB_SHIFT       20\r
-\r
-#define MCH_TSEGMB            0xAC\r
-#define MCH_TSEGMB_MB_SHIFT     20\r
-\r
-#define MCH_TOLUD             0xB0\r
-#define MCH_TOLUD_MB_SHIFT      4\r
+#define MCH_PCIEXBAR_LOW      0x60\r
+#define MCH_PCIEXBAR_LOWMASK  0x0FFFFFFF\r
+#define MCH_PCIEXBAR_BUS_FF   0\r
+#define MCH_PCIEXBAR_EN       BIT0\r
+\r
+#define MCH_PCIEXBAR_HIGH      0x64\r
+#define MCH_PCIEXBAR_HIGHMASK  0xFFFFFFF0\r
+\r
+#define MCH_PAM0  0x90\r
+#define MCH_PAM1  0x91\r
+#define MCH_PAM2  0x92\r
+#define MCH_PAM3  0x93\r
+#define MCH_PAM4  0x94\r
+#define MCH_PAM5  0x95\r
+#define MCH_PAM6  0x96\r
+\r
+#define MCH_DEFAULT_SMBASE_CTL     0x9C\r
+#define MCH_DEFAULT_SMBASE_QUERY   0xFF\r
+#define MCH_DEFAULT_SMBASE_IN_RAM  0x01\r
+#define MCH_DEFAULT_SMBASE_LCK     0x02\r
+#define MCH_DEFAULT_SMBASE_SIZE    SIZE_128KB\r
+\r
+#define MCH_SMRAM           0x9D\r
+#define MCH_SMRAM_D_LCK     BIT4\r
+#define MCH_SMRAM_G_SMRAME  BIT3\r
+\r
+#define MCH_ESMRAMC            0x9E\r
+#define MCH_ESMRAMC_H_SMRAME   BIT7\r
+#define MCH_ESMRAMC_E_SMERR    BIT6\r
+#define MCH_ESMRAMC_SM_CACHE   BIT5\r
+#define MCH_ESMRAMC_SM_L1      BIT4\r
+#define MCH_ESMRAMC_SM_L2      BIT3\r
+#define MCH_ESMRAMC_TSEG_EXT   (BIT2 | BIT1)\r
+#define MCH_ESMRAMC_TSEG_8MB   BIT2\r
+#define MCH_ESMRAMC_TSEG_2MB   BIT1\r
+#define MCH_ESMRAMC_TSEG_1MB   0\r
+#define MCH_ESMRAMC_TSEG_MASK  (BIT2 | BIT1)\r
+#define MCH_ESMRAMC_T_EN       BIT0\r
+\r
+#define MCH_GBSM           0xA4\r
+#define MCH_GBSM_MB_SHIFT  20\r
+\r
+#define MCH_BGSM           0xA8\r
+#define MCH_BGSM_MB_SHIFT  20\r
+\r
+#define MCH_TSEGMB           0xAC\r
+#define MCH_TSEGMB_MB_SHIFT  20\r
+\r
+#define MCH_TOLUD           0xB0\r
+#define MCH_TOLUD_MB_SHIFT  4\r
 \r
 //\r
 // B/D/F/Type: 0/0x1f/0/PCI\r
@@ -75,32 +90,38 @@
 #define POWER_MGMT_REGISTER_Q35(Offset) \\r
   PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))\r
 \r
-#define ICH9_PMBASE               0x40\r
-#define ICH9_PMBASE_MASK            (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \\r
+#define POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS(Offset) \\r
+  EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset))\r
+\r
+#define ICH9_PMBASE       0x40\r
+#define ICH9_PMBASE_MASK  (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 |           \\r
                                      BIT10 | BIT9  | BIT8  | BIT7)\r
 \r
-#define ICH9_ACPI_CNTL            0x44\r
-#define ICH9_ACPI_CNTL_ACPI_EN      BIT7\r
+#define ICH9_ACPI_CNTL          0x44\r
+#define ICH9_ACPI_CNTL_ACPI_EN  BIT7\r
 \r
-#define ICH9_GEN_PMCON_1          0xA0\r
-#define ICH9_GEN_PMCON_1_SMI_LOCK   BIT4\r
+#define ICH9_GEN_PMCON_1           0xA0\r
+#define ICH9_GEN_PMCON_1_SMI_LOCK  BIT4\r
 \r
-#define ICH9_RCBA                 0xF0\r
-#define ICH9_RCBA_EN                BIT0\r
+#define ICH9_RCBA     0xF0\r
+#define ICH9_RCBA_EN  BIT0\r
 \r
 //\r
 // IO ports\r
 //\r
-#define ICH9_APM_CNT 0xB2\r
-#define ICH9_APM_STS 0xB3\r
+#define ICH9_APM_CNT              0xB2\r
+#define ICH9_APM_CNT_CPU_HOTPLUG  0x04\r
+#define ICH9_APM_STS              0xB3\r
+\r
+#define ICH9_CPU_HOTPLUG_BASE  0x0CD8\r
 \r
 //\r
 // IO ports relative to PMBASE\r
 //\r
-#define ICH9_PMBASE_OFS_SMI_EN 0x30\r
-#define ICH9_SMI_EN_APMC_EN      BIT5\r
-#define ICH9_SMI_EN_GBL_SMI_EN   BIT0\r
+#define ICH9_PMBASE_OFS_SMI_EN  0x30\r
+#define ICH9_SMI_EN_APMC_EN     BIT5\r
+#define ICH9_SMI_EN_GBL_SMI_EN  BIT0\r
 \r
-#define ICH9_ROOT_COMPLEX_BASE 0xFED1C000\r
+#define ICH9_ROOT_COMPLEX_BASE  0xFED1C000\r
 \r
 #endif\r