#include <Protocol/PciHostBridgeResourceAllocation.h> // EFI_PCI_HOST_BRIDGE...\r
#include <Protocol/PciRootBridgeIo.h> // EFI_PCI_ATTRIBUTE_I...\r
\r
-STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 };\r
-\r
+STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 };\r
\r
/**\r
Return all the root bridge instances in an array.\r
PCI_ROOT_BRIDGE *\r
EFIAPI\r
PciHostBridgeGetRootBridges (\r
- UINTN *Count\r
+ UINTN *Count\r
)\r
{\r
- UINT64 Attributes;\r
- UINT64 AllocationAttributes;\r
- PCI_ROOT_BRIDGE_APERTURE Io;\r
- PCI_ROOT_BRIDGE_APERTURE Mem;\r
- PCI_ROOT_BRIDGE_APERTURE MemAbove4G;\r
+ UINT64 Attributes;\r
+ UINT64 AllocationAttributes;\r
+ PCI_ROOT_BRIDGE_APERTURE Io;\r
+ PCI_ROOT_BRIDGE_APERTURE Mem;\r
+ PCI_ROOT_BRIDGE_APERTURE MemAbove4G;\r
\r
ZeroMem (&Io, sizeof (Io));\r
ZeroMem (&Mem, sizeof (Mem));\r
ZeroMem (&MemAbove4G, sizeof (MemAbove4G));\r
\r
Attributes = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |\r
- EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r
- EFI_PCI_ATTRIBUTE_ISA_IO_16 |\r
- EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |\r
- EFI_PCI_ATTRIBUTE_VGA_MEMORY |\r
- EFI_PCI_ATTRIBUTE_VGA_IO_16 |\r
- EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r
+ EFI_PCI_ATTRIBUTE_ISA_IO_16 |\r
+ EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |\r
+ EFI_PCI_ATTRIBUTE_VGA_MEMORY |\r
+ EFI_PCI_ATTRIBUTE_VGA_IO_16 |\r
+ EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
\r
AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;\r
if (PcdGet64 (PcdPciMmio64Size) > 0) {\r
AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;\r
- MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base);\r
- MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) +\r
- PcdGet64 (PcdPciMmio64Size) - 1;\r
+ MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base);\r
+ MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) +\r
+ PcdGet64 (PcdPciMmio64Size) - 1;\r
} else {\r
CopyMem (&MemAbove4G, &mNonExistAperture, sizeof (mNonExistAperture));\r
}\r
\r
- Io.Base = PcdGet64 (PcdPciIoBase);\r
- Io.Limit = PcdGet64 (PcdPciIoBase) + (PcdGet64 (PcdPciIoSize) - 1);\r
- Mem.Base = PcdGet64 (PcdPciMmio32Base);\r
+ Io.Base = PcdGet64 (PcdPciIoBase);\r
+ Io.Limit = PcdGet64 (PcdPciIoBase) + (PcdGet64 (PcdPciIoSize) - 1);\r
+ Mem.Base = PcdGet64 (PcdPciMmio32Base);\r
Mem.Limit = PcdGet64 (PcdPciMmio32Base) + (PcdGet64 (PcdPciMmio32Size) - 1);\r
\r
return PciHostBridgeUtilityGetRootBridges (\r
- Count,\r
- Attributes,\r
- AllocationAttributes,\r
- FALSE,\r
- PcdGet16 (PcdOvmfHostBridgePciDevId) != INTEL_Q35_MCH_DEVICE_ID,\r
- 0,\r
- PCI_MAX_BUS,\r
- &Io,\r
- &Mem,\r
- &MemAbove4G,\r
- &mNonExistAperture,\r
- &mNonExistAperture\r
- );\r
+ Count,\r
+ Attributes,\r
+ AllocationAttributes,\r
+ FALSE,\r
+ PcdGet16 (PcdOvmfHostBridgePciDevId) != INTEL_Q35_MCH_DEVICE_ID,\r
+ 0,\r
+ PCI_MAX_BUS,\r
+ &Io,\r
+ &Mem,\r
+ &MemAbove4G,\r
+ &mNonExistAperture,\r
+ &mNonExistAperture\r
+ );\r
}\r
\r
-\r
/**\r
Free the root bridge instances array returned from\r
PciHostBridgeGetRootBridges().\r
VOID\r
EFIAPI\r
PciHostBridgeFreeRootBridges (\r
- PCI_ROOT_BRIDGE *Bridges,\r
- UINTN Count\r
+ PCI_ROOT_BRIDGE *Bridges,\r
+ UINTN Count\r
)\r
{\r
PciHostBridgeUtilityFreeRootBridges (Bridges, Count);\r
}\r
\r
-\r
/**\r
Inform the platform that the resource conflict happens.\r
\r
VOID\r
EFIAPI\r
PciHostBridgeResourceConflict (\r
- EFI_HANDLE HostBridgeHandle,\r
- VOID *Configuration\r
+ EFI_HANDLE HostBridgeHandle,\r
+ VOID *Configuration\r
)\r
{\r
PciHostBridgeUtilityResourceConflict (Configuration);\r