STATIC\r
VOID\r
PcatPciRootBridgeBarExisted (\r
- IN UINTN Address,\r
- OUT UINT32 *OriginalValue,\r
- OUT UINT32 *Value\r
+ IN UINTN Address,\r
+ OUT UINT32 *OriginalValue,\r
+ OUT UINT32 *Value\r
)\r
{\r
//\r
EnableInterrupts ();\r
}\r
\r
-#define PCI_COMMAND_DECODE ((UINT16)(EFI_PCI_COMMAND_IO_SPACE | \\r
+#define PCI_COMMAND_DECODE ((UINT16)(EFI_PCI_COMMAND_IO_SPACE |\\r
EFI_PCI_COMMAND_MEMORY_SPACE))\r
STATIC\r
VOID\r
PcatPciRootBridgeDecodingDisable (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- UINT16 Value;\r
+ UINT16 Value;\r
\r
Value = PciRead16 (Address);\r
if (Value & PCI_COMMAND_DECODE) {\r
STATIC\r
VOID\r
PcatPciRootBridgeParseBars (\r
- IN UINT16 Command,\r
- IN UINTN Bus,\r
- IN UINTN Device,\r
- IN UINTN Function,\r
- IN UINTN BarOffsetBase,\r
- IN UINTN BarOffsetEnd,\r
- IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
- IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
- IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G\r
-\r
-)\r
+ IN UINT16 Command,\r
+ IN UINTN Bus,\r
+ IN UINTN Device,\r
+ IN UINTN Function,\r
+ IN UINTN BarOffsetBase,\r
+ IN UINTN BarOffsetEnd,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G\r
+\r
+ )\r
{\r
- UINT32 OriginalValue;\r
- UINT32 Value;\r
- UINT32 OriginalUpperValue;\r
- UINT32 UpperValue;\r
- UINT64 Mask;\r
- UINTN Offset;\r
- UINT64 Base;\r
- UINT64 Length;\r
- UINT64 Limit;\r
- PCI_ROOT_BRIDGE_APERTURE *MemAperture;\r
+ UINT32 OriginalValue;\r
+ UINT32 Value;\r
+ UINT32 OriginalUpperValue;\r
+ UINT32 UpperValue;\r
+ UINT64 Mask;\r
+ UINTN Offset;\r
+ UINT64 Base;\r
+ UINT64 Length;\r
+ UINT64 Limit;\r
+ PCI_ROOT_BRIDGE_APERTURE *MemAperture;\r
\r
// Disable address decoding for every device before OVMF starts sizing it\r
PcatPciRootBridgeDecodingDisable (\r
PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET)\r
- );\r
+ );\r
\r
for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {\r
PcatPciRootBridgeBarExisted (\r
PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
- &OriginalValue, &Value\r
- );\r
+ &OriginalValue,\r
+ &Value\r
+ );\r
if (Value == 0) {\r
continue;\r
}\r
+\r
if ((Value & BIT0) == BIT0) {\r
//\r
// IO Bar\r
//\r
if (Command & EFI_PCI_COMMAND_IO_SPACE) {\r
- Mask = 0xfffffffc;\r
- Base = OriginalValue & Mask;\r
+ Mask = 0xfffffffc;\r
+ Base = OriginalValue & Mask;\r
Length = ((~(Value & Mask)) & Mask) + 0x04;\r
if (!(Value & 0xFFFF0000)) {\r
Length &= 0x0000FFFF;\r
}\r
+\r
Limit = Base + Length - 1;\r
\r
if (Base < Limit) {\r
if (Io->Base > Base) {\r
Io->Base = Base;\r
}\r
+\r
if (Io->Limit < Limit) {\r
Io->Limit = Limit;\r
}\r
// Mem Bar\r
//\r
if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {\r
-\r
- Mask = 0xfffffff0;\r
- Base = OriginalValue & Mask;\r
+ Mask = 0xfffffff0;\r
+ Base = OriginalValue & Mask;\r
Length = Value & Mask;\r
\r
if ((Value & (BIT1 | BIT2)) == 0) {\r
PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
&OriginalUpperValue,\r
&UpperValue\r
- );\r
+ );\r
\r
- Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);\r
- Length = Length | LShiftU64 ((UINT64) UpperValue, 32);\r
+ Base = Base | LShiftU64 ((UINT64)OriginalUpperValue, 32);\r
+ Length = Length | LShiftU64 ((UINT64)UpperValue, 32);\r
Length = (~Length) + 1;\r
\r
if (Base < BASE_4GB) {\r
if (MemAperture->Base > Base) {\r
MemAperture->Base = Base;\r
}\r
+\r
if (MemAperture->Limit < Limit) {\r
MemAperture->Limit = Limit;\r
}\r
}\r
}\r
\r
-STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 };\r
+STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 };\r
\r
PCI_ROOT_BRIDGE *\r
ScanForRootBridges (\r
- UINTN *NumberOfRootBridges\r
+ UINTN *NumberOfRootBridges\r
)\r
{\r
- UINTN PrimaryBus;\r
- UINTN SubBus;\r
- UINT8 Device;\r
- UINT8 Function;\r
- UINTN NumberOfDevices;\r
- UINTN Address;\r
- PCI_TYPE01 Pci;\r
- UINT64 Attributes;\r
- UINT64 Base;\r
- UINT64 Limit;\r
- UINT64 Value;\r
- PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, *MemAperture;\r
- PCI_ROOT_BRIDGE *RootBridges;\r
- UINTN BarOffsetEnd;\r
-\r
+ UINTN PrimaryBus;\r
+ UINTN SubBus;\r
+ UINT8 Device;\r
+ UINT8 Function;\r
+ UINTN NumberOfDevices;\r
+ UINTN Address;\r
+ PCI_TYPE01 Pci;\r
+ UINT64 Attributes;\r
+ UINT64 Base;\r
+ UINT64 Limit;\r
+ UINT64 Value;\r
+ PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, *MemAperture;\r
+ PCI_ROOT_BRIDGE *RootBridges;\r
+ UINTN BarOffsetEnd;\r
\r
*NumberOfRootBridges = 0;\r
- RootBridges = NULL;\r
+ RootBridges = NULL;\r
\r
//\r
// After scanning all the PCI devices on the PCI root bridge's primary bus,\r
// root bridge's subordinate bus number + 1.\r
//\r
for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {\r
- SubBus = PrimaryBus;\r
+ SubBus = PrimaryBus;\r
Attributes = 0;\r
\r
ZeroMem (&Io, sizeof (Io));\r
// Scan all the PCI devices on the primary bus of the PCI root bridge\r
//\r
for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
-\r
for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {\r
-\r
//\r
// Compute the PCI configuration address of the PCI device to probe\r
//\r
// Get the I/O range that the PPB is decoding\r
//\r
Value = Pci.Bridge.IoBase & 0x0f;\r
- Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;\r
- Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;\r
+ Base = ((UINT32)Pci.Bridge.IoBase & 0xf0) << 8;\r
+ Limit = (((UINT32)Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;\r
if (Value == BIT0) {\r
- Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);\r
- Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);\r
+ Base |= ((UINT32)Pci.Bridge.IoBaseUpper16 << 16);\r
+ Limit |= ((UINT32)Pci.Bridge.IoLimitUpper16 << 16);\r
}\r
+\r
if (Base < Limit) {\r
if (Io.Base > Base) {\r
Io.Base = Base;\r
}\r
+\r
if (Io.Limit < Limit) {\r
Io.Limit = Limit;\r
}\r
//\r
// Get the Memory range that the PPB is decoding\r
//\r
- Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;\r
- Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;\r
+ Base = ((UINT32)Pci.Bridge.MemoryBase & 0xfff0) << 16;\r
+ Limit = (((UINT32)Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;\r
if (Base < Limit) {\r
if (Mem.Base > Base) {\r
Mem.Base = Base;\r
}\r
+\r
if (Mem.Limit < Limit) {\r
Mem.Limit = Limit;\r
}\r
// and merge it into Memory range\r
//\r
Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;\r
- Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;\r
- Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)\r
+ Base = ((UINT32)Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;\r
+ Limit = (((UINT32)Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)\r
<< 16) | 0xfffff;\r
MemAperture = &Mem;\r
if (Value == BIT0) {\r
- Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);\r
- Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);\r
+ Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);\r
+ Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);\r
MemAperture = &MemAbove4G;\r
}\r
+\r
if (Base < Limit) {\r
if (MemAperture->Base > Base) {\r
MemAperture->Base = Base;\r
}\r
+\r
if (MemAperture->Limit < Limit) {\r
MemAperture->Limit = Limit;\r
}\r
// Look at the PPB Configuration for legacy decoding attributes\r
//\r
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)\r
- == EFI_PCI_BRIDGE_CONTROL_ISA) {\r
+ == EFI_PCI_BRIDGE_CONTROL_ISA)\r
+ {\r
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
}\r
+\r
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)\r
- == EFI_PCI_BRIDGE_CONTROL_VGA) {\r
+ == EFI_PCI_BRIDGE_CONTROL_VGA)\r
+ {\r
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)\r
- != 0) {\r
+ != 0)\r
+ {\r
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
}\r
OFFSET_OF (PCI_TYPE00, Device.Bar),\r
BarOffsetEnd,\r
&Io,\r
- &Mem, &MemAbove4G\r
- );\r
+ &Mem,\r
+ &MemAbove4G\r
+ );\r
\r
//\r
// See if the PCI device is an IDE controller\r
//\r
- if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,\r
- PCI_CLASS_MASS_STORAGE_IDE)) {\r
+ if (IS_CLASS2 (\r
+ &Pci,\r
+ PCI_CLASS_MASS_STORAGE,\r
+ PCI_CLASS_MASS_STORAGE_IDE\r
+ ))\r
+ {\r
if (Pci.Hdr.ClassCode[0] & 0x80) {\r
Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
}\r
+\r
if (Pci.Hdr.ClassCode[0] & 0x01) {\r
Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
}\r
+\r
if (Pci.Hdr.ClassCode[0] & 0x04) {\r
Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
}\r
//\r
if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||\r
IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)\r
- ) {\r
+ )\r
+ {\r
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
// or ISA_POSITIVE_DECODE Bridge device\r
//\r
if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {\r
- if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||\r
- Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||\r
- Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {\r
+ if ((Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA) ||\r
+ (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA) ||\r
+ (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE))\r
+ {\r
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
// If this device is not a multi function device, then skip the rest\r
// of this PCI device\r
//\r
- if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
+ if ((Function == 0) && !IS_PCI_MULTI_FUNC (&Pci)) {\r
break;\r
}\r
}\r
//\r
if (NumberOfDevices > 0) {\r
RootBridges = ReallocatePool (\r
- (*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),\r
- (*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),\r
- RootBridges\r
- );\r
+ (*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),\r
+ (*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),\r
+ RootBridges\r
+ );\r
ASSERT (RootBridges != NULL);\r
PciHostBridgeUtilityInitRootBridge (\r
- Attributes, Attributes, 0,\r
- FALSE, TRUE /* NoExtendedConfigSpace */,\r
- (UINT8) PrimaryBus, (UINT8) SubBus,\r
- &Io, &Mem, &MemAbove4G, &mNonExistAperture, &mNonExistAperture,\r
+ Attributes,\r
+ Attributes,\r
+ 0,\r
+ FALSE,\r
+ TRUE /* NoExtendedConfigSpace */,\r
+ (UINT8)PrimaryBus,\r
+ (UINT8)SubBus,\r
+ &Io,\r
+ &Mem,\r
+ &MemAbove4G,\r
+ &mNonExistAperture,\r
+ &mNonExistAperture,\r
&RootBridges[*NumberOfRootBridges]\r
- );\r
+ );\r
RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;\r
//\r
// Increment the index for the next PCI Root Bridge\r
projects / mirror_edk2.git / blobdiff