//\r
// EFER register LMA bit\r
//\r
-#define LMA BIT10\r
+#define LMA BIT10\r
\r
/**\r
The constructor function\r
// Configure SMBASE.\r
//\r
CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(\r
- SMM_DEFAULT_SMBASE +\r
- SMRAM_SAVE_STATE_MAP_OFFSET\r
- );\r
+ SMM_DEFAULT_SMBASE +\r
+ SMRAM_SAVE_STATE_MAP_OFFSET\r
+ );\r
if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {\r
CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
} else {\r
IN UINT64 NewInstructionPointer\r
)\r
{\r
- UINT64 OriginalInstructionPointer;\r
- QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
+ UINT64 OriginalInstructionPointer;\r
+ QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
\r
CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;\r
if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r
OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;\r
- CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;\r
+ CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;\r
//\r
// Clear the auto HALT restart flag so the RSM instruction returns\r
// program control to the instruction following the HLT instruction.\r
} else {\r
CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer;\r
}\r
+\r
//\r
// Clear the auto HALT restart flag so the RSM instruction returns\r
// program control to the instruction following the HLT instruction.\r
CpuSaveState->x64.AutoHALTRestart &= ~BIT0;\r
}\r
}\r
+\r
return OriginalInstructionPointer;\r
}\r
\r
-STATIC CPU_HOT_EJECT_DATA *mCpuHotEjectData = NULL;\r
+STATIC CPU_HOT_EJECT_DATA *mCpuHotEjectData = NULL;\r
\r
/**\r
Initialize mCpuHotEjectData if PcdCpuMaxLogicalProcessorNumber > 1.\r
\r
if (RETURN_ERROR (SafeUintnMult (MaxNumberOfCpus, sizeof (UINT64), &Size)) ||\r
RETURN_ERROR (SafeUintnAdd (Size, sizeof (*mCpuHotEjectData), &Size)) ||\r
- RETURN_ERROR (SafeUintnAdd (Size, sizeof (UINT64) - 1, &Size))) {\r
+ RETURN_ERROR (SafeUintnAdd (Size, sizeof (UINT64) - 1, &Size)))\r
+ {\r
DEBUG ((DEBUG_ERROR, "%a: invalid CPU_HOT_EJECT_DATA\n", __FUNCTION__));\r
goto Fatal;\r
}\r
goto Fatal;\r
}\r
\r
- mCpuHotEjectData->Handler = NULL;\r
+ mCpuHotEjectData->Handler = NULL;\r
mCpuHotEjectData->ArrayLength = MaxNumberOfCpus;\r
\r
- mCpuHotEjectData->QemuSelectorMap = ALIGN_POINTER (mCpuHotEjectData + 1,\r
- sizeof (UINT64));\r
+ mCpuHotEjectData->QemuSelectorMap = ALIGN_POINTER (\r
+ mCpuHotEjectData + 1,\r
+ sizeof (UINT64)\r
+ );\r
//\r
// We use mCpuHotEjectData->QemuSelectorMap to map\r
// ProcessorNum -> QemuSelector. Initialize to invalid values.\r
//\r
// Expose address of CPU Hot eject Data structure\r
//\r
- PcdStatus = PcdSet64S (PcdCpuHotEjectDataAddress,\r
- (UINTN)(VOID *)mCpuHotEjectData);\r
+ PcdStatus = PcdSet64S (\r
+ PcdCpuHotEjectDataAddress,\r
+ (UINTN)(VOID *)mCpuHotEjectData\r
+ );\r
ASSERT_RETURN_ERROR (PcdStatus);\r
\r
return;\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN MapPagesBase;\r
- UINTN MapPagesCount;\r
-\r
+ EFI_STATUS Status;\r
+ UINTN MapPagesBase;\r
+ UINTN MapPagesCount;\r
\r
InitCpuHotEjectData ();\r
\r
MapPagesCount // NumPages\r
);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "%a: MemEncryptSevSetPageEncMask(): %r\n",\r
- __FUNCTION__, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: MemEncryptSevSetPageEncMask(): %r\n",\r
+ __FUNCTION__,\r
+ Status\r
+ ));\r
ASSERT (FALSE);\r
CpuDeadLoop ();\r
}\r
//\r
\r
if (mCpuHotEjectData != NULL) {\r
- CPU_HOT_EJECT_HANDLER Handler;\r
+ CPU_HOT_EJECT_HANDLER Handler;\r
\r
//\r
// As the comment above mentions, mCpuHotEjectData->Handler might be\r
// ordered-after the AllCpusInSync loop by using a MemoryFence() with\r
// acquire semantics.\r
//\r
- MemoryFence();\r
+ MemoryFence ();\r
\r
Handler = mCpuHotEjectData->Handler;\r
\r
/// Macro used to simplify the lookup table entries of type\r
/// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
///\r
-#define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)\r
+#define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)\r
\r
///\r
/// Macro used to simplify the lookup table entries of type\r
/// CPU_SMM_SAVE_STATE_REGISTER_RANGE\r
///\r
-#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }\r
+#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }\r
\r
///\r
/// Structure used to describe a range of registers\r
///\r
typedef struct {\r
- EFI_SMM_SAVE_STATE_REGISTER Start;\r
- EFI_SMM_SAVE_STATE_REGISTER End;\r
- UINTN Length;\r
+ EFI_SMM_SAVE_STATE_REGISTER Start;\r
+ EFI_SMM_SAVE_STATE_REGISTER End;\r
+ UINTN Length;\r
} CPU_SMM_SAVE_STATE_REGISTER_RANGE;\r
\r
///\r
/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value\r
///\r
\r
-#define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1\r
+#define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1\r
\r
typedef struct {\r
- UINT8 Width32;\r
- UINT8 Width64;\r
- UINT16 Offset32;\r
- UINT16 Offset64Lo;\r
- UINT16 Offset64Hi;\r
- BOOLEAN Writeable;\r
+ UINT8 Width32;\r
+ UINT8 Width64;\r
+ UINT16 Offset32;\r
+ UINT16 Offset64Lo;\r
+ UINT16 Offset64Hi;\r
+ BOOLEAN Writeable;\r
} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;\r
\r
///\r
/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER\r
/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
///\r
-STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {\r
+STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {\r
SMM_REGISTER_RANGE (\r
EFI_SMM_SAVE_STATE_REGISTER_GDTBASE,\r
EFI_SMM_SAVE_STATE_REGISTER_LDTINFO\r
EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,\r
EFI_SMM_SAVE_STATE_REGISTER_CR4\r
),\r
- { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }\r
+ { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0,0 }\r
};\r
\r
///\r
/// Lookup table used to retrieve the widths and offsets associated with each\r
/// supported EFI_SMM_SAVE_STATE_REGISTER value\r
///\r
-STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {\r
+STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {\r
{\r
0, // Width32\r
0, // Width64\r
\r
for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX;\r
mSmmCpuRegisterRanges[Index].Length != 0;\r
- Index++) {\r
- if (Register >= mSmmCpuRegisterRanges[Index].Start &&\r
- Register <= mSmmCpuRegisterRanges[Index].End) {\r
+ Index++)\r
+ {\r
+ if ((Register >= mSmmCpuRegisterRanges[Index].Start) &&\r
+ (Register <= mSmmCpuRegisterRanges[Index].End))\r
+ {\r
return Register - mSmmCpuRegisterRanges[Index].Start + Offset;\r
}\r
+\r
Offset += mSmmCpuRegisterRanges[Index].Length;\r
}\r
+\r
return 0;\r
}\r
\r
STATIC\r
EFI_STATUS\r
ReadSaveStateRegisterByIndex (\r
- IN UINTN CpuIndex,\r
- IN UINTN RegisterIndex,\r
- IN UINTN Width,\r
- OUT VOID *Buffer\r
+ IN UINTN CpuIndex,\r
+ IN UINTN RegisterIndex,\r
+ IN UINTN Width,\r
+ OUT VOID *Buffer\r
)\r
{\r
QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
//\r
// Write return buffer\r
//\r
- ASSERT(CpuSaveState != NULL);\r
+ ASSERT (CpuSaveState != NULL);\r
CopyMem (\r
Buffer,\r
(UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,\r
);\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
OUT VOID *Buffer\r
)\r
{\r
- UINTN RegisterIndex;\r
+ UINTN RegisterIndex;\r
QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
\r
//\r
IN CONST VOID *Buffer\r
)\r
{\r
- UINTN RegisterIndex;\r
+ UINTN RegisterIndex;\r
QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
\r
//\r
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
return EFI_INVALID_PARAMETER;\r
}\r
+\r
//\r
// Write SMM State register\r
//\r
);\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
VOID *\r
EFIAPI\r
SmmCpuFeaturesAllocatePageTableMemory (\r
- IN UINTN Pages\r
+ IN UINTN Pages\r
)\r
{\r
return NULL;\r
}\r
-\r
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