+ ## The 64-bit MMIO aperture shared by all PCI root bridges.\r
+ #\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27\r
+\r
+ ## The following setting controls how many megabytes we configure as TSEG on\r
+ # Q35, for SMRAM purposes. Permitted values are: 1, 2, 8. Other values cause\r
+ # undefined behavior.\r
+ #\r
+ # This PCD is only consulted if PcdSmmSmramRequire is TRUE (see below).\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20\r
+\r