OvmfPkg/PlatformPei Q35 SMM helpers: stop using mPlatformInfoHob

[mirror_edk2.git] / OvmfPkg / PlatformPei / MemDetect.c

diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index 2e47b132299042024809b1a1db7a5ba29156a616..b9207107b4d95e6b66fc1a90e7ff9c255e4e57e2 100644 (file)
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -41,13 +41,13 @@ Module Name:
 \r
 VOID\r
 Q35TsegMbytesInitialization (\r
-  VOID\r
+  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
   )\r
 {\r
   UINT16         ExtendedTsegMbytes;\r
   RETURN_STATUS  PcdStatus;\r
 \r
-  ASSERT (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
+  ASSERT (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
 \r
   //\r
   // Check if QEMU offers an extended TSEG.\r
@@ -68,7 +68,7 @@ Q35TsegMbytesInitialization (
   PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);\r
   ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));\r
   if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {\r
-    mPlatformInfoHob.Q35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);\r
+    PlatformInfoHob->Q35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);\r
     return;\r
   }\r
 \r
@@ -80,19 +80,19 @@ Q35TsegMbytesInitialization (
     ));\r
   PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);\r
   ASSERT_RETURN_ERROR (PcdStatus);\r
-  mPlatformInfoHob.Q35TsegMbytes = ExtendedTsegMbytes;\r
+  PlatformInfoHob->Q35TsegMbytes = ExtendedTsegMbytes;\r
 }\r
 \r
 VOID\r
 Q35SmramAtDefaultSmbaseInitialization (\r
-  VOID\r
+  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
   )\r
 {\r
   RETURN_STATUS  PcdStatus;\r
 \r
-  ASSERT (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
+  ASSERT (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
 \r
-  mPlatformInfoHob.Q35SmramAtDefaultSmbase = FALSE;\r
+  PlatformInfoHob->Q35SmramAtDefaultSmbase = FALSE;\r
   if (FeaturePcdGet (PcdCsmEnable)) {\r
     DEBUG ((\r
       DEBUG_INFO,\r
@@ -106,19 +106,19 @@ Q35SmramAtDefaultSmbaseInitialization (
     CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL);\r
     PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY);\r
     CtlRegVal                                = PciRead8 (CtlReg);\r
-    mPlatformInfoHob.Q35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==\r
+    PlatformInfoHob->Q35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==\r
                                                          MCH_DEFAULT_SMBASE_IN_RAM);\r
     DEBUG ((\r
       DEBUG_INFO,\r
       "%a: SMRAM at default SMBASE %a\n",\r
       __FUNCTION__,\r
-      mPlatformInfoHob.Q35SmramAtDefaultSmbase ? "found" : "not found"\r
+      PlatformInfoHob->Q35SmramAtDefaultSmbase ? "found" : "not found"\r
       ));\r
   }\r
 \r
   PcdStatus = PcdSetBoolS (\r
                 PcdQ35SmramAtDefaultSmbase,\r
-                mPlatformInfoHob.Q35SmramAtDefaultSmbase\r
+                PlatformInfoHob->Q35SmramAtDefaultSmbase\r
                 );\r
   ASSERT_RETURN_ERROR (PcdStatus);\r
 }\r