#include "Platform.h"\r
#include "Cmos.h"\r
\r
-UINT8 mPhysMemAddressWidth;\r
+UINT8 mPhysMemAddressWidth;\r
\r
-STATIC UINT32 mS3AcpiReservedMemoryBase;\r
-STATIC UINT32 mS3AcpiReservedMemorySize;\r
+STATIC UINT32 mS3AcpiReservedMemoryBase;\r
+STATIC UINT32 mS3AcpiReservedMemorySize;\r
\r
-STATIC UINT16 mQ35TsegMbytes;\r
+STATIC UINT16 mQ35TsegMbytes;\r
\r
-BOOLEAN mQ35SmramAtDefaultSmbase;\r
+BOOLEAN mQ35SmramAtDefaultSmbase;\r
\r
-UINT32 mQemuUc32Base;\r
+UINT32 mQemuUc32Base;\r
\r
VOID\r
Q35TsegMbytesInitialization (\r
VOID\r
)\r
{\r
- UINT16 ExtendedTsegMbytes;\r
- RETURN_STATUS PcdStatus;\r
+ UINT16 ExtendedTsegMbytes;\r
+ RETURN_STATUS PcdStatus;\r
\r
ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
\r
mQ35TsegMbytes = ExtendedTsegMbytes;\r
}\r
\r
-\r
VOID\r
Q35SmramAtDefaultSmbaseInitialization (\r
VOID\r
)\r
{\r
- RETURN_STATUS PcdStatus;\r
+ RETURN_STATUS PcdStatus;\r
\r
ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
\r
mQ35SmramAtDefaultSmbase = FALSE;\r
if (FeaturePcdGet (PcdCsmEnable)) {\r
- DEBUG ((DEBUG_INFO, "%a: SMRAM at default SMBASE not checked due to CSM\n",\r
- __FUNCTION__));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: SMRAM at default SMBASE not checked due to CSM\n",\r
+ __FUNCTION__\r
+ ));\r
} else {\r
- UINTN CtlReg;\r
- UINT8 CtlRegVal;\r
+ UINTN CtlReg;\r
+ UINT8 CtlRegVal;\r
\r
CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL);\r
PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY);\r
- CtlRegVal = PciRead8 (CtlReg);\r
+ CtlRegVal = PciRead8 (CtlReg);\r
mQ35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==\r
MCH_DEFAULT_SMBASE_IN_RAM);\r
- DEBUG ((DEBUG_INFO, "%a: SMRAM at default SMBASE %a\n", __FUNCTION__,\r
- mQ35SmramAtDefaultSmbase ? "found" : "not found"));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: SMRAM at default SMBASE %a\n",\r
+ __FUNCTION__,\r
+ mQ35SmramAtDefaultSmbase ? "found" : "not found"\r
+ ));\r
}\r
\r
- PcdStatus = PcdSetBoolS (PcdQ35SmramAtDefaultSmbase,\r
- mQ35SmramAtDefaultSmbase);\r
+ PcdStatus = PcdSetBoolS (\r
+ PcdQ35SmramAtDefaultSmbase,\r
+ mQ35SmramAtDefaultSmbase\r
+ );\r
ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
-\r
VOID\r
QemuUc32BaseInitialization (\r
VOID\r
)\r
{\r
- UINT32 LowerMemorySize;\r
- UINT32 Uc32Size;\r
+ UINT32 LowerMemorySize;\r
+ UINT32 Uc32Size;\r
\r
if (mHostBridgeDevId == 0xffff /* microvm */) {\r
return;\r
// while keeping the end affixed to 4GB. This will round the base up.\r
//\r
LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r
- Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));\r
- mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size);\r
+ Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));\r
+ mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size);\r
//\r
// Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.\r
// Therefore mQemuUc32Base is at least 2GB.\r
ASSERT (mQemuUc32Base >= BASE_2GB);\r
\r
if (mQemuUc32Base != LowerMemorySize) {\r
- DEBUG ((DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, for "\r
- "an UC32 size of 0x%x\n", __FUNCTION__, LowerMemorySize, mQemuUc32Base,\r
- Uc32Size));\r
+ DEBUG ((\r
+ DEBUG_VERBOSE,\r
+ "%a: rounded UC32 base from 0x%x up to 0x%x, for "\r
+ "an UC32 size of 0x%x\n",\r
+ __FUNCTION__,\r
+ LowerMemorySize,\r
+ mQemuUc32Base,\r
+ Uc32Size\r
+ ));\r
}\r
}\r
\r
-\r
/**\r
Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside\r
of the 32-bit address range.\r
STATIC\r
EFI_STATUS\r
ScanOrAdd64BitE820Ram (\r
- OUT UINT64 *MaxAddress OPTIONAL\r
+ OUT UINT64 *MaxAddress OPTIONAL\r
)\r
{\r
- EFI_STATUS Status;\r
- FIRMWARE_CONFIG_ITEM FwCfgItem;\r
- UINTN FwCfgSize;\r
- EFI_E820_ENTRY64 E820Entry;\r
- UINTN Processed;\r
+ EFI_STATUS Status;\r
+ FIRMWARE_CONFIG_ITEM FwCfgItem;\r
+ UINTN FwCfgSize;\r
+ EFI_E820_ENTRY64 E820Entry;\r
+ UINTN Processed;\r
\r
Status = QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
if (FwCfgSize % sizeof E820Entry != 0) {\r
return EFI_PROTOCOL_ERROR;\r
}\r
E820Entry.Length,\r
E820Entry.Type\r
));\r
- if (E820Entry.Type == EfiAcpiAddressRangeMemory &&\r
- E820Entry.BaseAddr >= BASE_4GB) {\r
+ if ((E820Entry.Type == EfiAcpiAddressRangeMemory) &&\r
+ (E820Entry.BaseAddr >= BASE_4GB))\r
+ {\r
if (MaxAddress == NULL) {\r
- UINT64 Base;\r
- UINT64 End;\r
+ UINT64 Base;\r
+ UINT64 End;\r
\r
//\r
// Round up the start address, and round down the end address.\r
//\r
Base = ALIGN_VALUE (E820Entry.BaseAddr, (UINT64)EFI_PAGE_SIZE);\r
- End = (E820Entry.BaseAddr + E820Entry.Length) &\r
- ~(UINT64)EFI_PAGE_MASK;\r
+ End = (E820Entry.BaseAddr + E820Entry.Length) &\r
+ ~(UINT64)EFI_PAGE_MASK;\r
if (Base < End) {\r
AddMemoryRangeHob (Base, End);\r
DEBUG ((\r
));\r
}\r
} else {\r
- UINT64 Candidate;\r
+ UINT64 Candidate;\r
\r
Candidate = E820Entry.BaseAddr + E820Entry.Length;\r
if (Candidate > *MaxAddress) {\r
}\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
-\r
UINT32\r
GetSystemMemorySizeBelow4gb (\r
VOID\r
)\r
{\r
- UINT8 Cmos0x34;\r
- UINT8 Cmos0x35;\r
+ UINT8 Cmos0x34;\r
+ UINT8 Cmos0x35;\r
\r
//\r
// CMOS 0x34/0x35 specifies the system memory above 16 MB.\r
// into the calculation to get the total memory size.\r
//\r
\r
- Cmos0x34 = (UINT8) CmosRead8 (0x34);\r
- Cmos0x35 = (UINT8) CmosRead8 (0x35);\r
+ Cmos0x34 = (UINT8)CmosRead8 (0x34);\r
+ Cmos0x35 = (UINT8)CmosRead8 (0x35);\r
\r
- return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r
+ return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r
}\r
\r
-\r
STATIC\r
UINT64\r
GetSystemMemorySizeAbove4gb (\r
)\r
{\r
- UINT32 Size;\r
- UINTN CmosIndex;\r
+ UINT32 Size;\r
+ UINTN CmosIndex;\r
\r
//\r
// CMOS 0x5b-0x5d specifies the system memory above 4GB MB.\r
\r
Size = 0;\r
for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {\r
- Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);\r
+ Size = (UINT32)(Size << 8) + (UINT32)CmosRead8 (CmosIndex);\r
}\r
\r
return LShiftU64 (Size, 16);\r
}\r
\r
-\r
/**\r
Return the highest address that DXE could possibly use, plus one.\r
**/\r
VOID\r
)\r
{\r
- UINT64 FirstNonAddress;\r
- UINT64 Pci64Base, Pci64Size;\r
- UINT32 FwCfgPciMmio64Mb;\r
- EFI_STATUS Status;\r
- FIRMWARE_CONFIG_ITEM FwCfgItem;\r
- UINTN FwCfgSize;\r
- UINT64 HotPlugMemoryEnd;\r
- RETURN_STATUS PcdStatus;\r
+ UINT64 FirstNonAddress;\r
+ UINT64 Pci64Base, Pci64Size;\r
+ UINT32 FwCfgPciMmio64Mb;\r
+ EFI_STATUS Status;\r
+ FIRMWARE_CONFIG_ITEM FwCfgItem;\r
+ UINTN FwCfgSize;\r
+ UINT64 HotPlugMemoryEnd;\r
+ RETURN_STATUS PcdStatus;\r
\r
//\r
// set FirstNonAddress to suppress incorrect compiler/analyzer warnings\r
// resources to 32-bit anyway. See DegradeResource() in\r
// "PciResourceSupport.c".\r
//\r
-#ifdef MDE_CPU_IA32\r
+ #ifdef MDE_CPU_IA32\r
if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
return FirstNonAddress;\r
}\r
-#endif\r
+\r
+ #endif\r
\r
//\r
// Otherwise, in order to calculate the highest address plus one, we must\r
// As signaled by the "X-" prefix, this knob is experimental, and might go\r
// away at any time.\r
//\r
- Status = QemuFwCfgParseUint32 ("opt/ovmf/X-PciMmio64Mb", FALSE,\r
- &FwCfgPciMmio64Mb);\r
+ Status = QemuFwCfgParseUint32 (\r
+ "opt/ovmf/X-PciMmio64Mb",\r
+ FALSE,\r
+ &FwCfgPciMmio64Mb\r
+ );\r
switch (Status) {\r
- case EFI_UNSUPPORTED:\r
- case EFI_NOT_FOUND:\r
- break;\r
- case EFI_SUCCESS:\r
- if (FwCfgPciMmio64Mb <= 0x1000000) {\r
- Pci64Size = LShiftU64 (FwCfgPciMmio64Mb, 20);\r
+ case EFI_UNSUPPORTED:\r
+ case EFI_NOT_FOUND:\r
break;\r
- }\r
+ case EFI_SUCCESS:\r
+ if (FwCfgPciMmio64Mb <= 0x1000000) {\r
+ Pci64Size = LShiftU64 (FwCfgPciMmio64Mb, 20);\r
+ break;\r
+ }\r
+\r
//\r
// fall through\r
//\r
- default:\r
- DEBUG ((DEBUG_WARN,\r
- "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",\r
- __FUNCTION__));\r
- break;\r
+ default:\r
+ DEBUG ((\r
+ DEBUG_WARN,\r
+ "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",\r
+ __FUNCTION__\r
+ ));\r
+ break;\r
}\r
\r
if (Pci64Size == 0) {\r
if (mBootMode != BOOT_ON_S3_RESUME) {\r
- DEBUG ((DEBUG_INFO, "%a: disabling 64-bit PCI host aperture\n",\r
- __FUNCTION__));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: disabling 64-bit PCI host aperture\n",\r
+ __FUNCTION__\r
+ ));\r
PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
// starts right at the end of the memory above 4GB. The 64-bit PCI host\r
// aperture must be placed above it.\r
//\r
- Status = QemuFwCfgFindFile ("etc/reserved-memory-end", &FwCfgItem,\r
- &FwCfgSize);\r
- if (!EFI_ERROR (Status) && FwCfgSize == sizeof HotPlugMemoryEnd) {\r
+ Status = QemuFwCfgFindFile (\r
+ "etc/reserved-memory-end",\r
+ &FwCfgItem,\r
+ &FwCfgSize\r
+ );\r
+ if (!EFI_ERROR (Status) && (FwCfgSize == sizeof HotPlugMemoryEnd)) {\r
QemuFwCfgSelectItem (FwCfgItem);\r
QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd);\r
- DEBUG ((DEBUG_VERBOSE, "%a: HotPlugMemoryEnd=0x%Lx\n", __FUNCTION__,\r
- HotPlugMemoryEnd));\r
+ DEBUG ((\r
+ DEBUG_VERBOSE,\r
+ "%a: HotPlugMemoryEnd=0x%Lx\n",\r
+ __FUNCTION__,\r
+ HotPlugMemoryEnd\r
+ ));\r
\r
ASSERT (HotPlugMemoryEnd >= FirstNonAddress);\r
FirstNonAddress = HotPlugMemoryEnd;\r
PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
\r
- DEBUG ((DEBUG_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r
- __FUNCTION__, Pci64Base, Pci64Size));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r
+ __FUNCTION__,\r
+ Pci64Base,\r
+ Pci64Size\r
+ ));\r
}\r
\r
//\r
return FirstNonAddress;\r
}\r
\r
-\r
/**\r
Initialize the mPhysMemAddressWidth variable, based on guest RAM size.\r
**/\r
VOID\r
)\r
{\r
- UINT64 FirstNonAddress;\r
+ UINT64 FirstNonAddress;\r
\r
//\r
// As guest-physical memory size grows, the permanent PEI RAM requirements\r
if (mPhysMemAddressWidth <= 36) {\r
mPhysMemAddressWidth = 36;\r
}\r
+\r
ASSERT (mPhysMemAddressWidth <= 48);\r
}\r
\r
-\r
/**\r
Calculate the cap for the permanent PEI memory.\r
**/\r
VOID\r
)\r
{\r
- BOOLEAN Page1GSupport;\r
- UINT32 RegEax;\r
- UINT32 RegEdx;\r
- UINT32 Pml4Entries;\r
- UINT32 PdpEntries;\r
- UINTN TotalPages;\r
+ BOOLEAN Page1GSupport;\r
+ UINT32 RegEax;\r
+ UINT32 RegEdx;\r
+ UINT32 Pml4Entries;\r
+ UINT32 PdpEntries;\r
+ UINTN TotalPages;\r
\r
//\r
// If DXE is 32-bit, then just return the traditional 64 MB cap.\r
//\r
-#ifdef MDE_CPU_IA32\r
+ #ifdef MDE_CPU_IA32\r
if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
return SIZE_64MB;\r
}\r
-#endif\r
+\r
+ #endif\r
\r
//\r
// Dependent on physical address width, PEI memory allocations can be\r
\r
if (mPhysMemAddressWidth <= 39) {\r
Pml4Entries = 1;\r
- PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r
+ PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r
ASSERT (PdpEntries <= 0x200);\r
} else {\r
Pml4Entries = 1 << (mPhysMemAddressWidth - 39);\r
}\r
\r
TotalPages = Page1GSupport ? Pml4Entries + 1 :\r
- (PdpEntries + 1) * Pml4Entries + 1;\r
+ (PdpEntries + 1) * Pml4Entries + 1;\r
ASSERT (TotalPages <= 0x40201);\r
\r
//\r
return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r
}\r
\r
-\r
/**\r
Publish PEI core memory\r
\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PHYSICAL_ADDRESS MemoryBase;\r
- UINT64 MemorySize;\r
- UINT32 LowerMemorySize;\r
- UINT32 PeiMemoryCap;\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS MemoryBase;\r
+ UINT64 MemorySize;\r
+ UINT32 LowerMemorySize;\r
+ UINT32 PeiMemoryCap;\r
\r
LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r
if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
//\r
if (mS3Supported) {\r
mS3AcpiReservedMemorySize = SIZE_512KB +\r
- mMaxCpuCount *\r
- PcdGet32 (PcdCpuApStackSize);\r
+ mMaxCpuCount *\r
+ PcdGet32 (PcdCpuApStackSize);\r
mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;\r
- LowerMemorySize = mS3AcpiReservedMemoryBase;\r
+ LowerMemorySize = mS3AcpiReservedMemoryBase;\r
}\r
\r
if (mBootMode == BOOT_ON_S3_RESUME) {\r
MemorySize = mS3AcpiReservedMemorySize;\r
} else {\r
PeiMemoryCap = GetPeiMemoryCap ();\r
- DEBUG ((DEBUG_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
- __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
+ __FUNCTION__,\r
+ mPhysMemAddressWidth,\r
+ PeiMemoryCap >> 10\r
+ ));\r
\r
//\r
// Determine the range of memory to use during PEI\r
// shouldn't overlap with that HOB.\r
//\r
MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?\r
- PcdGet32 (PcdOvmfDecompressionScratchEnd) :\r
- PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r
+ PcdGet32 (PcdOvmfDecompressionScratchEnd) :\r
+ PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r
MemorySize = LowerMemorySize - MemoryBase;\r
if (MemorySize > PeiMemoryCap) {\r
MemoryBase = LowerMemorySize - PeiMemoryCap;\r
//\r
// Publish this memory to the PEI Core\r
//\r
- Status = PublishSystemMemory(MemoryBase, MemorySize);\r
+ Status = PublishSystemMemory (MemoryBase, MemorySize);\r
ASSERT_EFI_ERROR (Status);\r
\r
return Status;\r
}\r
\r
-\r
STATIC\r
VOID\r
QemuInitializeRamBelow1gb (\r
{\r
if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {\r
AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE);\r
- AddReservedMemoryBaseSizeHob (SMM_DEFAULT_SMBASE, MCH_DEFAULT_SMBASE_SIZE,\r
- TRUE /* Cacheable */);\r
+ AddReservedMemoryBaseSizeHob (\r
+ SMM_DEFAULT_SMBASE,\r
+ MCH_DEFAULT_SMBASE_SIZE,\r
+ TRUE /* Cacheable */\r
+ );\r
STATIC_ASSERT (\r
SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128KB,\r
"end of SMRAM at default SMBASE ends at, or exceeds, 640KB"\r
);\r
- AddMemoryRangeHob (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE,\r
- BASE_512KB + BASE_128KB);\r
+ AddMemoryRangeHob (\r
+ SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE,\r
+ BASE_512KB + BASE_128KB\r
+ );\r
} else {\r
AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r
}\r
}\r
\r
-\r
/**\r
Peform Memory Detection for QEMU / KVM\r
\r
VOID\r
)\r
{\r
- UINT64 LowerMemorySize;\r
- UINT64 UpperMemorySize;\r
- MTRR_SETTINGS MtrrSettings;\r
- EFI_STATUS Status;\r
+ UINT64 LowerMemorySize;\r
+ UINT64 UpperMemorySize;\r
+ MTRR_SETTINGS MtrrSettings;\r
+ EFI_STATUS Status;\r
\r
DEBUG ((DEBUG_INFO, "%a called\n", __FUNCTION__));\r
\r
QemuInitializeRamBelow1gb ();\r
\r
if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
- UINT32 TsegSize;\r
+ UINT32 TsegSize;\r
\r
TsegSize = mQ35TsegMbytes * SIZE_1MB;\r
AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);\r
- AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize,\r
- TRUE);\r
+ AddReservedMemoryBaseSizeHob (\r
+ LowerMemorySize - TsegSize,\r
+ TsegSize,\r
+ TRUE\r
+ );\r
} else {\r
AddMemoryRangeHob (BASE_1MB, LowerMemorySize);\r
}\r
// memory size read from the CMOS.\r
//\r
Status = ScanOrAdd64BitE820Ram (NULL);\r
- if (EFI_ERROR (Status) && UpperMemorySize != 0) {\r
+ if (EFI_ERROR (Status) && (UpperMemorySize != 0)) {\r
AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);\r
}\r
}\r
//\r
// Set memory range from 640KB to 1MB to uncacheable\r
//\r
- Status = MtrrSetMemoryAttribute (BASE_512KB + BASE_128KB,\r
- BASE_1MB - (BASE_512KB + BASE_128KB), CacheUncacheable);\r
+ Status = MtrrSetMemoryAttribute (\r
+ BASE_512KB + BASE_128KB,\r
+ BASE_1MB - (BASE_512KB + BASE_128KB),\r
+ CacheUncacheable\r
+ );\r
ASSERT_EFI_ERROR (Status);\r
\r
//\r
// Set the memory range from the start of the 32-bit MMIO area (32-bit PCI\r
// MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.\r
//\r
- Status = MtrrSetMemoryAttribute (mQemuUc32Base, SIZE_4GB - mQemuUc32Base,\r
- CacheUncacheable);\r
+ Status = MtrrSetMemoryAttribute (\r
+ mQemuUc32Base,\r
+ SIZE_4GB - mQemuUc32Base,\r
+ CacheUncacheable\r
+ );\r
ASSERT_EFI_ERROR (Status);\r
}\r
}\r
{\r
QemuInitializeRam ();\r
\r
- if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {\r
+ if (mS3Supported && (mBootMode != BOOT_ON_S3_RESUME)) {\r
//\r
// This is the memory range that will be used for PEI on S3 resume\r
//\r
EfiACPIMemoryNVS\r
);\r
\r
-#ifdef MDE_CPU_X64\r
+ #ifdef MDE_CPU_X64\r
//\r
// Reserve the initial page tables built by the reset vector code.\r
//\r
// resume, it must be reserved as ACPI NVS.\r
//\r
BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecPageTablesBase),\r
- (UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize),\r
+ (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecPageTablesBase),\r
+ (UINT64)(UINTN)PcdGet32 (PcdOvmfSecPageTablesSize),\r
EfiACPIMemoryNVS\r
);\r
\r
// resume, it must be reserved as ACPI NVS.\r
//\r
BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecGhcbPageTableBase),\r
- (UINT64)(UINTN) PcdGet32 (PcdOvmfSecGhcbPageTableSize),\r
+ (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableBase),\r
+ (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableSize),\r
EfiACPIMemoryNVS\r
);\r
BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecGhcbBase),\r
- (UINT64)(UINTN) PcdGet32 (PcdOvmfSecGhcbSize),\r
+ (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBase),\r
+ (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbSize),\r
EfiACPIMemoryNVS\r
);\r
BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecGhcbBackupBase),\r
- (UINT64)(UINTN) PcdGet32 (PcdOvmfSecGhcbBackupSize),\r
+ (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupBase),\r
+ (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupSize),\r
EfiACPIMemoryNVS\r
);\r
}\r
-#endif\r
+\r
+ #endif\r
}\r
\r
if (mBootMode != BOOT_ON_S3_RESUME) {\r
// such that they would overlap the LockBox storage.\r
//\r
ZeroMem (\r
- (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r
- (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)\r
+ (VOID *)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),\r
+ (UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize)\r
);\r
BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r
- (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),\r
+ (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),\r
+ (UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize),\r
mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData\r
);\r
}\r
\r
if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
- UINT32 TsegSize;\r
+ UINT32 TsegSize;\r
\r
//\r
// Make sure the TSEG area that we reported as a reserved memory resource\r
//\r
TsegSize = mQ35TsegMbytes * SIZE_1MB;\r
BuildMemoryAllocationHob (\r
- GetSystemMemorySizeBelow4gb() - TsegSize,\r
+ GetSystemMemorySizeBelow4gb () - TsegSize,\r
TsegSize,\r
EfiReservedMemoryType\r
);\r
}\r
}\r
\r
-#ifdef MDE_CPU_X64\r
+ #ifdef MDE_CPU_X64\r
if (FixedPcdGet32 (PcdOvmfWorkAreaSize) != 0) {\r
//\r
// Reserve the work area.\r
// such that they would overlap the work area.\r
//\r
BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN) FixedPcdGet32 (PcdOvmfWorkAreaBase),\r
- (UINT64)(UINTN) FixedPcdGet32 (PcdOvmfWorkAreaSize),\r
+ (EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase),\r
+ (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize),\r
mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData\r
);\r
}\r
-#endif\r
+\r
+ #endif\r
}\r
}\r
projects / mirror_edk2.git / blobdiff